diff options
| author | Sonny Jiang <[email protected]> | 2015-11-12 12:34:37 -0500 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2015-12-07 21:58:42 +0100 |
| commit | 338d7bf0531a10d90db75ad333f7e0a31693641f (patch) | |
| tree | e99505c2921768dfa4d27448b44aeb8a8943b17a /src/gallium | |
| parent | 676bc2514039f8f631b1fcc0215aaa6647eda946 (diff) | |
winsys/amdgpu: addrlib - port Checks mip 0 for czDispCompatible
Signed-off-by: Sonny Jiang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp | 4 | ||||
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h | 3 |
2 files changed, 5 insertions, 2 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp b/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp index 110e3d007b8..088b64593ba 100644 --- a/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp +++ b/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp @@ -352,6 +352,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMicroTiled( ComputeSurfaceAlignmentsMicroTiled(expTileMode, pIn->bpp, pIn->flags, + pIn->mipLevel, numSamples, &pOut->baseAlign, &pOut->pitchAlign, @@ -647,6 +648,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsMicroTiled( AddrTileMode tileMode, ///< [in] tile mode UINT_32 bpp, ///< [in] bits per pixel ADDR_SURFACE_FLAGS flags, ///< [in] surface flags + UINT_32 mipLevel, ///< [in] mip level UINT_32 numSamples, ///< [in] number of samples UINT_32* pBaseAlign, ///< [out] base address alignment in bytes UINT_32* pPitchAlign, ///< [out] pitch alignment in pixels @@ -669,7 +671,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsMicroTiled( // ECR#393489 // Workaround 2 for 1D tiling - There is HW bug for Carrizo // where it requires the following alignments for 1D tiling. - if (flags.czDispCompatible) + if (flags.czDispCompatible && (mipLevel == 0)) { *pBaseAlign = PowTwoAlign(*pBaseAlign, 4096); //Base address MOD 4096 = 0 *pPitchAlign = PowTwoAlign(*pPitchAlign, 512 / (BITS_TO_BYTES(bpp))); //(8 lines * pitch * bytes per pixel) MOD 4096 = 0 diff --git a/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h b/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h index 84adb66eedc..25e38964be0 100644 --- a/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h +++ b/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h @@ -315,7 +315,8 @@ private: UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const; BOOL_32 ComputeSurfaceAlignmentsMicroTiled( - AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples, + AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, + UINT_32 mipLevel, UINT_32 numSamples, UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const; BOOL_32 ComputeSurfaceAlignmentsMacroTiled( |