iris: Spruce up "are we using this engine?" checks for flushing

We were using batch->contains_draw as a proxy for "are we even using
this engine?"  That isn't quite right, because it only counts regular
draws.  BLORP operations may have also rendered to a resource, which
needs to trigger flushing.  To check for this, we also see if the
render and sometimes depth caches are non-empty.

We can also drop the "but there might already be stale data in the
cache even if we haven't emitted any commands yet" concern in the
comments.  The kernel flushes caches between batches.

This may not be great but it's at least better than what was there.

2 files changed, 12 insertions, 12 deletions

diff --git a/src/gallium/drivers/iris/iris_pipe_control.c b/src/gallium/drivers/iris/iris_pipe_control.c
index 52e842bc661..3d12a5b0360 100644
--- a/src/gallium/drivers/iris/iris_pipe_control.c
+++ b/src/gallium/drivers/iris/iris_pipe_control.c
@@ -149,8 +149,12 @@ static void
 iris_texture_barrier(struct pipe_context *ctx, unsigned flags)
 {
    struct iris_context *ice = (void *) ctx;
+   struct iris_batch *render_batch = &ice->batches[IRIS_BATCH_RENDER];
+   struct iris_batch *compute_batch = &ice->batches[IRIS_BATCH_COMPUTE];
 
-   if (ice->batches[IRIS_BATCH_RENDER].contains_draw) {
+   if (render_batch->contains_draw ||
+       render_batch->cache.render->entries ||
+       render_batch->cache.depth->entries) {
       iris_emit_pipe_control_flush(&ice->batches[IRIS_BATCH_RENDER],
                                    PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                                    PIPE_CONTROL_RENDER_TARGET_FLUSH |
@@ -159,7 +163,7 @@ iris_texture_barrier(struct pipe_context *ctx, unsigned flags)
                                    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
    }
 
-   if (ice->batches[IRIS_BATCH_COMPUTE].contains_draw) {
+   if (compute_batch->contains_draw) {
       iris_emit_pipe_control_flush(&ice->batches[IRIS_BATCH_COMPUTE],
                                    PIPE_CONTROL_CS_STALL);
       iris_emit_pipe_control_flush(&ice->batches[IRIS_BATCH_COMPUTE],
@@ -189,11 +193,9 @@ iris_memory_barrier(struct pipe_context *ctx, unsigned flags)
               PIPE_CONTROL_RENDER_TARGET_FLUSH;
    }
 
-   // XXX: don't unconditionally emit flushes in both engines, we don't
-   // even know if we're even using e.g. the compute engine...
-
    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
-      if (ice->batches[i].contains_draw)
+      if (ice->batches[i].contains_draw ||
+          ice->batches[i].cache.render->entries)
          iris_emit_pipe_control_flush(&ice->batches[i], bits);
    }
 }
diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c
index b5829e94b36..03ce35462fa 100644
--- a/src/gallium/drivers/iris/iris_resource.c
+++ b/src/gallium/drivers/iris/iris_resource.c
@@ -1161,11 +1161,9 @@ iris_transfer_flush_region(struct pipe_context *ctx,
    struct iris_context *ice = (struct iris_context *)ctx;
    struct iris_resource *res = (struct iris_resource *) xfer->resource;
 
-
-   // XXX: don't emit flushes in both engines...? we may also need to flush
-   // even if there isn't a draw yet - may still be stale data in caches...
    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
-      if (ice->batches[i].contains_draw) {
+      if (ice->batches[i].contains_draw ||
+          ice->batches[i].cache.render->entries) {
          iris_batch_maybe_flush(&ice->batches[i], 24);
          iris_flush_and_dirty_for_history(ice, &ice->batches[i], res);
       }
@@ -1182,9 +1180,9 @@ iris_transfer_unmap(struct pipe_context *ctx, struct pipe_transfer *xfer)
    if (map->unmap)
       map->unmap(map);
 
-   // XXX: don't emit flushes in both engines...?
    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
-      if (ice->batches[i].contains_draw) {
+      if (ice->batches[i].contains_draw ||
+          ice->batches[i].cache.render->entries) {
          iris_batch_maybe_flush(&ice->batches[i], 24);
          iris_flush_and_dirty_for_history(ice, &ice->batches[i], res);
       }