diff options
| author | Marek Olšák <[email protected]> | 2019-07-17 23:29:22 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-07-23 15:03:47 -0400 |
| commit | 16392cc3f3ed5515bf143b956f03ae5bc4b24c52 (patch) | |
| tree | 7d2b490959e680175fa7bb573245d87e90ba5472 /src/gallium | |
| parent | ad642d5b3a8c6c366731bc26551c149e50b83c6c (diff) | |
radeonsi/gfx10: fix and enable CLEAR_STATE
it was a driver bug.
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_gfx_cs.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index 843f8206149..1560e3a2df3 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -508,6 +508,9 @@ void si_begin_new_gfx_cs(struct si_context *ctx) ctx->tracked_regs.reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN] = 0x00000000; ctx->tracked_regs.reg_value[SI_TRACKED_VGT_REUSE_OFF] = 0x00000000; ctx->tracked_regs.reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG] = 0x00000000; + ctx->tracked_regs.reg_value[SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP] = 0x00000000; + ctx->tracked_regs.reg_value[SI_TRACKED_GE_NGG_SUBGRP_CNTL] = 0x00000000; + ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_IDX_FORMAT] = 0x00000000; ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT] = 0x00000000; ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VTE_CNTL] = 0x00000000; ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_NGG_CNTL] = 0x00000000; diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 65cfe7f4878..96c71d91bd5 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1088,7 +1088,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws, * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc. * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. */ sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 && - sscreen->info.chip_class <= GFX9 && sscreen->info.is_amdgpu; sscreen->has_distributed_tess = |