ilo: update headers from i965

Mainly for MI_LOAD_REGISTER_IMM and BCS_SWCTRL.

5 files changed, 149 insertions, 54 deletions

diff --git a/src/gallium/drivers/ilo/ilo_screen.c b/src/gallium/drivers/ilo/ilo_screen.c
index 36132042156..66f2e8e6a06 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -470,44 +470,44 @@ ilo_get_name(struct pipe_screen *screen)
       break;
    case PCI_CHIP_HASWELL_GT1:
    case PCI_CHIP_HASWELL_GT2:
-   case PCI_CHIP_HASWELL_GT2_PLUS:
+   case PCI_CHIP_HASWELL_GT3:
    case PCI_CHIP_HASWELL_SDV_GT1:
    case PCI_CHIP_HASWELL_SDV_GT2:
-   case PCI_CHIP_HASWELL_SDV_GT2_PLUS:
+   case PCI_CHIP_HASWELL_SDV_GT3:
    case PCI_CHIP_HASWELL_ULT_GT1:
    case PCI_CHIP_HASWELL_ULT_GT2:
-   case PCI_CHIP_HASWELL_ULT_GT2_PLUS:
+   case PCI_CHIP_HASWELL_ULT_GT3:
    case PCI_CHIP_HASWELL_CRW_GT1:
    case PCI_CHIP_HASWELL_CRW_GT2:
-   case PCI_CHIP_HASWELL_CRW_GT2_PLUS:
+   case PCI_CHIP_HASWELL_CRW_GT3:
       chipset = "Intel(R) Haswell Desktop";
       break;
    case PCI_CHIP_HASWELL_M_GT1:
    case PCI_CHIP_HASWELL_M_GT2:
-   case PCI_CHIP_HASWELL_M_GT2_PLUS:
+   case PCI_CHIP_HASWELL_M_GT3:
    case PCI_CHIP_HASWELL_SDV_M_GT1:
    case PCI_CHIP_HASWELL_SDV_M_GT2:
-   case PCI_CHIP_HASWELL_SDV_M_GT2_PLUS:
+   case PCI_CHIP_HASWELL_SDV_M_GT3:
    case PCI_CHIP_HASWELL_ULT_M_GT1:
    case PCI_CHIP_HASWELL_ULT_M_GT2:
-   case PCI_CHIP_HASWELL_ULT_M_GT2_PLUS:
+   case PCI_CHIP_HASWELL_ULT_M_GT3:
    case PCI_CHIP_HASWELL_CRW_M_GT1:
    case PCI_CHIP_HASWELL_CRW_M_GT2:
-   case PCI_CHIP_HASWELL_CRW_M_GT2_PLUS:
+   case PCI_CHIP_HASWELL_CRW_M_GT3:
       chipset = "Intel(R) Haswell Mobile";
       break;
    case PCI_CHIP_HASWELL_S_GT1:
    case PCI_CHIP_HASWELL_S_GT2:
-   case PCI_CHIP_HASWELL_S_GT2_PLUS:
+   case PCI_CHIP_HASWELL_S_GT3:
    case PCI_CHIP_HASWELL_SDV_S_GT1:
    case PCI_CHIP_HASWELL_SDV_S_GT2:
-   case PCI_CHIP_HASWELL_SDV_S_GT2_PLUS:
+   case PCI_CHIP_HASWELL_SDV_S_GT3:
    case PCI_CHIP_HASWELL_ULT_S_GT1:
    case PCI_CHIP_HASWELL_ULT_S_GT2:
-   case PCI_CHIP_HASWELL_ULT_S_GT2_PLUS:
+   case PCI_CHIP_HASWELL_ULT_S_GT3:
    case PCI_CHIP_HASWELL_CRW_S_GT1:
    case PCI_CHIP_HASWELL_CRW_S_GT2:
-   case PCI_CHIP_HASWELL_CRW_S_GT2_PLUS:
+   case PCI_CHIP_HASWELL_CRW_S_GT3:
       chipset = "Intel(R) Haswell Server";
       break;
    default:
@@ -649,13 +649,17 @@ init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
    if (IS_HASWELL(info->devid)) {
       dev->gen = ILO_GEN(7.5);
 
-      if (IS_HSW_GT2(info->devid)) {
+      if (IS_HSW_GT3(info->devid)) {
+         dev->gt = 3;
+         dev->urb_size = 512 * 1024;
+      }
+      else if (IS_HSW_GT2(info->devid)) {
          dev->gt = 2;
-	 dev->urb_size = 256 * 1024;
+         dev->urb_size = 256 * 1024;
       }
       else {
          dev->gt = 1;
-	 dev->urb_size = 128 * 1024;
+         dev->urb_size = 128 * 1024;
       }
    }
    else if (IS_GEN7(info->devid)) {
@@ -663,11 +667,11 @@ init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
 
       if (IS_IVB_GT2(info->devid)) {
          dev->gt = 2;
-	 dev->urb_size = 256 * 1024;
+         dev->urb_size = 256 * 1024;
       }
       else {
          dev->gt = 1;
-	 dev->urb_size = 128 * 1024;
+         dev->urb_size = 128 * 1024;
       }
    }
    else if (IS_GEN6(info->devid)) {
diff --git a/src/gallium/drivers/ilo/include/brw_defines.h b/src/gallium/drivers/ilo/include/brw_defines.h
index 6517f243a0d..fedd78c413c 100644
--- a/src/gallium/drivers/ilo/include/brw_defines.h
+++ b/src/gallium/drivers/ilo/include/brw_defines.h
@@ -277,6 +277,7 @@
 #define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED           0x007
 #define BRW_SURFACEFORMAT_R32G32B32A32_USCALED           0x008
 #define BRW_SURFACEFORMAT_R32G32B32A32_SFIXED            0x020
+#define BRW_SURFACEFORMAT_R64G64_PASSTHRU                0x021
 #define BRW_SURFACEFORMAT_R32G32B32_FLOAT                0x040
 #define BRW_SURFACEFORMAT_R32G32B32_SINT                 0x041
 #define BRW_SURFACEFORMAT_R32G32B32_UINT                 0x042
@@ -309,6 +310,7 @@
 #define BRW_SURFACEFORMAT_R32G32_SSCALED                 0x095
 #define BRW_SURFACEFORMAT_R32G32_USCALED                 0x096
 #define BRW_SURFACEFORMAT_R32G32_SFIXED                  0x0A0
+#define BRW_SURFACEFORMAT_R64_PASSTHRU                   0x0A1
 #define BRW_SURFACEFORMAT_B8G8R8A8_UNORM                 0x0C0
 #define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB            0x0C1
 #define BRW_SURFACEFORMAT_R10G10B10A2_UNORM              0x0C2
@@ -371,6 +373,8 @@
 #define BRW_SURFACEFORMAT_R16_SINT                       0x10C
 #define BRW_SURFACEFORMAT_R16_UINT                       0x10D
 #define BRW_SURFACEFORMAT_R16_FLOAT                      0x10E
+#define BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE0            0x10F
+#define BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE1            0x110
 #define BRW_SURFACEFORMAT_I16_UNORM                      0x111
 #define BRW_SURFACEFORMAT_L16_UNORM                      0x112
 #define BRW_SURFACEFORMAT_A16_UNORM                      0x113
@@ -386,6 +390,12 @@
 #define BRW_SURFACEFORMAT_R8G8_USCALED                   0x11D
 #define BRW_SURFACEFORMAT_R16_SSCALED                    0x11E
 #define BRW_SURFACEFORMAT_R16_USCALED                    0x11F
+#define BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE0            0x122
+#define BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE1            0x123
+#define BRW_SURFACEFORMAT_A1B5G5R5_UNORM                 0x124
+#define BRW_SURFACEFORMAT_A4B4G4R4_UNORM                 0x125
+#define BRW_SURFACEFORMAT_L8A8_UINT                      0x126
+#define BRW_SURFACEFORMAT_L8A8_SINT                      0x127
 #define BRW_SURFACEFORMAT_R8_UNORM                       0x140
 #define BRW_SURFACEFORMAT_R8_SNORM                       0x141
 #define BRW_SURFACEFORMAT_R8_SINT                        0x142
@@ -397,11 +407,22 @@
 #define BRW_SURFACEFORMAT_A4P4_UNORM                     0x148
 #define BRW_SURFACEFORMAT_R8_SSCALED                     0x149
 #define BRW_SURFACEFORMAT_R8_USCALED                     0x14A
+#define BRW_SURFACEFORMAT_P8_UNORM_PALETTE0              0x14B
 #define BRW_SURFACEFORMAT_L8_UNORM_SRGB                  0x14C
+#define BRW_SURFACEFORMAT_P8_UNORM_PALETTE1              0x14D
+#define BRW_SURFACEFORMAT_P4A4_UNORM_PALETTE1            0x14E
+#define BRW_SURFACEFORMAT_A4P4_UNORM_PALETTE1            0x14F
+#define BRW_SURFACEFORMAT_Y8_SNORM                       0x150
+#define BRW_SURFACEFORMAT_L8_UINT                        0x152
+#define BRW_SURFACEFORMAT_L8_SINT                        0x153
+#define BRW_SURFACEFORMAT_I8_UINT                        0x154
+#define BRW_SURFACEFORMAT_I8_SINT                        0x155
 #define BRW_SURFACEFORMAT_DXT1_RGB_SRGB                  0x180
 #define BRW_SURFACEFORMAT_R1_UINT                        0x181
 #define BRW_SURFACEFORMAT_YCRCB_NORMAL                   0x182
 #define BRW_SURFACEFORMAT_YCRCB_SWAPUVY                  0x183
+#define BRW_SURFACEFORMAT_P2_UNORM_PALETTE0              0x184
+#define BRW_SURFACEFORMAT_P2_UNORM_PALETTE1              0x185
 #define BRW_SURFACEFORMAT_BC1_UNORM                      0x186
 #define BRW_SURFACEFORMAT_BC2_UNORM                      0x187
 #define BRW_SURFACEFORMAT_BC3_UNORM                      0x188
@@ -423,10 +444,26 @@
 #define BRW_SURFACEFORMAT_R64G64B64_FLOAT                0x198
 #define BRW_SURFACEFORMAT_BC4_SNORM                      0x199
 #define BRW_SURFACEFORMAT_BC5_SNORM                      0x19A
+#define BRW_SURFACEFORMAT_R16G16B16_FLOAT                0x19B
 #define BRW_SURFACEFORMAT_R16G16B16_UNORM                0x19C
 #define BRW_SURFACEFORMAT_R16G16B16_SNORM                0x19D
 #define BRW_SURFACEFORMAT_R16G16B16_SSCALED              0x19E
 #define BRW_SURFACEFORMAT_R16G16B16_USCALED              0x19F
+#define BRW_SURFACEFORMAT_BC6H_SF16                      0x1A1
+#define BRW_SURFACEFORMAT_BC7_UNORM                      0x1A2
+#define BRW_SURFACEFORMAT_BC7_UNORM_SRGB                 0x1A3
+#define BRW_SURFACEFORMAT_BC6H_UF16                      0x1A4
+#define BRW_SURFACEFORMAT_PLANAR_420_8                   0x1A5
+#define BRW_SURFACEFORMAT_R8G8B8_UNORM_SRGB              0x1A8
+#define BRW_SURFACEFORMAT_ETC1_RGB8                      0x1A9
+#define BRW_SURFACEFORMAT_ETC2_RGB8                      0x1AA
+#define BRW_SURFACEFORMAT_EAC_R11                        0x1AB
+#define BRW_SURFACEFORMAT_EAC_RG11                       0x1AC
+#define BRW_SURFACEFORMAT_EAC_SIGNED_R11                 0x1AD
+#define BRW_SURFACEFORMAT_EAC_SIGNED_RG11                0x1AE
+#define BRW_SURFACEFORMAT_ETC2_SRGB8                     0x1AF
+#define BRW_SURFACEFORMAT_R16G16B16_UINT                 0x1B0
+#define BRW_SURFACEFORMAT_R16G16B16_SINT                 0x1B1
 #define BRW_SURFACEFORMAT_R32_SFIXED                     0x1B2
 #define BRW_SURFACEFORMAT_R10G10B10A2_SNORM              0x1B3
 #define BRW_SURFACEFORMAT_R10G10B10A2_USCALED            0x1B4
@@ -437,6 +474,14 @@
 #define BRW_SURFACEFORMAT_B10G10R10A2_SSCALED            0x1B9
 #define BRW_SURFACEFORMAT_B10G10R10A2_UINT               0x1BA
 #define BRW_SURFACEFORMAT_B10G10R10A2_SINT               0x1BB
+#define BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU          0x1BC
+#define BRW_SURFACEFORMAT_R64G64B64_PASSTHRU             0x1BD
+#define BRW_SURFACEFORMAT_ETC2_RGB8_PTA                  0x1C0
+#define BRW_SURFACEFORMAT_ETC2_SRGB8_PTA                 0x1C1
+#define BRW_SURFACEFORMAT_ETC2_EAC_RGBA8                 0x1C2
+#define BRW_SURFACEFORMAT_ETC2_EAC_SRGB8_A8              0x1C3
+#define BRW_SURFACEFORMAT_R8G8B8_UINT                    0x1C8
+#define BRW_SURFACEFORMAT_R8G8B8_SINT                    0x1C9
 #define BRW_SURFACEFORMAT_RAW                            0x1FF
 #define BRW_SURFACE_FORMAT_SHIFT	18
 #define BRW_SURFACE_FORMAT_MASK		INTEL_MASK(26, 18)
@@ -647,6 +692,10 @@ enum opcode {
    BRW_OPCODE_CMPN =	17,
    BRW_OPCODE_F32TO16 = 19,
    BRW_OPCODE_F16TO32 = 20,
+   BRW_OPCODE_BFREV =	23,
+   BRW_OPCODE_BFE =	24,
+   BRW_OPCODE_BFI1 =	25,
+   BRW_OPCODE_BFI2 =	26,
    BRW_OPCODE_JMPI =	32,
    BRW_OPCODE_IF =	34,
    BRW_OPCODE_IFF =	35,
@@ -676,6 +725,9 @@ enum opcode {
    BRW_OPCODE_MAC =	72,
    BRW_OPCODE_MACH =	73,
    BRW_OPCODE_LZD =	74,
+   BRW_OPCODE_FBH =	75,
+   BRW_OPCODE_FBL =	76,
+   BRW_OPCODE_CBIT =	77,
    BRW_OPCODE_SAD2 =	80,
    BRW_OPCODE_SADA2 =	81,
    BRW_OPCODE_DP4 =	84,
@@ -777,6 +829,17 @@ enum opcode {
 #define BRW_REGISTER_TYPE_V   6	/* packed int vector, immediates only, uword dest only */
 #define BRW_REGISTER_TYPE_F   7
 
+/* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
+ * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
+ * and unsigned doublewords, so a new field is also available in the da3src
+ * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
+ * dst and shared-src types. The values are different from BRW_REGISTER_TYPE_*.
+ */
+#define BRW_3SRC_TYPE_F  0
+#define BRW_3SRC_TYPE_D  1
+#define BRW_3SRC_TYPE_UD 2
+#define BRW_3SRC_TYPE_DF 3
+
 #define BRW_ARF_NULL                  0x00
 #define BRW_ARF_ADDRESS               0x10
 #define BRW_ARF_ACCUMULATOR           0x20
diff --git a/src/gallium/drivers/ilo/include/brw_structs.h b/src/gallium/drivers/ilo/include/brw_structs.h
index 75365e07566..c322edfbdcf 100644
--- a/src/gallium/drivers/ilo/include/brw_structs.h
+++ b/src/gallium/drivers/ilo/include/brw_structs.h
@@ -824,7 +824,7 @@ struct brw_instruction
       GLuint access_mode:1;
       GLuint mask_control:1;
       GLuint dependency_control:2;
-      GLuint compression_control:2; /* gen6: quater control */
+      GLuint compression_control:2; /* gen6: quarter control */
       GLuint thread_control:2;
       GLuint predicate_control:4;
       GLuint predicate_inverse:1;
@@ -849,7 +849,7 @@ struct brw_instruction
 	 GLuint src0_reg_type:3;
 	 GLuint src1_reg_file:2;
 	 GLuint src1_reg_type:3;
-	 GLuint pad:1;
+         GLuint nibctrl:1; /* gen7+ */
 	 GLuint dest_subreg_nr:5;
 	 GLuint dest_reg_nr:8;
 	 GLuint dest_horiz_stride:2;
@@ -864,7 +864,7 @@ struct brw_instruction
 	 GLuint src0_reg_type:3;
 	 GLuint src1_reg_file:2;        /* 0x00000c00 */
 	 GLuint src1_reg_type:3;        /* 0x00007000 */
-	 GLuint pad:1;
+         GLuint nibctrl:1; /* gen7+ */
 	 GLint dest_indirect_offset:10;	/* offset against the deref'd address reg */
 	 GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */
 	 GLuint dest_horiz_stride:2;
@@ -879,7 +879,7 @@ struct brw_instruction
 	 GLuint src0_reg_type:3;
 	 GLuint src1_reg_file:2;
 	 GLuint src1_reg_type:3;
-	 GLuint pad:1;
+         GLuint nibctrl:1; /* gen7+ */
 	 GLuint dest_writemask:4;
 	 GLuint dest_subreg_nr:1;
 	 GLuint dest_reg_nr:8;
@@ -893,7 +893,9 @@ struct brw_instruction
 	 GLuint dest_reg_type:3;
 	 GLuint src0_reg_file:2;
 	 GLuint src0_reg_type:3;
-	 GLuint pad0:6;
+         GLuint src1_reg_file:2;
+         GLuint src1_reg_type:3;
+         GLuint nibctrl:1; /* gen7+ */
 	 GLuint dest_writemask:4;
 	 GLint dest_indirect_offset:6;
 	 GLuint dest_subreg_nr:3;
@@ -914,16 +916,21 @@ struct brw_instruction
       } branch_gen6;
 
       struct {
-	 GLuint dest_reg_file:1;
+         GLuint dest_reg_file:1; /* gen6, not gen7+ */
 	 GLuint flag_subreg_num:1;
-	 GLuint pad0:2;
+         GLuint flag_reg_nr:1; /* gen7+ */
+         GLuint pad0:1;
 	 GLuint src0_abs:1;
 	 GLuint src0_negate:1;
 	 GLuint src1_abs:1;
 	 GLuint src1_negate:1;
 	 GLuint src2_abs:1;
 	 GLuint src2_negate:1;
-	 GLuint pad1:7;
+         GLuint src_type:2; /* gen7+ */
+         GLuint dst_type:2; /* gen7+ */
+         GLuint pad1:1;
+         GLuint nibctrl:1; /* gen7+ */
+         GLuint pad2:1;
 	 GLuint dest_writemask:4;
 	 GLuint dest_subreg_nr:3;
 	 GLuint dest_reg_nr:8;
@@ -945,7 +952,7 @@ struct brw_instruction
 	 GLuint src0_width:3;
 	 GLuint src0_vert_stride:4;
 	 GLuint flag_subreg_nr:1;
-	 GLuint flag_reg_nr:1;
+         GLuint flag_reg_nr:1; /* gen7+ */
 	 GLuint pad:5;
       } da1;
 
@@ -960,7 +967,7 @@ struct brw_instruction
 	 GLuint src0_width:3;
 	 GLuint src0_vert_stride:4;
 	 GLuint flag_subreg_nr:1;
-	 GLuint flag_reg_nr:1;
+         GLuint flag_reg_nr:1; /* gen7+ */
 	 GLuint pad:5;
       } ia1;
 
@@ -978,7 +985,7 @@ struct brw_instruction
 	 GLuint pad0:1;
 	 GLuint src0_vert_stride:4;
 	 GLuint flag_subreg_nr:1;
-	 GLuint flag_reg_nr:1;
+         GLuint flag_reg_nr:1; /* gen7+ */
 	 GLuint pad1:5;
       } da16;
 
@@ -996,7 +1003,7 @@ struct brw_instruction
 	 GLuint pad0:1;
 	 GLuint src0_vert_stride:4;
 	 GLuint flag_subreg_nr:1;
-	 GLuint flag_reg_nr:1;
+         GLuint flag_reg_nr:1; /* gen7+ */
 	 GLuint pad1:5;
       } ia16;
 
diff --git a/src/gallium/drivers/ilo/include/intel_chipset.h b/src/gallium/drivers/ilo/include/intel_chipset.h
index 04753ddb631..ee735bb2fbf 100644
--- a/src/gallium/drivers/ilo/include/intel_chipset.h
+++ b/src/gallium/drivers/ilo/include/intel_chipset.h
@@ -95,40 +95,40 @@
 
 #define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
 #define PCI_CHIP_HASWELL_GT2            0x0412
-#define PCI_CHIP_HASWELL_GT2_PLUS       0x0422
+#define PCI_CHIP_HASWELL_GT3            0x0422
 #define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
 #define PCI_CHIP_HASWELL_M_GT2          0x0416
-#define PCI_CHIP_HASWELL_M_GT2_PLUS     0x0426
+#define PCI_CHIP_HASWELL_M_GT3          0x0426
 #define PCI_CHIP_HASWELL_S_GT1          0x040A /* Server */
 #define PCI_CHIP_HASWELL_S_GT2          0x041A
-#define PCI_CHIP_HASWELL_S_GT2_PLUS     0x042A
+#define PCI_CHIP_HASWELL_S_GT3          0x042A
 #define PCI_CHIP_HASWELL_SDV_GT1        0x0C02 /* Desktop */
 #define PCI_CHIP_HASWELL_SDV_GT2        0x0C12
-#define PCI_CHIP_HASWELL_SDV_GT2_PLUS   0x0C22
+#define PCI_CHIP_HASWELL_SDV_GT3        0x0C22
 #define PCI_CHIP_HASWELL_SDV_M_GT1      0x0C06 /* Mobile */
 #define PCI_CHIP_HASWELL_SDV_M_GT2      0x0C16
-#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_M_GT3      0x0C26
 #define PCI_CHIP_HASWELL_SDV_S_GT1      0x0C0A /* Server */
 #define PCI_CHIP_HASWELL_SDV_S_GT2      0x0C1A
-#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
+#define PCI_CHIP_HASWELL_SDV_S_GT3      0x0C2A
 #define PCI_CHIP_HASWELL_ULT_GT1        0x0A02 /* Desktop */
 #define PCI_CHIP_HASWELL_ULT_GT2        0x0A12
-#define PCI_CHIP_HASWELL_ULT_GT2_PLUS   0x0A22
+#define PCI_CHIP_HASWELL_ULT_GT3        0x0A22
 #define PCI_CHIP_HASWELL_ULT_M_GT1      0x0A06 /* Mobile */
 #define PCI_CHIP_HASWELL_ULT_M_GT2      0x0A16
-#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_M_GT3      0x0A26
 #define PCI_CHIP_HASWELL_ULT_S_GT1      0x0A0A /* Server */
 #define PCI_CHIP_HASWELL_ULT_S_GT2      0x0A1A
-#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_ULT_S_GT3      0x0A2A
 #define PCI_CHIP_HASWELL_CRW_GT1        0x0D02 /* Desktop */
 #define PCI_CHIP_HASWELL_CRW_GT2        0x0D12
-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS   0x0D22
+#define PCI_CHIP_HASWELL_CRW_GT3        0x0D22
 #define PCI_CHIP_HASWELL_CRW_M_GT1      0x0D06 /* Mobile */
 #define PCI_CHIP_HASWELL_CRW_M_GT2      0x0D16
-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT3      0x0D26
 #define PCI_CHIP_HASWELL_CRW_S_GT1      0x0D0A /* Server */
 #define PCI_CHIP_HASWELL_CRW_S_GT2      0x0D1A
-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT3      0x0D2A
 
 #define IS_MOBILE(devid)	(devid == PCI_CHIP_I855_GM || \
 				 devid == PCI_CHIP_I915_GM || \
@@ -229,21 +229,23 @@
 				 devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
 				 devid == PCI_CHIP_HASWELL_CRW_GT2 || \
 				 devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
-				 devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
-				 devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
-				 devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
-				 devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
-				 devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
-				 devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
-				 devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
-				 devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
-				 devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
-				 devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
-				 devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
-				 devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
+				 devid == PCI_CHIP_HASWELL_CRW_S_GT2)
+#define IS_HSW_GT3(devid)	(devid == PCI_CHIP_HASWELL_GT3 || \
+				 devid == PCI_CHIP_HASWELL_M_GT3 || \
+				 devid == PCI_CHIP_HASWELL_S_GT3 || \
+				 devid == PCI_CHIP_HASWELL_SDV_GT3 || \
+				 devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
+				 devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \
+				 devid == PCI_CHIP_HASWELL_ULT_GT3 || \
+				 devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \
+				 devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \
+				 devid == PCI_CHIP_HASWELL_CRW_GT3 || \
+				 devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \
+				 devid == PCI_CHIP_HASWELL_CRW_S_GT3)
 
 #define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
-				 IS_HSW_GT2(devid))
+				 IS_HSW_GT2(devid) || \
+				 IS_HSW_GT3(devid))
 
 #define IS_965(devid)		(IS_GEN4(devid) || \
 				 IS_G4X(devid) || \
diff --git a/src/gallium/drivers/ilo/include/intel_reg.h b/src/gallium/drivers/ilo/include/intel_reg.h
index e4871ebf9e7..1cfb4645129 100644
--- a/src/gallium/drivers/ilo/include/intel_reg.h
+++ b/src/gallium/drivers/ilo/include/intel_reg.h
@@ -37,6 +37,8 @@
 #define FLUSH_MAP_CACHE				(1 << 0)
 #define INHIBIT_FLUSH_RENDER_CACHE		(1 << 2)
 
+#define MI_LOAD_REGISTER_IMM		(CMD_MI | (0x22 << 23))
+
 #define MI_FLUSH_DW			(CMD_MI | (0x26 << 23) | 2)
 
 /* Stalls command execution waiting for the given events to have occurred. */
@@ -264,6 +266,19 @@
 #define FENCE_XMAJOR 1
 #define FENCE_YMAJOR 2
 
+/* Pipeline Statistics Counter Registers */
+#define IA_VERTICES_COUNT               0x2310
+#define IA_PRIMITIVES_COUNT             0x2318
+#define VS_INVOCATION_COUNT             0x2320
+#define HS_INVOCATION_COUNT             0x2300
+#define DS_INVOCATION_COUNT             0x2308
+#define GS_INVOCATION_COUNT             0x2328
+#define GS_PRIMITIVES_COUNT             0x2330
+#define CL_INVOCATION_COUNT             0x2338
+#define CL_PRIMITIVES_COUNT             0x2340
+#define PS_INVOCATION_COUNT             0x2348
+#define PS_DEPTH_COUNT                  0x2350
+
 #define SO_NUM_PRIM_STORAGE_NEEDED	0x2280
 #define SO_PRIM_STORAGE_NEEDED0_IVB	0x5240
 #define SO_PRIM_STORAGE_NEEDED1_IVB	0x5248
@@ -277,3 +292,7 @@
 #define SO_NUM_PRIMS_WRITTEN3_IVB	0x5218
 
 #define TIMESTAMP                       0x2358
+
+#define BCS_SWCTRL                      0x22200
+# define BCS_SWCTRL_SRC_Y               (1 << 0)
+# define BCS_SWCTRL_DST_Y               (1 << 1)