diff options
author | Joakim Sindholt <[email protected]> | 2009-02-13 05:08:54 +0100 |
---|---|---|
committer | Corbin Simpson <[email protected]> | 2009-02-12 20:24:27 -0800 |
commit | 92661bcbad13c8750f63e3a30b6c616d2f1094d3 (patch) | |
tree | 5e59f2666263083b9cf4c9f7f266d3aa23f0719b /src/gallium | |
parent | 0d60a3f33cbc071fb5aca95b96f35908059b0435 (diff) |
r300-gallium: fix OUT_CS_ONE_REG and use where applicable
Signed-off-by: Corbin Simpson <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r-- | src/gallium/drivers/r300/r300_cs_inlines.h | 8 | ||||
-rw-r--r-- | src/gallium/drivers/r300/r300_emit.c | 16 | ||||
-rw-r--r-- | src/gallium/drivers/r300/r300_surface.c | 26 |
3 files changed, 23 insertions, 27 deletions
diff --git a/src/gallium/drivers/r300/r300_cs_inlines.h b/src/gallium/drivers/r300/r300_cs_inlines.h index a3ea4f900b5..98f9ee04511 100644 --- a/src/gallium/drivers/r300/r300_cs_inlines.h +++ b/src/gallium/drivers/r300/r300_cs_inlines.h @@ -28,8 +28,12 @@ #define RADEON_ONE_REG_WR (1 << 15) -#define OUT_CS_ONE_REG(register, count) \ - OUT_CS_REG_SEQ(register, (count | RADEON_ONE_REG_WR)) +#define OUT_CS_ONE_REG(register, count) do { \ + debug_printf("r300: writing data sequence of %d to 0x%04X\n", \ + count, register); \ + assert(register); \ + OUT_CS(CP_PACKET0(register, ((count) - 1)) | RADEON_ONE_REG_WR); \ +} while (0) #define R300_PACIFY do { \ OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | \ diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index 8391663f7f6..a4d520a6741 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -114,17 +114,15 @@ void r500_emit_fragment_shader(struct r300_context* r300, struct r500_fragment_shader* fs) { CS_LOCALS(r300); - int i; - /* XXX Problem: OUT_CS_ONE_REG causes card crash */ - /* BEGIN_CS(8 + (shader->shader.instruction_count * 6) + 6); */ - BEGIN_CS(10 + (shader->shader.instruction_count * 12)); + int i = 0; + BEGIN_CS(11 + (shader->shader.instruction_count * 6)); OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); OUT_CS_REG(R500_US_PIXSIZE, fs->shader.stack_size); OUT_CS_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(fs->instruction_count)); OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_INSTR); - /* OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, + OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, shader->shader.instruction_count * 6); for (i = 0; i < shader->shader.instruction_count; i++) { OUT_CS(shader->instructions[i].inst0); @@ -133,14 +131,6 @@ void r500_emit_fragment_shader(struct r300_context* r300, OUT_CS(shader->instructions[i].inst3); OUT_CS(shader->instructions[i].inst4); OUT_CS(shader->instructions[i].inst5); - } */ - for (i = 0; i < shader->shader.instruction_count; i++) { - OUT_CS_REG(R500_GA_US_VECTOR_DATA, shader->instructions[i].inst0); - OUT_CS_REG(R500_GA_US_VECTOR_DATA, shader->instructions[i].inst1); - OUT_CS_REG(R500_GA_US_VECTOR_DATA, shader->instructions[i].inst2); - OUT_CS_REG(R500_GA_US_VECTOR_DATA, shader->instructions[i].inst3); - OUT_CS_REG(R500_GA_US_VECTOR_DATA, shader->instructions[i].inst4); - OUT_CS_REG(R500_GA_US_VECTOR_DATA, shader->instructions[i].inst5); } R300_PACIFY; END_CS; diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 54ab778ce7c..2c6af363f28 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -54,7 +54,7 @@ static void r300_surface_fill(struct pipe_context* pipe, return; } - BEGIN_CS(172 + (caps->is_r500 ? 22 : 14) + (caps->has_tcl ? 4 : 2)); + BEGIN_CS(168 + (caps->is_r500 ? 22 : 14) + (caps->has_tcl ? 4 : 2)); R300_PACIFY; OUT_CS_REG(R300_TX_INVALTAGS, 0x0); R300_PACIFY; @@ -153,8 +153,9 @@ static void r300_surface_fill(struct pipe_context* pipe, OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003); OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000); OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000); + /* XXX Moar unknown that should probably be left out. OUT_CS_REG(0x4F30, 0x00000000); - OUT_CS_REG(0x4F34, 0x00000000); + OUT_CS_REG(0x4F34, 0x00000000); */ OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000); OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000); R300_PACIFY; @@ -233,8 +234,8 @@ static void r300_surface_fill(struct pipe_context* pipe, } else { r300_emit_fragment_shader(r300, &r300_passthrough_fragment_shader); } - - BEGIN_CS(2 + (caps->has_tcl ? 30 : 2)); + + BEGIN_CS(2 + (caps->has_tcl ? 23 : 2)); /* XXX these magic numbers should be explained when * this becomes a cached state object */ if (caps->has_tcl) { @@ -249,14 +250,15 @@ static void r300_surface_fill(struct pipe_context* pipe, /* XXX translate these back into normal instructions */ OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1); OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF00203); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10001); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248001); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF02203); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10021); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248021); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); + OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 8); + OUT_CS(0x00F00203); + OUT_CS(0x00D10001); + OUT_CS(0x01248001); + OUT_CS(0x00000000); + OUT_CS(0x00F02203); + OUT_CS(0x00D10021); + OUT_CS(0x01248021); + OUT_CS(0x00000000); } else { OUT_CS_REG(R300_VAP_CNTL, 0xA | (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) | |