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authorRob Clark <[email protected]>2014-04-09 09:54:20 -0400
committerRob Clark <[email protected]>2014-04-09 10:59:18 -0400
commit4a92c122324e0e1a08204f625620ab7635c22f99 (patch)
tree2f802a630aacf721dc73b398e9001ff87a804da1 /src/gallium
parent9604e31dc9b43529a17b823b9cb9ddb7492bb317 (diff)
freedreno/a3xx/compiler: add CEIL
fixes piglit glsl-fs-ceil Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_compiler.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c b/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c
index ad518b0b5e9..fd385d77024 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c
@@ -1730,6 +1730,7 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
INSTR(FLR, instr_cat2, .opc = OPC_FLOOR_F),
INSTR(ROUND, instr_cat2, .opc = OPC_RNDNE_F),
INSTR(SSG, instr_cat2, .opc = OPC_SIGN_F),
+ INSTR(CEIL, instr_cat2, .opc = OPC_CEIL_F),
INSTR(ARL, trans_arl),
INSTR(EX2, instr_cat4, .opc = OPC_EXP2),
INSTR(LG2, instr_cat4, .opc = OPC_LOG2),