diff options
author | Marek Olšák <[email protected]> | 2012-01-30 01:03:43 +0100 |
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committer | Marek Olšák <[email protected]> | 2012-01-30 01:27:25 +0100 |
commit | f9f8ce3ead04b5334bb323c37ec1f905ca5f58b2 (patch) | |
tree | 4c582145f134518858b5e88f474c84e0f2b990a3 /src/gallium | |
parent | ce816dd831ba4e57b024631ff39591efae50ce14 (diff) |
r600g: remove unused streamout code
Diffstat (limited to 'src/gallium')
-rw-r--r-- | src/gallium/drivers/r600/r600_hw_context.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index ef87c37ed13..e6aed10885c 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -2219,33 +2219,4 @@ void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_tar ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ); - -#if 0 /* I have not found this useful yet. */ - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_COPY_DW, 4, 0); - ctx->pm4[ctx->pm4_cdwords++] = COPY_DW_SRC_IS_REG | COPY_DW_DST_IS_REG; - ctx->pm4[ctx->pm4_cdwords++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* src register */ - ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */ - ctx->pm4[ctx->pm4_cdwords++] = R_0085F4_CP_COHER_SIZE >> 2; /* dst register */ - ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */ - - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0); - ctx->pm4[ctx->pm4_cdwords++] = (R_0085F0_CP_COHER_CNTL - R600_CONFIG_REG_OFFSET) >> 2; - ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_SO0_DEST_BASE_ENA(1) << t->so_index; - - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0); - ctx->pm4[ctx->pm4_cdwords++] = (R_0085F8_CP_COHER_BASE - R600_CONFIG_REG_OFFSET) >> 2; - ctx->pm4[ctx->pm4_cdwords++] = t->b.buffer_offset >> 2; - - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); - ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, (struct r600_resource*)t->b.buffer, - RADEON_USAGE_WRITE); - - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0); - ctx->pm4[ctx->pm4_cdwords++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */ - ctx->pm4[ctx->pm4_cdwords++] = R_0085FC_CP_COHER_STATUS >> 2; /* register */ - ctx->pm4[ctx->pm4_cdwords++] = 0; - ctx->pm4[ctx->pm4_cdwords++] = 0; /* reference value */ - ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* mask */ - ctx->pm4[ctx->pm4_cdwords++] = 4; /* poll interval */ -#endif } |