diff options
| author | Marek Olšák <[email protected]> | 2017-02-15 18:36:21 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-02-18 01:22:08 +0100 |
| commit | 620aded541a5b81df74575888754094fea2f2ae2 (patch) | |
| tree | ee77931dc1b114fdd3c08d56a28092ca6f352238 /src/gallium | |
| parent | 22b8a773e1edb6d1a39b2ab9f715be1138976a2b (diff) | |
radeonsi: move index buffer flushing into a non-upload indexed case
The other codepaths don't need this.
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index d4533093e46..e341f33fb1a 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1086,16 +1086,15 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) return; /* info->start will be added by the drawing code */ ib.offset -= start_offset; + } else if (sctx->b.chip_class <= CIK && + r600_resource(ib.buffer)->TC_L2_dirty) { + /* VI reads index buffers through TC L2, so it doesn't + * need this. */ + sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; + r600_resource(ib.buffer)->TC_L2_dirty = false; } } - /* VI reads index buffers through TC L2. */ - if (info->indexed && sctx->b.chip_class <= CIK && - r600_resource(ib.buffer)->TC_L2_dirty) { - sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; - r600_resource(ib.buffer)->TC_L2_dirty = false; - } - if (info->indirect) { /* Add the buffer size for memory checking in need_cs_space. */ r600_context_add_resource_size(ctx, info->indirect); |