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authorMarek Olšák <[email protected]>2014-04-19 23:11:41 +0200
committerMarek Olšák <[email protected]>2014-04-25 01:33:12 +0200
commit20a9b784da3c286bdba5fbfb4e6592e16560895c (patch)
tree794990ab114a34dd8300825f8bc3b8399ff03613 /src/gallium
parent6dd045ef4074d23ac659eadb2388b12542e3aab8 (diff)
r600g: fix MSAA resolve on R6xx when the destination is 1D-tiled
Cc: 10.0 10.1 [email protected] Reviewed-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/radeon/r600_texture.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index c410543b81b..55caece541f 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -289,6 +289,12 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
fmask.nsamples = 1;
fmask.flags |= RADEON_SURF_FMASK;
+ /* Force 2D tiling if it wasn't set. This may occur when creating
+ * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
+ * destination buffer must have an FMASK too. */
+ fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
+ fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+
if (rscreen->chip_class >= SI) {
fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
}