diff options
| author | Vincent Lejeune <[email protected]> | 2012-11-29 23:46:15 +0100 |
|---|---|---|
| committer | Vincent Lejeune <[email protected]> | 2012-12-05 18:31:55 +0100 |
| commit | 00d77e9fe49924e39e211e1890c083847498a9a0 (patch) | |
| tree | cd85d55d9e576ff8e368bd2c056b73223d6290be /src/gallium | |
| parent | 2d97f77b9f4ea58afe19f93dfc7ac7ed96819669 (diff) | |
r600g: use default action for min/max opcode in tgsi to llvm
Reveiwed-by: Tom Stellard <thomas.stellard at amd.com>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c index 2521582001e..9cb0e9a1953 100644 --- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c +++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c @@ -1120,11 +1120,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx) bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32"; bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem; bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp"; - bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max."; bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod; - bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min."; bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not; bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or; bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_readonly; |