diff options
author | Marek Olšák <[email protected]> | 2016-06-06 17:33:42 +0200 |
---|---|---|
committer | Marek Olšák <[email protected]> | 2016-06-08 00:22:45 +0200 |
commit | c06246501ed9c095a3fa9f8fe2a5dadd1df55271 (patch) | |
tree | b7295a61aba04b755f8219c1157f154111b46f36 /src/gallium | |
parent | 00389100b63d03adf70892b721d1b2e8b8d5e48a (diff) |
radeonsi: don't enable DCC in the sampler if first_level doesn't have it
If first_level > 0 and DCC is disabled for that level, let's skip DCC
reads entirely.
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 21 | ||||
-rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 2 | ||||
-rw-r--r-- | src/gallium/drivers/radeonsi/si_state.h | 5 |
3 files changed, 21 insertions, 7 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index e0c966666a1..e80db395075 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -312,10 +312,21 @@ static void si_sampler_views_begin_new_cs(struct si_context *sctx, } } +/* Set texture descriptor fields that can be changed by reallocations. + * + * \param tex texture + * \param base_level_info information of the level of BASE_ADDRESS + * \param base_level the level of BASE_ADDRESS + * \param first_level pipe_sampler_view.u.tex.first_level + * \param block_width util_format_get_blockwidth() + * \param is_stencil select between separate Z & Stencil + * \param state descriptor to update + */ void si_set_mutable_tex_desc_fields(struct r600_texture *tex, const struct radeon_surf_level *base_level_info, - unsigned base_level, unsigned block_width, - bool is_stencil, uint32_t *state) + unsigned base_level, unsigned first_level, + unsigned block_width, bool is_stencil, + uint32_t *state) { uint64_t va = tex->resource.gpu_address + base_level_info->offset; unsigned pitch = base_level_info->nblk_x * block_width; @@ -331,7 +342,7 @@ void si_set_mutable_tex_desc_fields(struct r600_texture *tex, is_stencil)); state[4] |= S_008F20_PITCH(pitch - 1); - if (tex->dcc_offset && base_level_info->dcc_enabled) { + if (tex->dcc_offset && tex->surface.level[first_level].dcc_enabled) { state[6] |= S_008F28_COMPRESSION_EN(1); state[7] = (tex->resource.gpu_address + tex->dcc_offset + @@ -369,6 +380,7 @@ static void si_set_sampler_view(struct si_context *sctx, si_set_mutable_tex_desc_fields(rtex, rview->base_level_info, rview->base_level, + rview->base.u.tex.first_level, rview->block_width, is_separate_stencil, desc); @@ -640,7 +652,8 @@ static void si_set_shader_image(struct si_context *ctx, view->u.tex.last_layer, width, height, depth, desc, NULL); - si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level], level, + si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level], + level, level, util_format_get_blockwidth(view->format), false, desc); } diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index fc28fc94ebf..270b9fda079 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3446,7 +3446,7 @@ static void si_query_opaque_metadata(struct r600_common_screen *rscreen, res->width0, res->height0, res->depth0, desc, NULL); - si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, + si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0, rtex->surface.blk_w, false, desc); /* Clear the base address and set the relative DCC offset. */ diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index 811a02f9a3c..a4a58bba905 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -279,8 +279,9 @@ struct si_buffer_resources { void si_ce_enable_loads(struct radeon_winsys_cs *ib); void si_set_mutable_tex_desc_fields(struct r600_texture *tex, const struct radeon_surf_level *base_level_info, - unsigned base_level, unsigned block_width, - bool is_stencil, uint32_t *state); + unsigned base_level, unsigned first_level, + unsigned block_width, bool is_stencil, + uint32_t *state); void si_set_ring_buffer(struct pipe_context *ctx, uint slot, struct pipe_resource *buffer, unsigned stride, unsigned num_records, |