diff options
| author | Tom Stellard <[email protected]> | 2012-07-27 21:04:36 +0000 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-07-30 21:10:13 +0000 |
| commit | aece7970eb171ec6c28c412d22f42362b4f52bac (patch) | |
| tree | 16569f3d3bf9c07afbda73fb7c30c8c67c8b510d /src/gallium | |
| parent | 0ce6e506016222b264163ee718202371f19064db (diff) | |
radeon/llvm: Cleanup and reorganize AMDIL .td files
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPU.td | 18 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILBase.td | 33 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILEnumeratedTypes.td | 522 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILFormats.td | 175 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILInstrInfo.td | 270 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILInstructions.td | 82 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILIntrinsics.td | 566 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILMultiClass.td | 95 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILNodes.td | 47 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILOperands.td | 32 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILPatterns.td | 504 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILProfiles.td | 174 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILTokenDesc.td | 120 |
13 files changed, 335 insertions, 2303 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPU.td b/src/gallium/drivers/radeon/AMDGPU.td index b5e22783203..5086f63d79c 100644 --- a/src/gallium/drivers/radeon/AMDGPU.td +++ b/src/gallium/drivers/radeon/AMDGPU.td @@ -10,6 +10,24 @@ // Include AMDIL TD files include "AMDILBase.td" + +def AMDGPUInstrInfo : InstrInfo {} + +//===----------------------------------------------------------------------===// +// Declare the target which we are implementing +//===----------------------------------------------------------------------===// +def AMDGPUAsmWriter : AsmWriter { + string AsmWriterClassName = "InstPrinter"; + int Variant = 0; + bit isMCAsmWriter = 1; +} + +def AMDGPU : Target { + // Pull in Instruction Info: + let InstructionSet = AMDGPUInstrInfo; + let AssemblyWriters = [AMDGPUAsmWriter]; +} + // Include AMDGPU TD files include "R600Schedule.td" include "SISchedule.td" diff --git a/src/gallium/drivers/radeon/AMDILBase.td b/src/gallium/drivers/radeon/AMDILBase.td index 23a890a5041..e6843171a88 100644 --- a/src/gallium/drivers/radeon/AMDILBase.td +++ b/src/gallium/drivers/radeon/AMDILBase.td @@ -78,36 +78,3 @@ def FeatureDumpCode : SubtargetFeature <"DumpCode", include "AMDILRegisterInfo.td" include "AMDILInstrInfo.td" -def AMDILInstrInfo : InstrInfo {} - -//===----------------------------------------------------------------------===// -// AMDIL processors supported. -//===----------------------------------------------------------------------===// -//include "Processors.td" - -//===----------------------------------------------------------------------===// -// Declare the target which we are implementing -//===----------------------------------------------------------------------===// -def AMDGPUAsmWriter : AsmWriter { - string AsmWriterClassName = "InstPrinter"; - int Variant = 0; - bit isMCAsmWriter = 1; -} - -def AMDILAsmParser : AsmParser { - string AsmParserClassName = "AsmParser"; - int Variant = 0; - - string CommentDelimiter = ";"; - - string RegisterPrefix = "r"; - -} - - -def AMDGPU : Target { - // Pull in Instruction Info: - let InstructionSet = AMDILInstrInfo; - let AssemblyWriters = [AMDGPUAsmWriter]; - let AssemblyParsers = [AMDILAsmParser]; -} diff --git a/src/gallium/drivers/radeon/AMDILEnumeratedTypes.td b/src/gallium/drivers/radeon/AMDILEnumeratedTypes.td deleted file mode 100644 index f10936b8c6c..00000000000 --- a/src/gallium/drivers/radeon/AMDILEnumeratedTypes.td +++ /dev/null @@ -1,522 +0,0 @@ -//===-- AMDILEnumeratedTypes.td - IL Type definitions --*- tablegen -*-----===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// -// ILEnumreatedTypes.td - The IL Enumerated Types -//===--------------------------------------------------------------------===// - -// Section 5.1 IL Shader -class ILShader<bits<8> val> { - bits<8> Value = val; -} -// Table 5-1 -def IL_SHADER_PIXEL : ILShader<0>; -def IL_SHADER_COMPUTE : ILShader<1>; - -// Section 5.2 IL RegType -class ILRegType<bits<6> val> { - bits<6> Value = val; -} -// Table 5-2 -def IL_REGTYPE_TEMP : ILRegType<0>; -def IL_REGTYPE_WINCOORD : ILRegType<1>; -def IL_REGTYPE_CONST_BUF : ILRegType<2>; -def IL_REGTYPE_LITERAL : ILRegType<3>; -def IL_REGTYPE_ITEMP : ILRegType<4>; -def IL_REGTYPE_GLOBAL : ILRegType<5>; - -// Section 5.3 IL Component Select -class ILComponentSelect<bits<3> val, string text> { - bits<3> Value = val; - string Text = text; -} -// Table 5-3 -def IL_COMPSEL_X : ILComponentSelect<0, "x">; -def IL_COMPSEL_Y : ILComponentSelect<1, "y">; -def IL_COMPSEL_Z : ILComponentSelect<2, "z">; -def IL_COMPSEL_W : ILComponentSelect<3, "w">; -def IL_COMPSEL_0 : ILComponentSelect<4, "0">; -def IL_COMPSEL_1 : ILComponentSelect<5, "1">; - -// Section 5.4 IL Mod Dst Comp -class ILModDstComp<bits<2> val, string text> { - bits<2> Value = val; - string Text = text; -} -// Table 5-4 -def IL_MODCOMP_NOWRITE : ILModDstComp<0, "_">; -def IL_MODCOMP_WRITE_X : ILModDstComp<1, "x">; -def IL_MODCOMP_WRITE_y : ILModDstComp<1, "y">; -def IL_MODCOMP_WRITE_z : ILModDstComp<1, "z">; -def IL_MODCOMP_WRITE_w : ILModDstComp<1, "w">; -def IL_MODCOMP_0 : ILModDstComp<2, "0">; -def IL_MODCOMP_1 : ILModDstComp<3, "1">; - -// Section 5.5 IL Import Usage -class ILImportUsage<bits<1> val, string usage> { - bits<1> Value = val; - string Text = usage; -} -// Table 5-5 -def IL_IMPORTUSAGE_WINCOORD : ILImportUsage<0, "_usage(wincoord)">; - -// Section 5.6 Il Shift Scale -class ILShiftScale<bits<4> val, string scale> { - bits<4> Value = val; - string Text = scale; -} - -// Table 5-6 -def IL_SHIFT_NONE : ILShiftScale<0, "">; -def IL_SHIFT_X2 : ILShiftScale<1, "_x2">; -def IL_SHIFT_X4 : ILShiftScale<2, "_x4">; -def IL_SHIFT_X8 : ILShiftScale<3, "_x8">; -def IL_SHIFT_D2 : ILShiftScale<4, "_d2">; -def IL_SHIFT_D4 : ILShiftScale<5, "_d4">; -def IL_SHIFT_D8 : ILShiftScale<6, "_d8">; - -// Section 5.7 IL Divide Component -class ILDivComp<bits<3> val, string divcomp> { - bits<3> Value = val; - string Text = divcomp; -} - -// Table 5-7 -def IL_DIVCOMP_NONE : ILDivComp<0, "_divcomp(none)">; -def IL_DIVCOMP_Y : ILDivComp<1, "_divcomp(y)">; -def IL_DIVCOMP_Z : ILDivComp<2, "_divcomp(z)">; -def IL_DIVCOMP_W : ILDivComp<3, "_divcomp(w)">; -//def IL_DIVCOMP_UNKNOWN : ILDivComp<4, "_divcomp(unknown)">; - -// Section 5.8 IL Relational Op -class ILRelOp<bits<3> val, string op> { - bits<3> Value = val; - string Text = op; -} - -// Table 5-8 -def IL_RELOP_EQ : ILRelOp<0, "_relop(eq)">; -def IL_RELOP_NE : ILRelOp<1, "_relop(ne)">; -def IL_RELOP_GT : ILRelOp<2, "_relop(gt)">; -def IL_RELOP_GE : ILRelOp<3, "_relop(ge)">; -def IL_RELOP_LT : ILRelOp<4, "_relop(lt)">; -def IL_RELOP_LE : ILRelOp<5, "_relop(le)">; - -// Section 5.9 IL Zero Op -class ILZeroOp<bits<3> val, string behavior> { - bits<3> Value = val; - string Text = behavior; -} - -// Table 5-9 -def IL_ZEROOP_FLTMAX : ILZeroOp<0, "_zeroop(fltmax)">; -def IL_ZEROOP_0 : ILZeroOp<1, "_zeroop(zero)">; -def IL_ZEROOP_INFINITY : ILZeroOp<2, "_zeroop(infinity)">; -def IL_ZEROOP_INF_ELSE_MAX : ILZeroOp<3, "_zeroop(inf_else_max)">; - -// Section 5.10 IL Cmp Value -class ILCmpValue<bits<3> val, string num> { - bits<3> Value = val; - string Text = num; -} - -// Table 5-10 -def IL_CMPVAL_0_0 : ILCmpValue<0, "0.0">; -def IL_CMPVAL_0_5 : ILCmpValue<1, "0.5">; -def IL_CMPVAL_1_0 : ILCmpValue<2, "1.0">; -def IL_CMPVAL_NEG_0_5 : ILCmpValue<3, "-0.5">; -def IL_CMPVAL_NEG_1_0 : ILCmpValue<4, "-1.0">; - -// Section 5.11 IL Addressing -class ILAddressing<bits<3> val> { - bits<3> Value = val; -} - -// Table 5-11 -def IL_ADDR_ABSOLUTE : ILAddressing<0>; -def IL_ADDR_RELATIVE : ILAddressing<1>; -def IL_ADDR_REG_RELATIVE : ILAddressing<2>; - -// Section 5.11 IL Element Format -class ILElementFormat<bits<5> val> { - bits<5> Value = val; -} - -// Table 5-11 -def IL_ELEMENTFORMAT_UNKNOWN : ILElementFormat<0>; -def IL_ELEMENTFORMAT_SNORM : ILElementFormat<1>; -def IL_ELEMENTFORMAT_UNORM : ILElementFormat<2>; -def IL_ELEMENTFORMAT_SINT : ILElementFormat<3>; -def IL_ELEMENTFORMAT_UINT : ILElementFormat<4>; -def IL_ELEMENTFORMAT_FLOAT : ILElementFormat<5>; -def IL_ELEMENTFORMAT_SRGB : ILElementFormat<6>; -def IL_ELEMENTFORMAT_MIXED : ILElementFormat<7>; -def IL_ELEMENTFORMAT_Last : ILElementFormat<8>; - -// Section 5.12 IL Op Code -class ILOpCode<bits<16> val = -1, string cmd> { - bits<16> Value = val; - string Text = cmd; -} - -// Table 5-12 -def IL_DCL_CONST_BUFFER : ILOpCode<0, "dcl_cb">; -def IL_DCL_INDEXED_TEMP_ARRAY : ILOpCode<1, "dcl_index_temp_array">; -def IL_DCL_INPUT : ILOpCode<2, "dcl_input">; -def IL_DCL_LITERAL : ILOpCode<3, "dcl_literal">; -def IL_DCL_OUTPUT : ILOpCode<4, "dcl_output">; -def IL_DCL_RESOURCE : ILOpCode<5, "dcl_resource">; -def IL_OP_ABS : ILOpCode<6, "abs">; -def IL_OP_ADD : ILOpCode<7, "add">; -def IL_OP_AND : ILOpCode<8, "iand">; -def IL_OP_BREAK : ILOpCode<9, "break">; -def IL_OP_BREAK_LOGICALNZ : ILOpCode<10, "break_logicalnz">; -def IL_OP_BREAK_LOGICALZ : ILOpCode<11, "break_logicalz">; -def IL_OP_BREAKC : ILOpCode<12, "breakc">; -def IL_OP_CALL : ILOpCode<13, "call">; -def IL_OP_CALL_LOGICALNZ : ILOpCode<14, "call_logicalnz">; -def IL_OP_CALL_LOGICALZ : ILOpCode<15, "call_logicalz">; -def IL_OP_CASE : ILOpCode<16, "case">; -def IL_OP_CLG : ILOpCode<17, "clg">; -def IL_OP_CMOV : ILOpCode<18, "cmov">; -def IL_OP_CMOV_LOGICAL : ILOpCode<19, "cmov_logical">; -def IL_OP_CMP : ILOpCode<20, "cmp">; -def IL_OP_CONTINUE : ILOpCode<21, "continue">; -def IL_OP_CONTINUE_LOGICALNZ : ILOpCode<22, "continue_logicalnz">; -def IL_OP_CONTINUE_LOGICALZ : ILOpCode<23, "continue_logicalz">; -def IL_OP_CONTINUEC : ILOpCode<24, "continuec">; -def IL_OP_COS : ILOpCode<25, "cos">; -def IL_OP_COS_VEC : ILOpCode<26, "cos_vec">; -def IL_OP_D_2_F : ILOpCode<27, "d2f">; -def IL_OP_D_ADD : ILOpCode<28, "dadd">; -def IL_OP_D_EQ : ILOpCode<29, "deq">; -def IL_OP_D_FRC : ILOpCode<30, "dfrac">; -def IL_OP_D_FREXP : ILOpCode<31, "dfrexp">; -def IL_OP_D_GE : ILOpCode<32, "dge">; -def IL_OP_D_LDEXP : ILOpCode<33, "dldexp">; -def IL_OP_D_LT : ILOpCode<34, "dlt">; -def IL_OP_D_MAD : ILOpCode<35, "dmad">; -def IL_OP_D_MUL : ILOpCode<36, "dmul">; -def IL_OP_D_NE : ILOpCode<37, "dne">; -def IL_OP_DEFAULT : ILOpCode<38, "default">; -def IL_OP_DISCARD_LOGICALNZ : ILOpCode<39, "discard_logicalnz">; -def IL_OP_DISCARD_LOGICALZ : ILOpCode<40, "discard_logicalz">; -def IL_OP_DIV : ILOpCode<41, "div_zeroop(infinity)">; -def IL_OP_DP2 : ILOpCode<42, "dp2">; -def IL_OP_DP3 : ILOpCode<43, "dp3">; -def IL_OP_DP4 : ILOpCode<44, "dp4">; -def IL_OP_ELSE : ILOpCode<45, "else">; -def IL_OP_END : ILOpCode<46, "end">; -def IL_OP_ENDFUNC : ILOpCode<47, "endfunc">; -def IL_OP_ENDIF : ILOpCode<48, "endif">; -def IL_OP_ENDLOOP : ILOpCode<49, "endloop">; -def IL_OP_ENDMAIN : ILOpCode<50, "endmain">; -def IL_OP_ENDSWITCH : ILOpCode<51, "endswitch">; -def IL_OP_EQ : ILOpCode<52, "eq">; -def IL_OP_EXP : ILOpCode<53, "exp">; -def IL_OP_EXP_VEC : ILOpCode<54, "exp_vec">; -def IL_OP_F_2_D : ILOpCode<55, "f2d">; -def IL_OP_FLR : ILOpCode<56, "flr">; -def IL_OP_FRC : ILOpCode<57, "frc">; -def IL_OP_FTOI : ILOpCode<58, "ftoi">; -def IL_OP_FTOU : ILOpCode<59, "ftou">; -def IL_OP_FUNC : ILOpCode<60, "func">; -def IL_OP_GE : ILOpCode<61, "ge">; -def IL_OP_I_ADD : ILOpCode<62, "iadd">; -def IL_OP_I_EQ : ILOpCode<63, "ieq">; -def IL_OP_I_GE : ILOpCode<64, "ige">; -def IL_OP_I_LT : ILOpCode<65, "ilt">; -def IL_OP_I_MAD : ILOpCode<66, "imad">; -def IL_OP_I_MAX : ILOpCode<67, "imax">; -def IL_OP_I_MIN : ILOpCode<68, "imin">; -def IL_OP_I_MUL : ILOpCode<69, "imul">; -def IL_OP_I_MUL_HIGH : ILOpCode<70, "imul_high">; -def IL_OP_I_NE : ILOpCode<71, "ine">; -def IL_OP_I_NEGATE : ILOpCode<72, "inegate">; -def IL_OP_I_NOT : ILOpCode<73, "inot">; -def IL_OP_I_OR : ILOpCode<74, "ior">; -def IL_OP_I_SHL : ILOpCode<75, "ishl">; -def IL_OP_I_SHR : ILOpCode<76, "ishr">; -def IL_OP_I_XOR : ILOpCode<77, "ixor">; -def IL_OP_IF_LOGICALNZ : ILOpCode<78, "if_logicalnz">; -def IL_OP_IF_LOGICALZ : ILOpCode<79, "if_logicalz">; -def IL_OP_IFC : ILOpCode<80, "ifc">; -def IL_OP_ITOF : ILOpCode<81, "itof">; -def IL_OP_LN : ILOpCode<82, "ln">; -def IL_OP_LOG : ILOpCode<83, "log">; -def IL_OP_LOG_VEC : ILOpCode<84, "log_vec">; -def IL_OP_LOOP : ILOpCode<85, "loop">; -def IL_OP_LT : ILOpCode<86, "lt">; -def IL_OP_MAD : ILOpCode<87, "mad_ieee">; -def IL_OP_MAX : ILOpCode<88, "max_ieee">; -def IL_OP_MIN : ILOpCode<89, "min_ieee">; -def IL_OP_MOD : ILOpCode<90, "mod_ieee">; -def IL_OP_MOV : ILOpCode<91, "mov">; -def IL_OP_MUL_IEEE : ILOpCode<92, "mul_ieee">; -def IL_OP_NE : ILOpCode<93, "ne">; -def IL_OP_NRM : ILOpCode<94, "nrm_nrm4_zeroop(zero)">; -def IL_OP_POW : ILOpCode<95, "pow">; -def IL_OP_RCP : ILOpCode<96, "rcp">; -def IL_OP_RET : ILOpCode<97, "ret">; -def IL_OP_RET_DYN : ILOpCode<98, "ret_dyn">; -def IL_OP_RET_LOGICALNZ : ILOpCode<99, "ret_logicalnz">; -def IL_OP_RET_LOGICALZ : ILOpCode<100, "ret_logicalz">; -def IL_OP_RND : ILOpCode<101, "rnd">; -def IL_OP_ROUND_NEAR : ILOpCode<102, "round_nearest">; -def IL_OP_ROUND_NEG_INF : ILOpCode<103, "round_neginf">; -def IL_OP_ROUND_POS_INF : ILOpCode<104, "round_plusinf">; -def IL_OP_ROUND_ZERO : ILOpCode<105, "round_z">; -def IL_OP_RSQ : ILOpCode<106, "rsq">; -def IL_OP_RSQ_VEC : ILOpCode<107, "rsq_vec">; -def IL_OP_SAMPLE : ILOpCode<108, "sample">; -def IL_OP_SAMPLE_L : ILOpCode<109, "sample_l">; -def IL_OP_SET : ILOpCode<110, "set">; -def IL_OP_SGN : ILOpCode<111, "sgn">; -def IL_OP_SIN : ILOpCode<112, "sin">; -def IL_OP_SIN_VEC : ILOpCode<113, "sin_vec">; -def IL_OP_SUB : ILOpCode<114, "sub">; -def IL_OP_SWITCH : ILOpCode<115, "switch">; -def IL_OP_TRC : ILOpCode<116, "trc">; -def IL_OP_U_DIV : ILOpCode<117, "udiv">; -def IL_OP_U_GE : ILOpCode<118, "uge">; -def IL_OP_U_LT : ILOpCode<119, "ult">; -def IL_OP_U_MAD : ILOpCode<120, "umad">; -def IL_OP_U_MAX : ILOpCode<121, "umax">; -def IL_OP_U_MIN : ILOpCode<122, "umin">; -def IL_OP_U_MOD : ILOpCode<123, "umod">; -def IL_OP_U_MUL : ILOpCode<124, "umul">; -def IL_OP_U_MUL_HIGH : ILOpCode<125, "umul_high">; -def IL_OP_U_SHR : ILOpCode<126, "ushr">; -def IL_OP_UTOF : ILOpCode<127, "utof">; -def IL_OP_WHILE : ILOpCode<128, "whileloop">; -// SC IL instructions that are not in CAL IL -def IL_OP_ACOS : ILOpCode<129, "acos">; -def IL_OP_ASIN : ILOpCode<130, "asin">; -def IL_OP_EXN : ILOpCode<131, "exn">; -def IL_OP_UBIT_REVERSE : ILOpCode<132, "ubit_reverse">; -def IL_OP_UBIT_EXTRACT : ILOpCode<133, "ubit_extract">; -def IL_OP_IBIT_EXTRACT : ILOpCode<134, "ibit_extract">; -def IL_OP_SQRT : ILOpCode<135, "sqrt">; -def IL_OP_SQRT_VEC : ILOpCode<136, "sqrt_vec">; -def IL_OP_ATAN : ILOpCode<137, "atan">; -def IL_OP_TAN : ILOpCode<137, "tan">; -def IL_OP_D_DIV : ILOpCode<138, "ddiv">; -def IL_OP_F_NEG : ILOpCode<139, "mov">; -def IL_OP_GT : ILOpCode<140, "gt">; -def IL_OP_LE : ILOpCode<141, "lt">; -def IL_OP_DIST : ILOpCode<142, "dist">; -def IL_OP_LEN : ILOpCode<143, "len">; -def IL_OP_MACRO : ILOpCode<144, "mcall">; -def IL_OP_INTR : ILOpCode<145, "call">; -def IL_OP_I_FFB_HI : ILOpCode<146, "ffb_hi">; -def IL_OP_I_FFB_LO : ILOpCode<147, "ffb_lo">; -def IL_OP_BARRIER : ILOpCode<148, "fence_threads_memory_lds">; -def IL_OP_BARRIER_LOCAL : ILOpCode<149, "fence_threads_lds">; -def IL_OP_BARRIER_GLOBAL : ILOpCode<150, "fence_threads_memory">; -def IL_OP_FENCE : ILOpCode<151, "fence_lds_memory">; -def IL_OP_FENCE_READ_ONLY : ILOpCode<152, "fence_lds_mem_read_only">; -def IL_OP_FENCE_WRITE_ONLY : ILOpCode<153, "fence_lds_mem_write_only">; -def IL_PSEUDO_INST : ILOpCode<154, ";Pseudo Op">; -def IL_OP_UNPACK_0 : ILOpCode<155, "unpack0">; -def IL_OP_UNPACK_1 : ILOpCode<156, "unpack1">; -def IL_OP_UNPACK_2 : ILOpCode<157, "unpack2">; -def IL_OP_UNPACK_3 : ILOpCode<158, "unpack3">; -def IL_OP_PI_REDUCE : ILOpCode<159, "pireduce">; -def IL_OP_IBIT_COUNT : ILOpCode<160, "icbits">; -def IL_OP_I_FFB_SGN : ILOpCode<161, "ffb_shi">; -def IL_OP_F2U4 : ILOpCode<162, "f_2_u4">; -def IL_OP_BIT_ALIGN : ILOpCode<163, "bitalign">; -def IL_OP_BYTE_ALIGN : ILOpCode<164, "bytealign">; -def IL_OP_U4_LERP : ILOpCode<165, "u4lerp">; -def IL_OP_SAD : ILOpCode<166, "sad">; -def IL_OP_SAD_HI : ILOpCode<167, "sadhi">; -def IL_OP_SAD4 : ILOpCode<168, "sad4">; -def IL_OP_UBIT_INSERT : ILOpCode<169, "ubit_insert">; -def IL_OP_I_CARRY : ILOpCode<170, "icarry">; -def IL_OP_I_BORROW : ILOpCode<171, "iborrow">; -def IL_OP_U_MAD24 : ILOpCode<172, "umad24">; -def IL_OP_U_MUL24 : ILOpCode<173, "umul24">; -def IL_OP_I_MAD24 : ILOpCode<174, "imad24">; -def IL_OP_I_MUL24 : ILOpCode<175, "imul24">; -def IL_OP_CLAMP : ILOpCode<176, "clamp">; -def IL_OP_LERP : ILOpCode<177, "lrp">; -def IL_OP_FMA : ILOpCode<178, "fma">; -def IL_OP_D_MIN : ILOpCode<179, "dmin">; -def IL_OP_D_MAX : ILOpCode<180, "dmax">; -def IL_OP_D_SQRT : ILOpCode<181, "dsqrt">; -def IL_OP_DP2_ADD : ILOpCode<182, "dp2add">; -def IL_OP_F16_TO_F32 : ILOpCode<183, "f162f">; -def IL_OP_F32_TO_F16 : ILOpCode<184, "f2f16">; -def IL_REG_LOCAL_ID_FLAT : ILOpCode<185, "vTidInGrpFlat">; -def IL_REG_LOCAL_ID : ILOpCode<186, "vTidInGrp">; -def IL_REG_GLOBAL_ID_FLAT : ILOpCode<187, "vAbsTidFlag">; -def IL_REG_GLOBAL_ID : ILOpCode<188, "vAbsTid">; -def IL_REG_GROUP_ID_FLAT : ILOpCode<189, "vThreadGrpIDFlat">; -def IL_REG_GROUP_ID : ILOpCode<190, "vThreadGrpID">; -def IL_OP_D_RCP : ILOpCode<191, "drcp_zeroop(infinity)">; -def IL_OP_D_RSQ : ILOpCode<192, "drsq_zeroop(infinity)">; -def IL_OP_D_MOV : ILOpCode<193, "dmov">; -def IL_OP_D_MOVC : ILOpCode<194, "dmovc">; -def IL_OP_NOP : ILOpCode<195, "nop">; -def IL_OP_UAV_ADD : ILOpCode<196, "uav_add">; -def IL_OP_UAV_AND : ILOpCode<197, "uav_and">; -def IL_OP_UAV_MAX : ILOpCode<198, "uav_max">; -def IL_OP_UAV_MIN : ILOpCode<199, "uav_min">; -def IL_OP_UAV_OR : ILOpCode<200, "uav_or">; -def IL_OP_UAV_RSUB : ILOpCode<201, "uav_rsub">; -def IL_OP_UAV_SUB : ILOpCode<202, "uav_sub">; -def IL_OP_UAV_UMAX : ILOpCode<203, "uav_umax">; -def IL_OP_UAV_UMIN : ILOpCode<204, "uav_umin">; -def IL_OP_UAV_XOR : ILOpCode<205, "uav_xor">; -def IL_OP_UAV_INC : ILOpCode<206, "uav_uinc">; -def IL_OP_UAV_DEC : ILOpCode<207, "uav_udec">; -def IL_OP_UAV_CMP : ILOpCode<208, "uav_cmp">; -def IL_OP_UAV_READ_ADD : ILOpCode<209, "uav_read_add">; -def IL_OP_UAV_READ_AND : ILOpCode<210, "uav_read_and">; -def IL_OP_UAV_READ_MAX : ILOpCode<211, "uav_read_max">; -def IL_OP_UAV_READ_MIN : ILOpCode<212, "uav_read_min">; -def IL_OP_UAV_READ_OR : ILOpCode<213, "uav_read_or">; -def IL_OP_UAV_READ_RSUB : ILOpCode<214, "uav_read_rsub">; -def IL_OP_UAV_READ_SUB : ILOpCode<215, "uav_read_sub">; -def IL_OP_UAV_READ_UMAX : ILOpCode<216, "uav_read_umax">; -def IL_OP_UAV_READ_UMIN : ILOpCode<217, "uav_read_umin">; -def IL_OP_UAV_READ_XOR : ILOpCode<218, "uav_read_xor">; -def IL_OP_UAV_READ_INC : ILOpCode<219, "uav_read_uinc">; -def IL_OP_UAV_READ_DEC : ILOpCode<220, "uav_read_udec">; -def IL_OP_UAV_READ_XCHG : ILOpCode<221, "uav_read_xchg">; -def IL_OP_UAV_READ_CMPXCHG : ILOpCode<222, "uav_read_cmp_xchg">; -def IL_OP_LDS_ADD : ILOpCode<223, "lds_add">; -def IL_OP_LDS_AND : ILOpCode<224, "lds_and">; -def IL_OP_LDS_MAX : ILOpCode<225, "lds_max">; -def IL_OP_LDS_MIN : ILOpCode<226, "lds_min">; -def IL_OP_LDS_OR : ILOpCode<227, "lds_or">; -def IL_OP_LDS_RSUB : ILOpCode<228, "lds_rsub">; -def IL_OP_LDS_SUB : ILOpCode<229, "lds_sub">; -def IL_OP_LDS_UMAX : ILOpCode<230, "lds_umax">; -def IL_OP_LDS_UMIN : ILOpCode<231, "lds_umin">; -def IL_OP_LDS_XOR : ILOpCode<232, "lds_xor">; -def IL_OP_LDS_INC : ILOpCode<233, "lds_inc">; -def IL_OP_LDS_DEC : ILOpCode<234, "lds_dec">; -def IL_OP_LDS_CMP : ILOpCode<235, "lds_cmp">; -def IL_OP_LDS_READ_ADD : ILOpCode<236, "lds_read_add">; -def IL_OP_LDS_READ_AND : ILOpCode<237, "lds_read_and">; -def IL_OP_LDS_READ_MAX : ILOpCode<238, "lds_read_max">; -def IL_OP_LDS_READ_MIN : ILOpCode<239, "lds_read_min">; -def IL_OP_LDS_READ_OR : ILOpCode<240, "lds_read_or">; -def IL_OP_LDS_READ_RSUB : ILOpCode<241, "lds_read_rsub">; -def IL_OP_LDS_READ_SUB : ILOpCode<242, "lds_read_sub">; -def IL_OP_LDS_READ_UMAX : ILOpCode<243, "lds_read_umax">; -def IL_OP_LDS_READ_UMIN : ILOpCode<244, "lds_read_umin">; -def IL_OP_LDS_READ_XOR : ILOpCode<245, "lds_read_xor">; -def IL_OP_LDS_READ_INC : ILOpCode<246, "lds_read_inc">; -def IL_OP_LDS_READ_DEC : ILOpCode<247, "lds_read_dec">; -def IL_OP_LDS_READ_XCHG : ILOpCode<248, "lds_read_xchg">; -def IL_OP_LDS_READ_CMPXCHG : ILOpCode<249, "lds_read_cmp_xchg">; -def IL_OP_GDS_ADD : ILOpCode<250, "gds_add">; -def IL_OP_GDS_AND : ILOpCode<251, "gds_and">; -def IL_OP_GDS_MAX : ILOpCode<252, "gds_max">; -def IL_OP_GDS_MIN : ILOpCode<253, "gds_min">; -def IL_OP_GDS_OR : ILOpCode<254, "gds_or">; -def IL_OP_GDS_RSUB : ILOpCode<255, "gds_rsub">; -def IL_OP_GDS_SUB : ILOpCode<256, "gds_sub">; -def IL_OP_GDS_UMAX : ILOpCode<257, "gds_umax">; -def IL_OP_GDS_UMIN : ILOpCode<258, "gds_umin">; -def IL_OP_GDS_MSKOR : ILOpCode<259, "gds_mskor">; -def IL_OP_GDS_XOR : ILOpCode<260, "gds_xor">; -def IL_OP_GDS_INC : ILOpCode<261, "gds_inc">; -def IL_OP_GDS_DEC : ILOpCode<262, "gds_dec">; -def IL_OP_GDS_CMP : ILOpCode<263, "gds_cmp">; -def IL_OP_GDS_READ_ADD : ILOpCode<264, "gds_read_add">; -def IL_OP_GDS_READ_AND : ILOpCode<265, "gds_read_and">; -def IL_OP_GDS_READ_MAX : ILOpCode<266, "gds_read_max">; -def IL_OP_GDS_READ_MIN : ILOpCode<267, "gds_read_min">; -def IL_OP_GDS_READ_OR : ILOpCode<268, "gds_read_or">; -def IL_OP_GDS_READ_RSUB : ILOpCode<269, "gds_read_rsub">; -def IL_OP_GDS_READ_SUB : ILOpCode<270, "gds_read_sub">; -def IL_OP_GDS_READ_UMAX : ILOpCode<271, "gds_read_umax">; -def IL_OP_GDS_READ_UMIN : ILOpCode<272, "gds_read_umin">; -def IL_OP_GDS_READ_MSKOR : ILOpCode<273, "gds_read_mskor">; -def IL_OP_GDS_READ_XOR : ILOpCode<274, "gds_read_xor">; -def IL_OP_GDS_READ_INC : ILOpCode<275, "gds_read_inc">; -def IL_OP_GDS_READ_DEC : ILOpCode<276, "gds_read_dec">; -def IL_OP_GDS_READ_XCHG : ILOpCode<277, "gds_read_xchg">; -def IL_OP_GDS_READ_CMPXCHG : ILOpCode<278, "gds_read_cmp_xchg">; -def IL_OP_APPEND_BUF_ALLOC : ILOpCode<279, "append_buf_alloc">; -def IL_OP_APPEND_BUF_CONSUME : ILOpCode<280, "append_buf_consume">; -def IL_OP_I64_ADD : ILOpCode<281, "i64add">; -def IL_OP_I64_MAX : ILOpCode<282, "i64max">; -def IL_OP_U64_MAX : ILOpCode<283, "u64max">; -def IL_OP_I64_MIN : ILOpCode<284, "i64min">; -def IL_OP_U64_MIN : ILOpCode<285, "u64min">; -def IL_OP_I64_NEGATE : ILOpCode<286, "i64negate">; -def IL_OP_I64_SHL : ILOpCode<287, "i64shl">; -def IL_OP_I64_SHR : ILOpCode<288, "i64shr">; -def IL_OP_U64_SHR : ILOpCode<289, "u64shr">; -def IL_OP_I64_EQ : ILOpCode<290, "i64eq">; -def IL_OP_I64_GE : ILOpCode<291, "i64ge">; -def IL_OP_U64_GE : ILOpCode<292, "u64ge">; -def IL_OP_I64_LT : ILOpCode<293, "i64lt">; -def IL_OP_U64_LT : ILOpCode<294, "u64lt">; -def IL_OP_I64_NE : ILOpCode<295, "i64ne">; -def IL_OP_U_MULHI24 : ILOpCode<296, "umul24_high">; -def IL_OP_I_MULHI24 : ILOpCode<297, "imul24_high">; -def IL_OP_GDS_LOAD : ILOpCode<298, "gds_load">; -def IL_OP_GDS_STORE : ILOpCode<299, "gds_store">; -def IL_OP_LDS_LOAD : ILOpCode<300, "lds_load">; -def IL_OP_LDS_LOAD_VEC : ILOpCode<301, "lds_load_vec">; -def IL_OP_LDS_LOAD_BYTE : ILOpCode<302, "lds_load_byte">; -def IL_OP_LDS_LOAD_UBYTE : ILOpCode<303, "lds_load_ubyte">; -def IL_OP_LDS_LOAD_SHORT : ILOpCode<304, "lds_load_short">; -def IL_OP_LDS_LOAD_USHORT : ILOpCode<305, "lds_load_ushort">; -def IL_OP_LDS_STORE : ILOpCode<306, "lds_store">; -def IL_OP_LDS_STORE_VEC : ILOpCode<307, "lds_store_vec">; -def IL_OP_LDS_STORE_BYTE : ILOpCode<308, "lds_store_byte">; -def IL_OP_LDS_STORE_SHORT : ILOpCode<309, "lds_store_short">; -def IL_OP_RAW_UAV_LOAD : ILOpCode<310, "uav_raw_load">; -def IL_OP_RAW_UAV_STORE : ILOpCode<311, "uav_raw_store">; -def IL_OP_ARENA_UAV_LOAD : ILOpCode<312, "uav_arena_load">; -def IL_OP_ARENA_UAV_STORE : ILOpCode<313, "uav_arena_store">; -def IL_OP_LDS_MSKOR : ILOpCode<314, "lds_mskor">; -def IL_OP_LDS_READ_MSKOR : ILOpCode<315, "lds_read_mskor">; -def IL_OP_UAV_BYTE_LOAD : ILOpCode<316, "uav_byte_load">; -def IL_OP_UAV_UBYTE_LOAD : ILOpCode<317, "uav_ubyte_load">; -def IL_OP_UAV_SHORT_LOAD : ILOpCode<318, "uav_short_load">; -def IL_OP_UAV_USHORT_LOAD : ILOpCode<319, "uav_ushort_load">; -def IL_OP_UAV_BYTE_STORE : ILOpCode<320, "uav_byte_store">; -def IL_OP_UAV_SHORT_STORE : ILOpCode<320, "uav_short_store">; -def IL_OP_UAV_STORE : ILOpCode<321, "uav_store">; -def IL_OP_UAV_LOAD : ILOpCode<322, "uav_load">; -def IL_OP_MUL : ILOpCode<323, "mul">; -def IL_OP_DIV_INF : ILOpCode<324, "div_zeroop(infinity)">; -def IL_OP_DIV_FLTMAX : ILOpCode<325, "div_zeroop(fltmax)">; -def IL_OP_DIV_ZERO : ILOpCode<326, "div_zeroop(zero)">; -def IL_OP_DIV_INFELSEMAX : ILOpCode<327, "div_zeroop(inf_else_max)">; -def IL_OP_FTOI_FLR : ILOpCode<328, "ftoi_flr">; -def IL_OP_FTOI_RPI : ILOpCode<329, "ftoi_rpi">; -def IL_OP_F32_TO_F16_NEAR : ILOpCode<330, "f2f16_near">; -def IL_OP_F32_TO_F16_NEG_INF : ILOpCode<331, "f2f16_neg_inf">; -def IL_OP_F32_TO_F16_PLUS_INF : ILOpCode<332, "f2f16_plus_inf">; -def IL_OP_I64_MUL : ILOpCode<333, "i64mul">; -def IL_OP_U64_MUL : ILOpCode<334, "u64mul">; -def IL_OP_CU_ID : ILOpCode<355, "cu_id">; -def IL_OP_WAVE_ID : ILOpCode<356, "wave_id">; -def IL_OP_I64_SUB : ILOpCode<357, "i64sub">; -def IL_OP_I64_DIV : ILOpCode<358, "i64div">; -def IL_OP_U64_DIV : ILOpCode<359, "u64div">; -def IL_OP_I64_MOD : ILOpCode<360, "i64mod">; -def IL_OP_U64_MOD : ILOpCode<361, "u64mod">; -def IL_DCL_GWS_THREAD_COUNT : ILOpCode<362, "dcl_gws_thread_count">; -def IL_DCL_SEMAPHORE : ILOpCode<363, "dcl_semaphore">; -def IL_OP_SEMAPHORE_INIT : ILOpCode<364, "init_semaphore">; -def IL_OP_SEMAPHORE_WAIT : ILOpCode<365, "semaphore_wait">; -def IL_OP_SEMAPHORE_SIGNAL : ILOpCode<366, "semaphore_signal">; -def IL_OP_BARRIER_REGION : ILOpCode<377, "fence_threads_gds">; -def IL_OP_BFI : ILOpCode<394, "bfi">; -def IL_OP_BFM : ILOpCode<395, "bfm">; -def IL_DBG_STRING : ILOpCode<396, "dbg_string">; -def IL_DBG_LINE : ILOpCode<397, "dbg_line">; -def IL_DBG_TEMPLOC : ILOpCode<398, "dbg_temploc">; diff --git a/src/gallium/drivers/radeon/AMDILFormats.td b/src/gallium/drivers/radeon/AMDILFormats.td deleted file mode 100644 index 5a71ded9b68..00000000000 --- a/src/gallium/drivers/radeon/AMDILFormats.td +++ /dev/null @@ -1,175 +0,0 @@ -//==- AMDILFormats.td - AMDIL Instruction Formats ----*- tablegen -*-==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// -// -//===--------------------------------------------------------------------===// -include "AMDILTokenDesc.td" - -//===--------------------------------------------------------------------===// -// The parent IL instruction class that inherits the Instruction class. This -// class sets the corresponding namespace, the out and input dag lists the -// pattern to match to and the string to print out for the assembly printer. -//===--------------------------------------------------------------------===// -class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> -: Instruction { - - let Namespace = "AMDGPU"; - dag OutOperandList = outs; - dag InOperandList = ins; - ILOpCode operation = op; - let Pattern = pattern; - let AsmString = !strconcat(asmstr, "\n"); - let isPseudo = 1; - let Itinerary = NullALU; - bit hasIEEEFlag = 0; - bit hasZeroOpFlag = 0; -} - -//===--------------------------------------------------------------------===// -// Class that has one input parameters and one output parameter. -// The basic pattern for this class is "Opcode Dst, Src0" and -// handles the unary math operators. -// It sets the binary token ILSrc, ILSrcMod, ILRelAddr and ILSrc and ILSrcMod -// if the addressing is register relative for input and output register 0. -//===--------------------------------------------------------------------===// -class OneInOneOut<ILOpCode op, dag outs, dag ins, - string asmstr, list<dag> pattern> - : ILFormat<op, outs, ins, asmstr, pattern> -{ - ILDst dst_reg; - ILDstMod dst_mod; - ILRelAddr dst_rel; - ILSrc dst_reg_rel; - ILSrcMod dst_reg_rel_mod; - ILSrc src0_reg; - ILSrcMod src0_mod; - ILRelAddr src0_rel; - ILSrc src0_reg_rel; - ILSrcMod src0_reg_rel_mod; -} - -//===--------------------------------------------------------------------===// -// This class is similiar to the UnaryOp class, however, there is no -// result value to assign. -//===--------------------------------------------------------------------===// -class UnaryOpNoRet<ILOpCode op, dag outs, dag ins, - string asmstr, list<dag> pattern> - : ILFormat<op, outs, ins, asmstr, pattern> -{ - ILSrc src0_reg; - ILSrcMod src0_mod; - ILRelAddr src0_rel; - ILSrc src0_reg_rel; - ILSrcMod src0_reg_rel_mod; -} - -//===--------------------------------------------------------------------===// -// Set of classes that have two input parameters and one output parameter. -// The basic pattern for this class is "Opcode Dst, Src0, Src1" and -// handles the binary math operators and comparison operations. -// It sets the binary token ILSrc, ILSrcMod, ILRelAddr and ILSrc and ILSrcMod -// if the addressing is register relative for input register 1. -//===--------------------------------------------------------------------===// -class TwoInOneOut<ILOpCode op, dag outs, dag ins, - string asmstr, list<dag> pattern> - : OneInOneOut<op, outs, ins, asmstr, pattern> -{ - ILSrc src1_reg; - ILSrcMod src1_mod; - ILRelAddr src1_rel; - ILSrc src1_reg_rel; - ILSrcMod src1_reg_rel_mod; -} - -//===--------------------------------------------------------------------===// -// Similiar to the UnaryOpNoRet class, but takes as arguments two input -// operands. Used mainly for barrier instructions on PC platform. -//===--------------------------------------------------------------------===// -class BinaryOpNoRet<ILOpCode op, dag outs, dag ins, - string asmstr, list<dag> pattern> - : UnaryOpNoRet<op, outs, ins, asmstr, pattern> -{ - ILSrc src1_reg; - ILSrcMod src1_mod; - ILRelAddr src1_rel; - ILSrc src1_reg_rel; - ILSrcMod src1_reg_rel_mod; -} - -//===--------------------------------------------------------------------===// -// Set of classes that have three input parameters and one output parameter. -// The basic pattern for this class is "Opcode Dst, Src0, Src1, Src2" and -// handles the mad and conditional mov instruction. -// It sets the binary token ILSrc, ILSrcMod, ILRelAddr and ILSrc and ILSrcMod -// if the addressing is register relative. -// This class is the parent class of TernaryOp -//===--------------------------------------------------------------------===// -class ThreeInOneOut<ILOpCode op, dag outs, dag ins, - string asmstr, list<dag> pattern> - : TwoInOneOut<op, outs, ins, asmstr, pattern> { - ILSrc src2_reg; - ILSrcMod src2_mod; - ILRelAddr src2_rel; - ILSrc src2_reg_rel; - ILSrcMod src2_reg_rel_mod; - } - -//===--------------------------------------------------------------------===// -// Intrinsic classes -// Generic versions of the above classes but for Target specific intrinsics -// instead of SDNode patterns. -//===--------------------------------------------------------------------===// -let TargetPrefix = "AMDIL", isTarget = 1 in { - class VoidIntLong : - Intrinsic<[llvm_i64_ty], [], []>; - class VoidIntInt : - Intrinsic<[llvm_i32_ty], [], []>; - class VoidIntBool : - Intrinsic<[llvm_i32_ty], [], []>; - class UnaryIntInt : - Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>; - class UnaryIntFloat : - Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; - class ConvertIntFTOI : - Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>; - class ConvertIntITOF : - Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty], [IntrNoMem]>; - class UnaryIntNoRetInt : - Intrinsic<[], [llvm_anyint_ty], []>; - class UnaryIntNoRetFloat : - Intrinsic<[], [llvm_anyfloat_ty], []>; - class BinaryIntInt : - Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; - class BinaryIntFloat : - Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; - class BinaryIntNoRetInt : - Intrinsic<[], [llvm_anyint_ty, LLVMMatchType<0>], []>; - class BinaryIntNoRetFloat : - Intrinsic<[], [llvm_anyfloat_ty, LLVMMatchType<0>], []>; - class TernaryIntInt : - Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, - LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; - class TernaryIntFloat : - Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, - LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; - class QuaternaryIntInt : - Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, - LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; - class UnaryAtomicInt : - Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; - class BinaryAtomicInt : - Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; - class TernaryAtomicInt : - Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty]>; - class UnaryAtomicIntNoRet : - Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; - class BinaryAtomicIntNoRet : - Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; - class TernaryAtomicIntNoRet : - Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; -} diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.td b/src/gallium/drivers/radeon/AMDILInstrInfo.td index 969618e1afc..ad7f618be52 100644 --- a/src/gallium/drivers/radeon/AMDILInstrInfo.td +++ b/src/gallium/drivers/radeon/AMDILInstrInfo.td @@ -70,32 +70,221 @@ def Has32BitPtr : Predicate<"!Subtarget.is64bit()">; //===--------------------------------------------------------------------===// // Custom Operands //===--------------------------------------------------------------------===// -include "AMDILOperands.td" +def brtarget : Operand<OtherVT>; //===--------------------------------------------------------------------===// // Custom Selection DAG Type Profiles //===--------------------------------------------------------------------===// -include "AMDILProfiles.td" +//===----------------------------------------------------------------------===// +// Generic Profile Types +//===----------------------------------------------------------------------===// + +def SDTIL_GenBinaryOp : SDTypeProfile<1, 2, [ + SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> + ]>; +def SDTIL_GenTernaryOp : SDTypeProfile<1, 3, [ + SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<2, 3> + ]>; +def SDTIL_GenVecBuild : SDTypeProfile<1, 1, [ + SDTCisEltOfVec<1, 0> + ]>; + +//===----------------------------------------------------------------------===// +// Flow Control Profile Types +//===----------------------------------------------------------------------===// +// Branch instruction where second and third are basic blocks +def SDTIL_BRCond : SDTypeProfile<0, 2, [ + SDTCisVT<0, OtherVT> + ]>; +// Comparison instruction +def SDTIL_Cmp : SDTypeProfile<1, 3, [ + SDTCisSameAs<0, 2>, SDTCisSameAs<2,3>, SDTCisVT<1, i32> + ]>; //===--------------------------------------------------------------------===// // Custom Selection DAG Nodes //===--------------------------------------------------------------------===// -include "AMDILNodes.td" +//===----------------------------------------------------------------------===// +// Flow Control DAG Nodes +//===----------------------------------------------------------------------===// +def IL_brcond : SDNode<"AMDILISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>; + +//===----------------------------------------------------------------------===// +// Comparison DAG Nodes +//===----------------------------------------------------------------------===// +def IL_cmp : SDNode<"AMDILISD::CMP", SDTIL_Cmp>; + +//===----------------------------------------------------------------------===// +// Call/Return DAG Nodes +//===----------------------------------------------------------------------===// +def IL_retflag : SDNode<"AMDILISD::RET_FLAG", SDTNone, + [SDNPHasChain, SDNPOptInGlue]>; + +//===--------------------------------------------------------------------===// +// Instructions +//===--------------------------------------------------------------------===// +// Floating point math functions +def IL_cmov_logical : SDNode<"AMDILISD::CMOVLOG", SDTIL_GenTernaryOp>; +def IL_div_inf : SDNode<"AMDILISD::DIV_INF", SDTIL_GenBinaryOp>; +def IL_mad : SDNode<"AMDILISD::MAD", SDTIL_GenTernaryOp>; + +//===----------------------------------------------------------------------===// +// Integer functions +//===----------------------------------------------------------------------===// +def IL_umul : SDNode<"AMDILISD::UMUL" , SDTIntBinOp, + [SDNPCommutative, SDNPAssociative]>; + +//===----------------------------------------------------------------------===// +// Vector functions +//===----------------------------------------------------------------------===// +def IL_vbuild : SDNode<"AMDILISD::VBUILD", SDTIL_GenVecBuild, + []>; //===--------------------------------------------------------------------===// // Custom Pattern DAG Nodes //===--------------------------------------------------------------------===// -include "AMDILPatterns.td" +def global_store : PatFrag<(ops node:$val, node:$ptr), + (store node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast<StoreSDNode>(N)); +}]>; + +//===----------------------------------------------------------------------===// +// Load pattern fragments +//===----------------------------------------------------------------------===// +// Global address space loads +def global_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return isGlobalLoad(dyn_cast<LoadSDNode>(N)); +}]>; +// Constant address space loads +def constant_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); +}]>; + +//===----------------------------------------------------------------------===// +// Complex addressing mode patterns +//===----------------------------------------------------------------------===// +def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>; +def ADDRF : ComplexPattern<i32, 2, "SelectADDR", [frameindex], []>; +def ADDR64 : ComplexPattern<i64, 2, "SelectADDR64", [], []>; +def ADDR64F : ComplexPattern<i64, 2, "SelectADDR64", [frameindex], []>; + + +//===----------------------------------------------------------------------===// +// Conditional Instruction Pattern Leafs +//===----------------------------------------------------------------------===// +class IL_CC_Op<int N> : PatLeaf<(i32 N)>; +def IL_CC_D_EQ : IL_CC_Op<0>; +def IL_CC_D_GE : IL_CC_Op<1>; +def IL_CC_D_LT : IL_CC_Op<2>; +def IL_CC_D_NE : IL_CC_Op<3>; +def IL_CC_F_EQ : IL_CC_Op<4>; +def IL_CC_F_GE : IL_CC_Op<5>; +def IL_CC_F_LT : IL_CC_Op<6>; +def IL_CC_F_NE : IL_CC_Op<7>; +def IL_CC_I_EQ : IL_CC_Op<8>; +def IL_CC_I_GE : IL_CC_Op<9>; +def IL_CC_I_LT : IL_CC_Op<10>; +def IL_CC_I_NE : IL_CC_Op<11>; +def IL_CC_U_GE : IL_CC_Op<12>; +def IL_CC_U_LT : IL_CC_Op<13>; +// Pseudo IL comparison instructions that aren't natively supported +def IL_CC_F_GT : IL_CC_Op<14>; +def IL_CC_U_GT : IL_CC_Op<15>; +def IL_CC_I_GT : IL_CC_Op<16>; +def IL_CC_D_GT : IL_CC_Op<17>; +def IL_CC_F_LE : IL_CC_Op<18>; +def IL_CC_U_LE : IL_CC_Op<19>; +def IL_CC_I_LE : IL_CC_Op<20>; +def IL_CC_D_LE : IL_CC_Op<21>; +def IL_CC_F_UNE : IL_CC_Op<22>; +def IL_CC_F_UEQ : IL_CC_Op<23>; +def IL_CC_F_ULT : IL_CC_Op<24>; +def IL_CC_F_UGT : IL_CC_Op<25>; +def IL_CC_F_ULE : IL_CC_Op<26>; +def IL_CC_F_UGE : IL_CC_Op<27>; +def IL_CC_F_ONE : IL_CC_Op<28>; +def IL_CC_F_OEQ : IL_CC_Op<29>; +def IL_CC_F_OLT : IL_CC_Op<30>; +def IL_CC_F_OGT : IL_CC_Op<31>; +def IL_CC_F_OLE : IL_CC_Op<32>; +def IL_CC_F_OGE : IL_CC_Op<33>; +def IL_CC_D_UNE : IL_CC_Op<34>; +def IL_CC_D_UEQ : IL_CC_Op<35>; +def IL_CC_D_ULT : IL_CC_Op<36>; +def IL_CC_D_UGT : IL_CC_Op<37>; +def IL_CC_D_ULE : IL_CC_Op<38>; +def IL_CC_D_UGE : IL_CC_Op<39>; +def IL_CC_D_ONE : IL_CC_Op<30>; +def IL_CC_D_OEQ : IL_CC_Op<41>; +def IL_CC_D_OLT : IL_CC_Op<42>; +def IL_CC_D_OGT : IL_CC_Op<43>; +def IL_CC_D_OLE : IL_CC_Op<44>; +def IL_CC_D_OGE : IL_CC_Op<45>; +def IL_CC_U_EQ : IL_CC_Op<46>; +def IL_CC_U_NE : IL_CC_Op<47>; +def IL_CC_F_O : IL_CC_Op<48>; +def IL_CC_D_O : IL_CC_Op<49>; +def IL_CC_F_UO : IL_CC_Op<50>; +def IL_CC_D_UO : IL_CC_Op<51>; +def IL_CC_L_LE : IL_CC_Op<52>; +def IL_CC_L_GE : IL_CC_Op<53>; +def IL_CC_L_EQ : IL_CC_Op<54>; +def IL_CC_L_NE : IL_CC_Op<55>; +def IL_CC_L_LT : IL_CC_Op<56>; +def IL_CC_L_GT : IL_CC_Op<57>; +def IL_CC_UL_LE : IL_CC_Op<58>; +def IL_CC_UL_GE : IL_CC_Op<59>; +def IL_CC_UL_EQ : IL_CC_Op<60>; +def IL_CC_UL_NE : IL_CC_Op<61>; +def IL_CC_UL_LT : IL_CC_Op<62>; +def IL_CC_UL_GT : IL_CC_Op<63>; //===----------------------------------------------------------------------===// // Instruction format classes //===----------------------------------------------------------------------===// -include "AMDILFormats.td" +class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern> +: Instruction { + + let Namespace = "AMDGPU"; + dag OutOperandList = outs; + dag InOperandList = ins; + let Pattern = pattern; + let AsmString = !strconcat(asmstr, "\n"); + let isPseudo = 1; + let Itinerary = NullALU; + bit hasIEEEFlag = 0; + bit hasZeroOpFlag = 0; +} //===--------------------------------------------------------------------===// // Multiclass Instruction formats //===--------------------------------------------------------------------===// -include "AMDILMultiClass.td" +// Multiclass that handles branch instructions +multiclass BranchConditional<SDNode Op> { + def _i32 : ILFormat<(outs), + (ins brtarget:$target, GPRI32:$src0), + "; i32 Pseudo branch instruction", + [(Op bb:$target, GPRI32:$src0)]>; + def _f32 : ILFormat<(outs), + (ins brtarget:$target, GPRF32:$src0), + "; f32 Pseudo branch instruction", + [(Op bb:$target, GPRF32:$src0)]>; +} + +// Only scalar types should generate flow control +multiclass BranchInstr<string name> { + def _i32 : ILFormat<(outs), (ins GPRI32:$src), + !strconcat(name, " $src"), []>; + def _f32 : ILFormat<(outs), (ins GPRF32:$src), + !strconcat(name, " $src"), []>; +} +// Only scalar types should generate flow control +multiclass BranchInstr2<string name> { + def _i32 : ILFormat<(outs), (ins GPRI32:$src0, GPRI32:$src1), + !strconcat(name, " $src0, $src1"), []>; + def _f32 : ILFormat<(outs), (ins GPRF32:$src0, GPRF32:$src1), + !strconcat(name, " $src0, $src1"), []>; +} //===--------------------------------------------------------------------===// // Intrinsics support @@ -105,4 +294,71 @@ include "AMDILIntrinsics.td" //===--------------------------------------------------------------------===// // Instructions support //===--------------------------------------------------------------------===// -include "AMDILInstructions.td" +//===---------------------------------------------------------------------===// +// Custom Inserter for Branches and returns, this eventually will be a +// seperate pass +//===---------------------------------------------------------------------===// +let isTerminator = 1 in { + def BRANCH : ILFormat<(outs), (ins brtarget:$target), + "; Pseudo unconditional branch instruction", + [(br bb:$target)]>; + defm BRANCH_COND : BranchConditional<IL_brcond>; +} +//===---------------------------------------------------------------------===// +// return instructions +//===---------------------------------------------------------------------===// +let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in { + def RETURN : ILFormat<(outs), (ins variable_ops), + "RETURN", [(IL_retflag)]>; +} + +//===---------------------------------------------------------------------===// +// Flow and Program control Instructions +//===---------------------------------------------------------------------===// +let isTerminator=1 in { + def SWITCH : ILFormat< (outs), (ins GPRI32:$src), + !strconcat("SWITCH", " $src"), []>; + def CASE : ILFormat< (outs), (ins GPRI32:$src), + !strconcat("CASE", " $src"), []>; + def BREAK : ILFormat< (outs), (ins), + "BREAK", []>; + def CONTINUE : ILFormat< (outs), (ins), + "CONTINUE", []>; + def DEFAULT : ILFormat< (outs), (ins), + "DEFAULT", []>; + def ELSE : ILFormat< (outs), (ins), + "ELSE", []>; + def ENDSWITCH : ILFormat< (outs), (ins), + "ENDSWITCH", []>; + def ENDMAIN : ILFormat< (outs), (ins), + "ENDMAIN", []>; + def END : ILFormat< (outs), (ins), + "END", []>; + def ENDFUNC : ILFormat< (outs), (ins), + "ENDFUNC", []>; + def ENDIF : ILFormat< (outs), (ins), + "ENDIF", []>; + def WHILELOOP : ILFormat< (outs), (ins), + "WHILE", []>; + def ENDLOOP : ILFormat< (outs), (ins), + "ENDLOOP", []>; + def FUNC : ILFormat< (outs), (ins), + "FUNC", []>; + def RETDYN : ILFormat< (outs), (ins), + "RET_DYN", []>; + // This opcode has custom swizzle pattern encoded in Swizzle Encoder + defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">; + // This opcode has custom swizzle pattern encoded in Swizzle Encoder + defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">; + // This opcode has custom swizzle pattern encoded in Swizzle Encoder + defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">; + // This opcode has custom swizzle pattern encoded in Swizzle Encoder + defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">; + // This opcode has custom swizzle pattern encoded in Swizzle Encoder + defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">; + // This opcode has custom swizzle pattern encoded in Swizzle Encoder + defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">; + defm IFC : BranchInstr2<"IFC">; + defm BREAKC : BranchInstr2<"BREAKC">; + defm CONTINUEC : BranchInstr2<"CONTINUEC">; +} diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td deleted file mode 100644 index 2eebb4a6266..00000000000 --- a/src/gallium/drivers/radeon/AMDILInstructions.td +++ /dev/null @@ -1,82 +0,0 @@ -//===-- AMDILInstructions.td - AMDIL Instruction definitions --------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// - -//===---------------------------------------------------------------------===// -// Custom Inserter for Branches and returns, this eventually will be a -// seperate pass -//===---------------------------------------------------------------------===// -let isTerminator = 1 in { - def BRANCH : ILFormat<IL_PSEUDO_INST, (outs), (ins brtarget:$target), - "; Pseudo unconditional branch instruction", - [(br bb:$target)]>; - defm BRANCH_COND : BranchConditional<IL_brcond>; -} -//===---------------------------------------------------------------------===// -// return instructions -//===---------------------------------------------------------------------===// -let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in { - def RETURN : ILFormat<IL_OP_RET,(outs), (ins variable_ops), - IL_OP_RET.Text, [(IL_retflag)]>; -} - -//===---------------------------------------------------------------------===// -// Flow and Program control Instructions -//===---------------------------------------------------------------------===// -let isTerminator=1 in { - def SWITCH : ILFormat<IL_OP_SWITCH, (outs), (ins GPRI32:$src), - !strconcat(IL_OP_SWITCH.Text, " $src"), []>; - def CASE : ILFormat<IL_OP_CASE, (outs), (ins GPRI32:$src), - !strconcat(IL_OP_CASE.Text, " $src"), []>; - def BREAK : ILFormat<IL_OP_BREAK, (outs), (ins), - IL_OP_BREAK.Text, []>; - def CONTINUE : ILFormat<IL_OP_CONTINUE, (outs), (ins), - IL_OP_CONTINUE.Text, []>; - def DEFAULT : ILFormat<IL_OP_DEFAULT, (outs), (ins), - IL_OP_DEFAULT.Text, []>; - def ELSE : ILFormat<IL_OP_ELSE, (outs), (ins), - IL_OP_ELSE.Text, []>; - def ENDSWITCH : ILFormat<IL_OP_ENDSWITCH, (outs), (ins), - IL_OP_ENDSWITCH.Text, []>; - def ENDMAIN : ILFormat<IL_OP_ENDMAIN, (outs), (ins), - IL_OP_ENDMAIN.Text, []>; - def END : ILFormat<IL_OP_END, (outs), (ins), - IL_OP_END.Text, []>; - def ENDFUNC : ILFormat<IL_OP_ENDFUNC, (outs), (ins), - IL_OP_ENDFUNC.Text, []>; - def ENDIF : ILFormat<IL_OP_ENDIF, (outs), (ins), - IL_OP_ENDIF.Text, []>; - def WHILELOOP : ILFormat<IL_OP_WHILE, (outs), (ins), - IL_OP_WHILE.Text, []>; - def ENDLOOP : ILFormat<IL_OP_ENDLOOP, (outs), (ins), - IL_OP_ENDLOOP.Text, []>; - def FUNC : ILFormat<IL_OP_FUNC, (outs), (ins), - IL_OP_FUNC.Text, []>; - def RETDYN : ILFormat<IL_OP_RET_DYN, (outs), (ins), - IL_OP_RET_DYN.Text, []>; - // This opcode has custom swizzle pattern encoded in Swizzle Encoder - defm IF_LOGICALNZ : BranchInstr<IL_OP_IF_LOGICALNZ>; - // This opcode has custom swizzle pattern encoded in Swizzle Encoder - defm IF_LOGICALZ : BranchInstr<IL_OP_IF_LOGICALZ>; - // This opcode has custom swizzle pattern encoded in Swizzle Encoder - defm BREAK_LOGICALNZ : BranchInstr<IL_OP_BREAK_LOGICALNZ>; - // This opcode has custom swizzle pattern encoded in Swizzle Encoder - defm BREAK_LOGICALZ : BranchInstr<IL_OP_BREAK_LOGICALZ>; - // This opcode has custom swizzle pattern encoded in Swizzle Encoder - defm CONTINUE_LOGICALNZ : BranchInstr<IL_OP_CONTINUE_LOGICALNZ>; - // This opcode has custom swizzle pattern encoded in Swizzle Encoder - defm CONTINUE_LOGICALZ : BranchInstr<IL_OP_CONTINUE_LOGICALZ>; - defm IFC : BranchInstr2<IL_OP_IFC>; - defm BREAKC : BranchInstr2<IL_OP_BREAKC>; - defm CONTINUEC : BranchInstr2<IL_OP_CONTINUEC>; -} -let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in { - def TRAP : ILFormat<IL_OP_NOP, (outs), (ins), - IL_OP_NOP.Text, [(trap)]>; -} - diff --git a/src/gallium/drivers/radeon/AMDILIntrinsics.td b/src/gallium/drivers/radeon/AMDILIntrinsics.td index ef361f4e6af..104b32e38ca 100644 --- a/src/gallium/drivers/radeon/AMDILIntrinsics.td +++ b/src/gallium/drivers/radeon/AMDILIntrinsics.td @@ -10,39 +10,62 @@ // This file defines all of the amdil-specific intrinsics // //===---------------------------------------------------------------===// - +//===--------------------------------------------------------------------===// +// Intrinsic classes +// Generic versions of the above classes but for Target specific intrinsics +// instead of SDNode patterns. +//===--------------------------------------------------------------------===// let TargetPrefix = "AMDIL", isTarget = 1 in { -//------------- Synchronization Functions - OpenCL 6.11.9 --------------------// - def int_AMDIL_fence : GCCBuiltin<"mem_fence">, - UnaryIntNoRetInt; - def int_AMDIL_fence_global : GCCBuiltin<"mem_fence_global">, - UnaryIntNoRetInt; - def int_AMDIL_fence_local : GCCBuiltin<"mem_fence_local">, - UnaryIntNoRetInt; - def int_AMDIL_fence_region : GCCBuiltin<"mem_fence_region">, - UnaryIntNoRetInt; - def int_AMDIL_fence_read_only : GCCBuiltin<"read_mem_fence">, - UnaryIntNoRetInt; - def int_AMDIL_fence_read_only_global : GCCBuiltin<"read_mem_fence_global">, - UnaryIntNoRetInt; - def int_AMDIL_fence_read_only_local : GCCBuiltin<"read_mem_fence_local">, - UnaryIntNoRetInt; - def int_AMDIL_fence_read_only_region : GCCBuiltin<"read_mem_fence_region">, - UnaryIntNoRetInt; - def int_AMDIL_fence_write_only : GCCBuiltin<"write_mem_fence">, - UnaryIntNoRetInt; - def int_AMDIL_fence_write_only_global : GCCBuiltin<"write_mem_fence_global">, - UnaryIntNoRetInt; - def int_AMDIL_fence_write_only_local : GCCBuiltin<"write_mem_fence_local">, - UnaryIntNoRetInt; - def int_AMDIL_fence_write_only_region : GCCBuiltin<"write_mem_fence_region">, - UnaryIntNoRetInt; - - def int_AMDIL_early_exit : GCCBuiltin<"__amdil_early_exit">, - UnaryIntNoRetInt; + class VoidIntLong : + Intrinsic<[llvm_i64_ty], [], []>; + class VoidIntInt : + Intrinsic<[llvm_i32_ty], [], []>; + class VoidIntBool : + Intrinsic<[llvm_i32_ty], [], []>; + class UnaryIntInt : + Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>; + class UnaryIntFloat : + Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; + class ConvertIntFTOI : + Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>; + class ConvertIntITOF : + Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty], [IntrNoMem]>; + class UnaryIntNoRetInt : + Intrinsic<[], [llvm_anyint_ty], []>; + class UnaryIntNoRetFloat : + Intrinsic<[], [llvm_anyfloat_ty], []>; + class BinaryIntInt : + Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; + class BinaryIntFloat : + Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; + class BinaryIntNoRetInt : + Intrinsic<[], [llvm_anyint_ty, LLVMMatchType<0>], []>; + class BinaryIntNoRetFloat : + Intrinsic<[], [llvm_anyfloat_ty, LLVMMatchType<0>], []>; + class TernaryIntInt : + Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, + LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; + class TernaryIntFloat : + Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, + LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; + class QuaternaryIntInt : + Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, + LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; + class UnaryAtomicInt : + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; + class BinaryAtomicInt : + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; + class TernaryAtomicInt : + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty]>; + class UnaryAtomicIntNoRet : + Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; + class BinaryAtomicIntNoRet : + Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; + class TernaryAtomicIntNoRet : + Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; +} - def int_AMDIL_cmov_logical : GCCBuiltin<"__amdil_cmov_logical">, - TernaryIntInt; +let TargetPrefix = "AMDIL", isTarget = 1 in { def int_AMDIL_fabs : GCCBuiltin<"__amdil_fabs">, UnaryIntFloat; def int_AMDIL_abs : GCCBuiltin<"__amdil_abs">, UnaryIntInt; @@ -221,485 +244,4 @@ let TargetPrefix = "AMDIL", isTarget = 1 in { def int_AMDIL_dp4 : GCCBuiltin<"__amdil_dp4">, Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; -//===---------------------- Image functions begin ------------------------===// - def int_AMDIL_image1d_write : GCCBuiltin<"__amdil_image1d_write">, - Intrinsic<[], [llvm_ptr_ty, llvm_v2i32_ty, llvm_v4i32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image1d_read_norm : GCCBuiltin<"__amdil_image1d_read_norm">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image1d_read_unnorm : GCCBuiltin<"__amdil_image1d_read_unnorm">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image1d_info0 : GCCBuiltin<"__amdil_image1d_info0">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; - - def int_AMDIL_image1d_info1 : GCCBuiltin<"__amdil_image1d_info1">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; - - def int_AMDIL_image1d_array_write : GCCBuiltin<"__amdil_image1d_array_write">, - Intrinsic<[], [llvm_ptr_ty, llvm_v2i32_ty, llvm_v4i32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image1d_array_read_norm : GCCBuiltin<"__amdil_image1d_array_read_norm">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image1d_array_read_unnorm : GCCBuiltin<"__amdil_image1d_array_read_unnorm">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image1d_array_info0 : GCCBuiltin<"__amdil_image1d_array_info0">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; - - def int_AMDIL_image1d_array_info1 : GCCBuiltin<"__amdil_image1d_array_info1">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; - - def int_AMDIL_image2d_write : GCCBuiltin<"__amdil_image2d_write">, - Intrinsic<[], [llvm_ptr_ty, llvm_v2i32_ty, llvm_v4i32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image2d_read_norm : GCCBuiltin<"__amdil_image2d_read_norm">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image2d_read_unnorm : GCCBuiltin<"__amdil_image2d_read_unnorm">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image2d_info0 : GCCBuiltin<"__amdil_image2d_info0">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; - - def int_AMDIL_image2d_info1 : GCCBuiltin<"__amdil_image2d_info1">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; - - def int_AMDIL_image2d_array_write : GCCBuiltin<"__amdil_image2d_array_write">, - Intrinsic<[], [llvm_ptr_ty, llvm_v2i32_ty, llvm_v4i32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image2d_array_read_norm : GCCBuiltin<"__amdil_image2d_array_read_norm">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image2d_array_read_unnorm : GCCBuiltin<"__amdil_image2d_array_read_unnorm">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image2d_array_info0 : GCCBuiltin<"__amdil_image2d_array_info0">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; - - def int_AMDIL_image2d_array_info1 : GCCBuiltin<"__amdil_image2d_array_info1">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; - - def int_AMDIL_image3d_write : GCCBuiltin<"__amdil_image3d_write">, - Intrinsic<[], [llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image3d_read_norm : GCCBuiltin<"__amdil_image3d_read_norm">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image3d_read_unnorm : GCCBuiltin<"__amdil_image3d_read_unnorm">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_image3d_info0 : GCCBuiltin<"__amdil_image3d_info0">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; - - def int_AMDIL_image3d_info1 : GCCBuiltin<"__amdil_image3d_info1">, - Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; - -//===---------------------- Image functions end --------------------------===// - - def int_AMDIL_append_alloc_i32 : GCCBuiltin<"__amdil_append_alloc">, - Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadWriteArgMem]>; - def int_AMDIL_append_consume_i32 : GCCBuiltin<"__amdil_append_consume">, - Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadWriteArgMem]>; - def int_AMDIL_append_alloc_i32_noret : GCCBuiltin<"__amdil_append_alloc_noret">, - Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadWriteArgMem]>; - def int_AMDIL_append_consume_i32_noret : GCCBuiltin<"__amdil_append_consume_noret">, - Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadWriteArgMem]>; - - def int_AMDIL_get_global_id : GCCBuiltin<"__amdil_get_global_id_int">, - Intrinsic<[llvm_v4i32_ty], [], []>; - def int_AMDIL_get_local_id : GCCBuiltin<"__amdil_get_local_id_int">, - Intrinsic<[llvm_v4i32_ty], [], []>; - def int_AMDIL_get_group_id : GCCBuiltin<"__amdil_get_group_id_int">, - Intrinsic<[llvm_v4i32_ty], [], []>; - def int_AMDIL_get_num_groups : GCCBuiltin<"__amdil_get_num_groups_int">, - Intrinsic<[llvm_v4i32_ty], [], []>; - def int_AMDIL_get_local_size : GCCBuiltin<"__amdil_get_local_size_int">, - Intrinsic<[llvm_v4i32_ty], [], []>; - def int_AMDIL_get_global_size : GCCBuiltin<"__amdil_get_global_size_int">, - Intrinsic<[llvm_v4i32_ty], [], []>; - def int_AMDIL_get_global_offset : GCCBuiltin<"__amdil_get_global_offset_int">, - Intrinsic<[llvm_v4i32_ty], [], []>; - def int_AMDIL_get_work_dim : GCCBuiltin<"get_work_dim">, - Intrinsic<[llvm_i32_ty], [], []>; - def int_AMDIL_get_printf_offset : GCCBuiltin<"__amdil_get_printf_offset">, - Intrinsic<[llvm_i32_ty], []>; - def int_AMDIL_get_printf_size : GCCBuiltin<"__amdil_get_printf_size">, - Intrinsic<[llvm_i32_ty], []>; - -/// Intrinsics for atomic instructions with no return value -/// Signed 32 bit integer atomics for global address space -def int_AMDIL_atomic_add_gi32_noret : GCCBuiltin<"__atomic_add_gi32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_sub_gi32_noret : GCCBuiltin<"__atomic_sub_gi32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_rsub_gi32_noret : GCCBuiltin<"__atomic_rsub_gi32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_xchg_gi32_noret : GCCBuiltin<"__atomic_xchg_gi32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_inc_gi32_noret : GCCBuiltin<"__atomic_inc_gi32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_dec_gi32_noret : GCCBuiltin<"__atomic_dec_gi32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_cmpxchg_gi32_noret : GCCBuiltin<"__atomic_cmpxchg_gi32_noret">, - TernaryAtomicIntNoRet; -def int_AMDIL_atomic_min_gi32_noret : GCCBuiltin<"__atomic_min_gi32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_max_gi32_noret : GCCBuiltin<"__atomic_max_gi32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_and_gi32_noret : GCCBuiltin<"__atomic_and_gi32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_or_gi32_noret : GCCBuiltin<"__atomic_or_gi32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_xor_gi32_noret : GCCBuiltin<"__atomic_xor_gi32_noret">, - BinaryAtomicIntNoRet; - - - -/// Unsigned 32 bit integer atomics for global address space -def int_AMDIL_atomic_add_gu32_noret : GCCBuiltin<"__atomic_add_gu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_sub_gu32_noret : GCCBuiltin<"__atomic_sub_gu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_rsub_gu32_noret : GCCBuiltin<"__atomic_rsub_gu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_xchg_gu32_noret : GCCBuiltin<"__atomic_xchg_gu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_inc_gu32_noret : GCCBuiltin<"__atomic_inc_gu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_dec_gu32_noret : GCCBuiltin<"__atomic_dec_gu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_cmpxchg_gu32_noret : GCCBuiltin<"__atomic_cmpxchg_gu32_noret">, - TernaryAtomicIntNoRet; -def int_AMDIL_atomic_min_gu32_noret : GCCBuiltin<"__atomic_min_gu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_max_gu32_noret : GCCBuiltin<"__atomic_max_gu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_and_gu32_noret : GCCBuiltin<"__atomic_and_gu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_or_gu32_noret : GCCBuiltin<"__atomic_or_gu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_xor_gu32_noret : GCCBuiltin<"__atomic_xor_gu32_noret">, - BinaryAtomicIntNoRet; - - -/// Intrinsics for atomic instructions with a return value -/// Signed 32 bit integer atomics for global address space -def int_AMDIL_atomic_add_gi32 : GCCBuiltin<"__atomic_add_gi32">, - BinaryAtomicInt; -def int_AMDIL_atomic_sub_gi32 : GCCBuiltin<"__atomic_sub_gi32">, - BinaryAtomicInt; -def int_AMDIL_atomic_rsub_gi32 : GCCBuiltin<"__atomic_rsub_gi32">, - BinaryAtomicInt; -def int_AMDIL_atomic_xchg_gi32 : GCCBuiltin<"__atomic_xchg_gi32">, - BinaryAtomicInt; -def int_AMDIL_atomic_inc_gi32 : GCCBuiltin<"__atomic_inc_gi32">, - BinaryAtomicInt; -def int_AMDIL_atomic_dec_gi32 : GCCBuiltin<"__atomic_dec_gi32">, - BinaryAtomicInt; -def int_AMDIL_atomic_cmpxchg_gi32 : GCCBuiltin<"__atomic_cmpxchg_gi32">, - TernaryAtomicInt; -def int_AMDIL_atomic_min_gi32 : GCCBuiltin<"__atomic_min_gi32">, - BinaryAtomicInt; -def int_AMDIL_atomic_max_gi32 : GCCBuiltin<"__atomic_max_gi32">, - BinaryAtomicInt; -def int_AMDIL_atomic_and_gi32 : GCCBuiltin<"__atomic_and_gi32">, - BinaryAtomicInt; -def int_AMDIL_atomic_or_gi32 : GCCBuiltin<"__atomic_or_gi32">, - BinaryAtomicInt; -def int_AMDIL_atomic_xor_gi32 : GCCBuiltin<"__atomic_xor_gi32">, - BinaryAtomicInt; - -/// 32 bit float atomics required by OpenCL -def int_AMDIL_atomic_xchg_gf32 : GCCBuiltin<"__atomic_xchg_gf32">, - BinaryAtomicInt; -def int_AMDIL_atomic_xchg_gf32_noret : GCCBuiltin<"__atomic_xchg_gf32_noret">, - BinaryAtomicIntNoRet; - -/// Unsigned 32 bit integer atomics for global address space -def int_AMDIL_atomic_add_gu32 : GCCBuiltin<"__atomic_add_gu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_sub_gu32 : GCCBuiltin<"__atomic_sub_gu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_rsub_gu32 : GCCBuiltin<"__atomic_rsub_gu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_xchg_gu32 : GCCBuiltin<"__atomic_xchg_gu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_inc_gu32 : GCCBuiltin<"__atomic_inc_gu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_dec_gu32 : GCCBuiltin<"__atomic_dec_gu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_cmpxchg_gu32 : GCCBuiltin<"__atomic_cmpxchg_gu32">, - TernaryAtomicInt; -def int_AMDIL_atomic_min_gu32 : GCCBuiltin<"__atomic_min_gu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_max_gu32 : GCCBuiltin<"__atomic_max_gu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_and_gu32 : GCCBuiltin<"__atomic_and_gu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_or_gu32 : GCCBuiltin<"__atomic_or_gu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_xor_gu32 : GCCBuiltin<"__atomic_xor_gu32">, - BinaryAtomicInt; - - -/// Intrinsics for atomic instructions with no return value -/// Signed 32 bit integer atomics for local address space -def int_AMDIL_atomic_add_li32_noret : GCCBuiltin<"__atomic_add_li32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_sub_li32_noret : GCCBuiltin<"__atomic_sub_li32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_rsub_li32_noret : GCCBuiltin<"__atomic_rsub_li32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_xchg_li32_noret : GCCBuiltin<"__atomic_xchg_li32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_inc_li32_noret : GCCBuiltin<"__atomic_inc_li32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_dec_li32_noret : GCCBuiltin<"__atomic_dec_li32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_cmpxchg_li32_noret : GCCBuiltin<"__atomic_cmpxchg_li32_noret">, - TernaryAtomicIntNoRet; -def int_AMDIL_atomic_min_li32_noret : GCCBuiltin<"__atomic_min_li32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_max_li32_noret : GCCBuiltin<"__atomic_max_li32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_and_li32_noret : GCCBuiltin<"__atomic_and_li32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_or_li32_noret : GCCBuiltin<"__atomic_or_li32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_mskor_li32_noret : GCCBuiltin<"__atomic_mskor_li32_noret">, - TernaryAtomicIntNoRet; -def int_AMDIL_atomic_xor_li32_noret : GCCBuiltin<"__atomic_xor_li32_noret">, - BinaryAtomicIntNoRet; - -/// Signed 32 bit integer atomics for region address space -def int_AMDIL_atomic_add_ri32_noret : GCCBuiltin<"__atomic_add_ri32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_sub_ri32_noret : GCCBuiltin<"__atomic_sub_ri32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_rsub_ri32_noret : GCCBuiltin<"__atomic_rsub_ri32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_xchg_ri32_noret : GCCBuiltin<"__atomic_xchg_ri32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_inc_ri32_noret : GCCBuiltin<"__atomic_inc_ri32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_dec_ri32_noret : GCCBuiltin<"__atomic_dec_ri32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_cmpxchg_ri32_noret : GCCBuiltin<"__atomic_cmpxchg_ri32_noret">, - TernaryAtomicIntNoRet; -def int_AMDIL_atomic_min_ri32_noret : GCCBuiltin<"__atomic_min_ri32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_max_ri32_noret : GCCBuiltin<"__atomic_max_ri32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_and_ri32_noret : GCCBuiltin<"__atomic_and_ri32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_or_ri32_noret : GCCBuiltin<"__atomic_or_ri32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_mskor_ri32_noret : GCCBuiltin<"__atomic_mskor_ri32_noret">, - TernaryAtomicIntNoRet; -def int_AMDIL_atomic_xor_ri32_noret : GCCBuiltin<"__atomic_xor_ri32_noret">, - BinaryAtomicIntNoRet; - - - -/// Unsigned 32 bit integer atomics for local address space -def int_AMDIL_atomic_add_lu32_noret : GCCBuiltin<"__atomic_add_lu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_sub_lu32_noret : GCCBuiltin<"__atomic_sub_lu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_rsub_lu32_noret : GCCBuiltin<"__atomic_rsub_lu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_xchg_lu32_noret : GCCBuiltin<"__atomic_xchg_lu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_inc_lu32_noret : GCCBuiltin<"__atomic_inc_lu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_dec_lu32_noret : GCCBuiltin<"__atomic_dec_lu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_cmpxchg_lu32_noret : GCCBuiltin<"__atomic_cmpxchg_lu32_noret">, - TernaryAtomicIntNoRet; -def int_AMDIL_atomic_min_lu32_noret : GCCBuiltin<"__atomic_min_lu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_max_lu32_noret : GCCBuiltin<"__atomic_max_lu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_and_lu32_noret : GCCBuiltin<"__atomic_and_lu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_or_lu32_noret : GCCBuiltin<"__atomic_or_lu32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_mskor_lu32_noret : GCCBuiltin<"__atomic_mskor_lu32_noret">, - TernaryAtomicIntNoRet; -def int_AMDIL_atomic_xor_lu32_noret : GCCBuiltin<"__atomic_xor_lu32_noret">, - BinaryAtomicIntNoRet; - -/// Unsigned 32 bit integer atomics for region address space -def int_AMDIL_atomic_add_ru32_noret : GCCBuiltin<"__atomic_add_ru32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_sub_ru32_noret : GCCBuiltin<"__atomic_sub_ru32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_rsub_ru32_noret : GCCBuiltin<"__atomic_rsub_ru32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_xchg_ru32_noret : GCCBuiltin<"__atomic_xchg_ru32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_inc_ru32_noret : GCCBuiltin<"__atomic_inc_ru32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_dec_ru32_noret : GCCBuiltin<"__atomic_dec_ru32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_cmpxchg_ru32_noret : GCCBuiltin<"__atomic_cmpxchg_ru32_noret">, - TernaryAtomicIntNoRet; -def int_AMDIL_atomic_min_ru32_noret : GCCBuiltin<"__atomic_min_ru32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_max_ru32_noret : GCCBuiltin<"__atomic_max_ru32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_and_ru32_noret : GCCBuiltin<"__atomic_and_ru32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_or_ru32_noret : GCCBuiltin<"__atomic_or_ru32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_mskor_ru32_noret : GCCBuiltin<"__atomic_mskor_ru32_noret">, - TernaryAtomicIntNoRet; -def int_AMDIL_atomic_xor_ru32_noret : GCCBuiltin<"__atomic_xor_ru32_noret">, - BinaryAtomicIntNoRet; - -def int_AMDIL_get_cycle_count : GCCBuiltin<"__amdil_get_cycle_count">, - VoidIntLong; - -def int_AMDIL_compute_unit_id : GCCBuiltin<"__amdil_compute_unit_id">, - VoidIntInt; - -def int_AMDIL_wavefront_id : GCCBuiltin<"__amdil_wavefront_id">, - VoidIntInt; - - -/// Intrinsics for atomic instructions with a return value -/// Signed 32 bit integer atomics for local address space -def int_AMDIL_atomic_add_li32 : GCCBuiltin<"__atomic_add_li32">, - BinaryAtomicInt; -def int_AMDIL_atomic_sub_li32 : GCCBuiltin<"__atomic_sub_li32">, - BinaryAtomicInt; -def int_AMDIL_atomic_rsub_li32 : GCCBuiltin<"__atomic_rsub_li32">, - BinaryAtomicInt; -def int_AMDIL_atomic_xchg_li32 : GCCBuiltin<"__atomic_xchg_li32">, - BinaryAtomicInt; -def int_AMDIL_atomic_inc_li32 : GCCBuiltin<"__atomic_inc_li32">, - BinaryAtomicInt; -def int_AMDIL_atomic_dec_li32 : GCCBuiltin<"__atomic_dec_li32">, - BinaryAtomicInt; -def int_AMDIL_atomic_cmpxchg_li32 : GCCBuiltin<"__atomic_cmpxchg_li32">, - TernaryAtomicInt; -def int_AMDIL_atomic_min_li32 : GCCBuiltin<"__atomic_min_li32">, - BinaryAtomicInt; -def int_AMDIL_atomic_max_li32 : GCCBuiltin<"__atomic_max_li32">, - BinaryAtomicInt; -def int_AMDIL_atomic_and_li32 : GCCBuiltin<"__atomic_and_li32">, - BinaryAtomicInt; -def int_AMDIL_atomic_or_li32 : GCCBuiltin<"__atomic_or_li32">, - BinaryAtomicInt; -def int_AMDIL_atomic_mskor_li32 : GCCBuiltin<"__atomic_mskor_li32">, - TernaryAtomicInt; -def int_AMDIL_atomic_xor_li32 : GCCBuiltin<"__atomic_xor_li32">, - BinaryAtomicInt; - -/// Signed 32 bit integer atomics for region address space -def int_AMDIL_atomic_add_ri32 : GCCBuiltin<"__atomic_add_ri32">, - BinaryAtomicInt; -def int_AMDIL_atomic_sub_ri32 : GCCBuiltin<"__atomic_sub_ri32">, - BinaryAtomicInt; -def int_AMDIL_atomic_rsub_ri32 : GCCBuiltin<"__atomic_rsub_ri32">, - BinaryAtomicInt; -def int_AMDIL_atomic_xchg_ri32 : GCCBuiltin<"__atomic_xchg_ri32">, - BinaryAtomicInt; -def int_AMDIL_atomic_inc_ri32 : GCCBuiltin<"__atomic_inc_ri32">, - BinaryAtomicInt; -def int_AMDIL_atomic_dec_ri32 : GCCBuiltin<"__atomic_dec_ri32">, - BinaryAtomicInt; -def int_AMDIL_atomic_cmpxchg_ri32 : GCCBuiltin<"__atomic_cmpxchg_ri32">, - TernaryAtomicInt; -def int_AMDIL_atomic_min_ri32 : GCCBuiltin<"__atomic_min_ri32">, - BinaryAtomicInt; -def int_AMDIL_atomic_max_ri32 : GCCBuiltin<"__atomic_max_ri32">, - BinaryAtomicInt; -def int_AMDIL_atomic_and_ri32 : GCCBuiltin<"__atomic_and_ri32">, - BinaryAtomicInt; -def int_AMDIL_atomic_or_ri32 : GCCBuiltin<"__atomic_or_ri32">, - BinaryAtomicInt; -def int_AMDIL_atomic_mskor_ri32 : GCCBuiltin<"__atomic_mskor_ri32">, - TernaryAtomicInt; -def int_AMDIL_atomic_xor_ri32 : GCCBuiltin<"__atomic_xor_ri32">, - BinaryAtomicInt; - -/// 32 bit float atomics required by OpenCL -def int_AMDIL_atomic_xchg_lf32 : GCCBuiltin<"__atomic_xchg_lf32">, - BinaryAtomicInt; -def int_AMDIL_atomic_xchg_lf32_noret : GCCBuiltin<"__atomic_xchg_lf32_noret">, - BinaryAtomicIntNoRet; -def int_AMDIL_atomic_xchg_rf32 : GCCBuiltin<"__atomic_xchg_rf32">, - BinaryAtomicInt; -def int_AMDIL_atomic_xchg_rf32_noret : GCCBuiltin<"__atomic_xchg_rf32_noret">, - BinaryAtomicIntNoRet; - -/// Unsigned 32 bit integer atomics for local address space -def int_AMDIL_atomic_add_lu32 : GCCBuiltin<"__atomic_add_lu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_sub_lu32 : GCCBuiltin<"__atomic_sub_lu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_rsub_lu32 : GCCBuiltin<"__atomic_rsub_lu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_xchg_lu32 : GCCBuiltin<"__atomic_xchg_lu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_inc_lu32 : GCCBuiltin<"__atomic_inc_lu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_dec_lu32 : GCCBuiltin<"__atomic_dec_lu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_cmpxchg_lu32 : GCCBuiltin<"__atomic_cmpxchg_lu32">, - TernaryAtomicInt; -def int_AMDIL_atomic_min_lu32 : GCCBuiltin<"__atomic_min_lu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_max_lu32 : GCCBuiltin<"__atomic_max_lu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_and_lu32 : GCCBuiltin<"__atomic_and_lu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_or_lu32 : GCCBuiltin<"__atomic_or_lu32">, - BinaryAtomicInt; -def int_AMDIL_atomic_mskor_lu32 : GCCBuiltin<"__atomic_mskor_lu32">, - TernaryAtomicInt; -def int_AMDIL_atomic_xor_lu32 : GCCBuiltin<"__atomic_xor_lu32">, - BinaryAtomicInt; - -/// Unsigned 32 bit integer atomics for region address space -def int_AMDIL_atomic_add_ru32 : GCCBuiltin<"__atomic_add_ru32">, - BinaryAtomicInt; -def int_AMDIL_atomic_sub_ru32 : GCCBuiltin<"__atomic_sub_ru32">, - BinaryAtomicInt; -def int_AMDIL_atomic_rsub_ru32 : GCCBuiltin<"__atomic_rsub_ru32">, - BinaryAtomicInt; -def int_AMDIL_atomic_xchg_ru32 : GCCBuiltin<"__atomic_xchg_ru32">, - BinaryAtomicInt; -def int_AMDIL_atomic_inc_ru32 : GCCBuiltin<"__atomic_inc_ru32">, - BinaryAtomicInt; -def int_AMDIL_atomic_dec_ru32 : GCCBuiltin<"__atomic_dec_ru32">, - BinaryAtomicInt; -def int_AMDIL_atomic_cmpxchg_ru32 : GCCBuiltin<"__atomic_cmpxchg_ru32">, - TernaryAtomicInt; -def int_AMDIL_atomic_min_ru32 : GCCBuiltin<"__atomic_min_ru32">, - BinaryAtomicInt; -def int_AMDIL_atomic_max_ru32 : GCCBuiltin<"__atomic_max_ru32">, - BinaryAtomicInt; -def int_AMDIL_atomic_and_ru32 : GCCBuiltin<"__atomic_and_ru32">, - BinaryAtomicInt; -def int_AMDIL_atomic_or_ru32 : GCCBuiltin<"__atomic_or_ru32">, - BinaryAtomicInt; -def int_AMDIL_atomic_mskor_ru32 : GCCBuiltin<"__atomic_mskor_ru32">, - TernaryAtomicInt; -def int_AMDIL_atomic_xor_ru32 : GCCBuiltin<"__atomic_xor_ru32">, - BinaryAtomicInt; - -/// Semaphore signal/wait/init -def int_AMDIL_semaphore_init : GCCBuiltin<"__amdil_semaphore_init">, - Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty]>; -def int_AMDIL_semaphore_wait : GCCBuiltin<"__amdil_semaphore_wait">, - Intrinsic<[], [llvm_ptr_ty]>; -def int_AMDIL_semaphore_signal : GCCBuiltin<"__amdil_semaphore_signal">, - Intrinsic<[], [llvm_ptr_ty]>; -def int_AMDIL_semaphore_size : GCCBuiltin<"__amdil_max_semaphore_size">, - Intrinsic<[llvm_i32_ty], []>; } diff --git a/src/gallium/drivers/radeon/AMDILMultiClass.td b/src/gallium/drivers/radeon/AMDILMultiClass.td deleted file mode 100644 index 12e92f571e6..00000000000 --- a/src/gallium/drivers/radeon/AMDILMultiClass.td +++ /dev/null @@ -1,95 +0,0 @@ -//===-- AMDILMultiClass.td - AMDIL Multiclass defs ---*- tablegen -*-------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// -// Multiclass that handles branch instructions -multiclass BranchConditional<SDNode Op> { - def _i32 : ILFormat<IL_OP_IFC, (outs), - (ins brtarget:$target, GPRI32:$src0), - "; i32 Pseudo branch instruction", - [(Op bb:$target, GPRI32:$src0)]>; - def _f32 : ILFormat<IL_OP_IFC, (outs), - (ins brtarget:$target, GPRF32:$src0), - "; f32 Pseudo branch instruction", - [(Op bb:$target, GPRF32:$src0)]>; -} - -// Multiclass that handles memory store operations -multiclass GTRUNCSTORE<string asm> { - def _i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEMI32:$ptr), - !strconcat(asm, " $val $ptr"), - [(global_i8trunc_store GPRI32:$val, ADDR:$ptr)]>; - def _i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEMI32:$ptr), - !strconcat(asm, " $val $ptr"), - [(global_i16trunc_store GPRI32:$val, ADDR:$ptr)]>; -} - -// Multiclass that handles memory store operations -multiclass LTRUNCSTORE<string asm> { - def _i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEMI32:$ptr), - !strconcat(asm, " $val $ptr"), - [(local_i8trunc_store GPRI32:$val, ADDR:$ptr)]>; - def _i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEMI32:$ptr), - !strconcat(asm, " $val $ptr"), - [(local_i16trunc_store GPRI32:$val, ADDR:$ptr)]>; -} - -// Multiclass that handles memory store operations -multiclass PTRUNCSTORE<string asm> { - def _i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEMI32:$ptr), - !strconcat(asm, " $val $ptr"), - [(private_i8trunc_store GPRI32:$val, ADDR:$ptr)]>; - def _i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEMI32:$ptr), - !strconcat(asm, " $val $ptr"), - [(private_i16trunc_store GPRI32:$val, ADDR:$ptr)]>; -} - -// Multiclass that handles memory store operations -multiclass RTRUNCSTORE<string asm> { - def _i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEMI32:$ptr), - !strconcat(asm, " $val $ptr"), - [(region_i8trunc_store GPRI32:$val, ADDR:$ptr)]>; - def _i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEMI32:$ptr), - !strconcat(asm, " $val $ptr"), - [(region_i16trunc_store GPRI32:$val, ADDR:$ptr)]>; -} - - -// Multiclass that handles memory store operations -multiclass STORE<string asm, PatFrag OpNode> { - def _i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEMI32:$ptr), - !strconcat(asm, " $val $ptr"), - [(OpNode GPRI32:$val, ADDR:$ptr)]>; - def _f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF32:$val, MEMI32:$ptr), - !strconcat(asm, " $val $ptr"), - [(OpNode GPRF32:$val, ADDR:$ptr)]>; -} - -// Multiclass that handles load operations -multiclass LOAD<string asm, PatFrag OpNode> { - def _i32 : OneInOneOut<IL_OP_MOV, (outs GPRI32:$dst), (ins MEMI32:$ptr), - !strconcat(asm, " $dst $ptr"), - [(set GPRI32:$dst, (OpNode ADDR:$ptr))]>; - def _f32 : OneInOneOut<IL_OP_MOV, (outs GPRF32:$dst), (ins MEMI32:$ptr), - !strconcat(asm, " $dst $ptr"), - [(set GPRF32:$dst, (OpNode ADDR:$ptr))]>; -} - -// Only scalar types should generate flow control -multiclass BranchInstr<ILOpCode opc> { - def _i32 : UnaryOpNoRet<opc, (outs), (ins GPRI32:$src), - !strconcat(opc.Text, " $src"), []>; - def _f32 : UnaryOpNoRet<opc, (outs), (ins GPRF32:$src), - !strconcat(opc.Text, " $src"), []>; -} -// Only scalar types should generate flow control -multiclass BranchInstr2<ILOpCode opc> { - def _i32 : BinaryOpNoRet<opc, (outs), (ins GPRI32:$src0, GPRI32:$src1), - !strconcat(opc.Text, " $src0, $src1"), []>; - def _f32 : BinaryOpNoRet<opc, (outs), (ins GPRF32:$src0, GPRF32:$src1), - !strconcat(opc.Text, " $src0, $src1"), []>; -} diff --git a/src/gallium/drivers/radeon/AMDILNodes.td b/src/gallium/drivers/radeon/AMDILNodes.td deleted file mode 100644 index 699fdadf8b4..00000000000 --- a/src/gallium/drivers/radeon/AMDILNodes.td +++ /dev/null @@ -1,47 +0,0 @@ -//===- AMDILNodes.td - AMD IL nodes ------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Flow Control DAG Nodes -//===----------------------------------------------------------------------===// -def IL_brcond : SDNode<"AMDILISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>; - -//===----------------------------------------------------------------------===// -// Comparison DAG Nodes -//===----------------------------------------------------------------------===// -def IL_cmp : SDNode<"AMDILISD::CMP", SDTIL_Cmp>; - -//===----------------------------------------------------------------------===// -// Call/Return DAG Nodes -//===----------------------------------------------------------------------===// -def IL_call : SDNode<"AMDILISD::CALL", SDTIL_Call, - [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; - -def IL_retflag : SDNode<"AMDILISD::RET_FLAG", SDTNone, - [SDNPHasChain, SDNPOptInGlue]>; - -//===--------------------------------------------------------------------===// -// Instructions -//===--------------------------------------------------------------------===// -// Floating point math functions -def IL_cmov_logical : SDNode<"AMDILISD::CMOVLOG", SDTIL_GenTernaryOp>; -def IL_div_inf : SDNode<"AMDILISD::DIV_INF", SDTIL_GenBinaryOp>; -def IL_mad : SDNode<"AMDILISD::MAD", SDTIL_GenTernaryOp>; - -//===----------------------------------------------------------------------===// -// Integer functions -//===----------------------------------------------------------------------===// -def IL_umul : SDNode<"AMDILISD::UMUL" , SDTIntBinOp, - [SDNPCommutative, SDNPAssociative]>; - -//===----------------------------------------------------------------------===// -// Vector functions -//===----------------------------------------------------------------------===// -def IL_vbuild : SDNode<"AMDILISD::VBUILD", SDTIL_GenVecBuild, - []>; diff --git a/src/gallium/drivers/radeon/AMDILOperands.td b/src/gallium/drivers/radeon/AMDILOperands.td deleted file mode 100644 index 1014f95bb93..00000000000 --- a/src/gallium/drivers/radeon/AMDILOperands.td +++ /dev/null @@ -1,32 +0,0 @@ -//===- AMDILOperands.td - AMD IL Operands ------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// Custom memory operand -//===----------------------------------------------------------------------===// - -def MEMI32 : Operand<i32> { - let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops GPRI32, GPRI32); -} - -// Call target types -def calltarget : Operand<i32>; -def brtarget : Operand<OtherVT>; - -// def v2i8imm : Operand<v2i8>; -// def v4i8imm : Operand<v4i8>; -// def v2i16imm : Operand<v2i16>; -// def v4i16imm : Operand<v4i16>; -// def v2i32imm : Operand<v2i32>; -// def v4i32imm : Operand<v4i32>; -// def v2i64imm : Operand<v2i64>; -// def v2f32imm : Operand<v2f32>; -// def v4f32imm : Operand<v4f32>; -// def v2f64imm : Operand<v2f64>; - diff --git a/src/gallium/drivers/radeon/AMDILPatterns.td b/src/gallium/drivers/radeon/AMDILPatterns.td deleted file mode 100644 index aa59bcb5b4e..00000000000 --- a/src/gallium/drivers/radeon/AMDILPatterns.td +++ /dev/null @@ -1,504 +0,0 @@ -//===- AMDILPatterns.td - AMDIL Target Patterns------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Store pattern fragments -//===----------------------------------------------------------------------===// -def truncstorei64 : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i64; -}]>; -def truncstorev2i8 : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v2i8; -}]>; -def truncstorev2i16 : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v2i16; -}]>; -def truncstorev2i32 : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v2i32; -}]>; -def truncstorev2i64 : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v2i64; -}]>; -def truncstorev2f32 : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v2f32; -}]>; -def truncstorev2f64 : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v2f64; -}]>; -def truncstorev4i8 : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v4i8; -}]>; -def truncstorev4i16 : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v4i16; -}]>; -def truncstorev4i32 : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v4i32; -}]>; -def truncstorev4f32 : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v4f32; -}]>; - -def global_store : PatFrag<(ops node:$val, node:$ptr), - (store node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_store : PatFrag<(ops node:$val, node:$ptr), - (store node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_store : PatFrag<(ops node:$val, node:$ptr), - (store node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_store : PatFrag<(ops node:$val, node:$ptr), - (store node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_i8trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei8 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_i16trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei16 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_i32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei32 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_i64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei64 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_f32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstoref32 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_f64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstoref64 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_v2i8trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i8 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_v2i16trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i16 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_v2i32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i32 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_v2i64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i64 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_v2f32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2f32 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_v2f64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2f64 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_v4i8trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4i8 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_v4i16trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4i16 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_v4i32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4i32 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def global_v4f32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4f32 node:$val, node:$ptr), [{ - return isGlobalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_i8trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei8 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_i16trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei16 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_i32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei32 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_i64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei64 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_f32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstoref32 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_f64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstoref64 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_v2i8trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i8 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_v2i16trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i16 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_v2i32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i32 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_v2i64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i64 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_v2f32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2f32 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_v2f64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2f64 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_v4i8trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4i8 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_v4i16trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4i16 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_v4i32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4i32 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; -def private_v4f32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4f32 node:$val, node:$ptr), [{ - return isPrivateStore(dyn_cast<StoreSDNode>(N)); -}]>; - -def local_trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_i8trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei8 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_i16trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei16 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_i32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei32 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_i64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei64 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_f32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstoref32 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_f64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstoref64 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_v2i8trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i8 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_v2i16trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i16 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_v2i32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i32 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_v2i64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i64 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_v2f32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2f32 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_v2f64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2f64 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_v4i8trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4i8 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_v4i16trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4i16 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_v4i32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4i32 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; -def local_v4f32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4f32 node:$val, node:$ptr), [{ - return isLocalStore(dyn_cast<StoreSDNode>(N)); -}]>; - -def region_trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstore node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_i8trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei8 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_i16trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei16 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_i32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei32 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_i64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorei64 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_f32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstoref32 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_f64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstoref64 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_v2i8trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i8 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_v2i16trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i16 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_v2i32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i32 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_v2i64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2i64 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_v2f32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2f32 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_v2f64trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev2f64 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_v4i8trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4i8 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_v4i16trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4i16 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_v4i32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4i32 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; -def region_v4f32trunc_store : PatFrag<(ops node:$val, node:$ptr), - (truncstorev4f32 node:$val, node:$ptr), [{ - return isRegionStore(dyn_cast<StoreSDNode>(N)); -}]>; - -//===----------------------------------------------------------------------===// -// Load pattern fragments -//===----------------------------------------------------------------------===// -// Global address space loads -def global_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - return isGlobalLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def global_sext_load : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ - return isGlobalLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def global_aext_load : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ - return isGlobalLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def global_zext_load : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ - return isGlobalLoad(dyn_cast<LoadSDNode>(N)); -}]>; -// Private address space loads -def private_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - return isPrivateLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def private_sext_load : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ - return isPrivateLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def private_aext_load : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ - return isPrivateLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def private_zext_load : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ - return isPrivateLoad(dyn_cast<LoadSDNode>(N)); -}]>; -// Local address space loads -def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - return isLocalLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def local_sext_load : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ - return isLocalLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def local_aext_load : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ - return isLocalLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def local_zext_load : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ - return isLocalLoad(dyn_cast<LoadSDNode>(N)); -}]>; -// Region address space loads -def region_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - return isRegionLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def region_sext_load : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ - return isRegionLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def region_aext_load : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ - return isRegionLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def region_zext_load : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ - return isRegionLoad(dyn_cast<LoadSDNode>(N)); -}]>; -// Constant address space loads -def constant_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); -}]>; -def constant_sext_load : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ - return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); -}]>; -def constant_aext_load : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ - return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); -}]>; -def constant_zext_load : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ - return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); -}]>; -// Constant pool loads -def cp_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - return isCPLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def cp_sext_load : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ - return isCPLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def cp_zext_load : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ - return isCPLoad(dyn_cast<LoadSDNode>(N)); -}]>; -def cp_aext_load : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ - return isCPLoad(dyn_cast<LoadSDNode>(N)); -}]>; - -//===----------------------------------------------------------------------===// -// Complex addressing mode patterns -//===----------------------------------------------------------------------===// -def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>; -def ADDRF : ComplexPattern<i32, 2, "SelectADDR", [frameindex], []>; -def ADDR64 : ComplexPattern<i64, 2, "SelectADDR64", [], []>; -def ADDR64F : ComplexPattern<i64, 2, "SelectADDR64", [frameindex], []>; - - -//===----------------------------------------------------------------------===// -// Conditional Instruction Pattern Leafs -//===----------------------------------------------------------------------===// -class IL_CC_Op<int N> : PatLeaf<(i32 N)>; -def IL_CC_D_EQ : IL_CC_Op<0>; -def IL_CC_D_GE : IL_CC_Op<1>; -def IL_CC_D_LT : IL_CC_Op<2>; -def IL_CC_D_NE : IL_CC_Op<3>; -def IL_CC_F_EQ : IL_CC_Op<4>; -def IL_CC_F_GE : IL_CC_Op<5>; -def IL_CC_F_LT : IL_CC_Op<6>; -def IL_CC_F_NE : IL_CC_Op<7>; -def IL_CC_I_EQ : IL_CC_Op<8>; -def IL_CC_I_GE : IL_CC_Op<9>; -def IL_CC_I_LT : IL_CC_Op<10>; -def IL_CC_I_NE : IL_CC_Op<11>; -def IL_CC_U_GE : IL_CC_Op<12>; -def IL_CC_U_LT : IL_CC_Op<13>; -// Pseudo IL comparison instructions that aren't natively supported -def IL_CC_F_GT : IL_CC_Op<14>; -def IL_CC_U_GT : IL_CC_Op<15>; -def IL_CC_I_GT : IL_CC_Op<16>; -def IL_CC_D_GT : IL_CC_Op<17>; -def IL_CC_F_LE : IL_CC_Op<18>; -def IL_CC_U_LE : IL_CC_Op<19>; -def IL_CC_I_LE : IL_CC_Op<20>; -def IL_CC_D_LE : IL_CC_Op<21>; -def IL_CC_F_UNE : IL_CC_Op<22>; -def IL_CC_F_UEQ : IL_CC_Op<23>; -def IL_CC_F_ULT : IL_CC_Op<24>; -def IL_CC_F_UGT : IL_CC_Op<25>; -def IL_CC_F_ULE : IL_CC_Op<26>; -def IL_CC_F_UGE : IL_CC_Op<27>; -def IL_CC_F_ONE : IL_CC_Op<28>; -def IL_CC_F_OEQ : IL_CC_Op<29>; -def IL_CC_F_OLT : IL_CC_Op<30>; -def IL_CC_F_OGT : IL_CC_Op<31>; -def IL_CC_F_OLE : IL_CC_Op<32>; -def IL_CC_F_OGE : IL_CC_Op<33>; -def IL_CC_D_UNE : IL_CC_Op<34>; -def IL_CC_D_UEQ : IL_CC_Op<35>; -def IL_CC_D_ULT : IL_CC_Op<36>; -def IL_CC_D_UGT : IL_CC_Op<37>; -def IL_CC_D_ULE : IL_CC_Op<38>; -def IL_CC_D_UGE : IL_CC_Op<39>; -def IL_CC_D_ONE : IL_CC_Op<30>; -def IL_CC_D_OEQ : IL_CC_Op<41>; -def IL_CC_D_OLT : IL_CC_Op<42>; -def IL_CC_D_OGT : IL_CC_Op<43>; -def IL_CC_D_OLE : IL_CC_Op<44>; -def IL_CC_D_OGE : IL_CC_Op<45>; -def IL_CC_U_EQ : IL_CC_Op<46>; -def IL_CC_U_NE : IL_CC_Op<47>; -def IL_CC_F_O : IL_CC_Op<48>; -def IL_CC_D_O : IL_CC_Op<49>; -def IL_CC_F_UO : IL_CC_Op<50>; -def IL_CC_D_UO : IL_CC_Op<51>; -def IL_CC_L_LE : IL_CC_Op<52>; -def IL_CC_L_GE : IL_CC_Op<53>; -def IL_CC_L_EQ : IL_CC_Op<54>; -def IL_CC_L_NE : IL_CC_Op<55>; -def IL_CC_L_LT : IL_CC_Op<56>; -def IL_CC_L_GT : IL_CC_Op<57>; -def IL_CC_UL_LE : IL_CC_Op<58>; -def IL_CC_UL_GE : IL_CC_Op<59>; -def IL_CC_UL_EQ : IL_CC_Op<60>; -def IL_CC_UL_NE : IL_CC_Op<61>; -def IL_CC_UL_LT : IL_CC_Op<62>; -def IL_CC_UL_GT : IL_CC_Op<63>; diff --git a/src/gallium/drivers/radeon/AMDILProfiles.td b/src/gallium/drivers/radeon/AMDILProfiles.td deleted file mode 100644 index 60435a82b66..00000000000 --- a/src/gallium/drivers/radeon/AMDILProfiles.td +++ /dev/null @@ -1,174 +0,0 @@ -//===- AMDILProfiles.td - AMD IL Profiles ------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// -// These are used for custom selection dag type profiles - -//===----------------------------------------------------------------------===// -// Custom Selection DAG Type Profiles -//===----------------------------------------------------------------------===// -// SDTCisDP - The specified operand has double type -// Tablegen needs to be hacked to get this constraint to work -//class SDTCisDP<int OpNum> : SDTypeConstraint<OpNum>; - -//===----------------------------------------------------------------------===// -// Generic Profile Types -//===----------------------------------------------------------------------===// - -def SDTIL_GenUnaryOp : SDTypeProfile<1, 1, [ - SDTCisSameAs<0, 1> - ]>; -def SDTIL_GenBinaryOp : SDTypeProfile<1, 2, [ - SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> - ]>; -def SDTIL_GenTernaryOp : SDTypeProfile<1, 3, [ - SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<2, 3> - ]>; -def SDTIL_GenCMovLog : SDTypeProfile<1, 3, [ - SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisInt<1> - ]>; -def SDTIL_GenVecBuild : SDTypeProfile<1, 1, [ - SDTCisEltOfVec<1, 0> - ]>; - -def SDTIL_GenVecExtract : SDTypeProfile<1, 2, [ - SDTCisEltOfVec<0, 1>, SDTCisVT<2, i32> - ]>; - -def SDTIL_GenVecInsert : SDTypeProfile<1, 4, [ - SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, - SDTCisVT<3, i32>, SDTCisVT<4, i32> - ]>; - -def SDTIL_GenVecShuffle : SDTypeProfile <1, 2, [ - SDTCisSameAs<0, 1>, SDTCisVT<2, i32> - ]>; - -def SDTIL_GenVecConcat : SDTypeProfile <1, 2, [ - SDTCisSameAs<1, 2> - ]>; -//===----------------------------------------------------------------------===// -// Conversion Profile Types -//===----------------------------------------------------------------------===// -def SDTIL_DPToFPOp : SDTypeProfile<1, 1, [ - SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> - ]>; // d2f - -def SDTIL_AnyToInt : SDTypeProfile<1, 1, [ - SDTCisInt<0> - ]>; -def SDTIL_IntToAny : SDTypeProfile<1, 1, [ - SDTCisInt<1> - ]>; -def SDTIL_GenBitConv : SDTypeProfile<1, 1, []>; -//===----------------------------------------------------------------------===// -// Scalar Profile Types -//===----------------------------------------------------------------------===// - -// Add instruction pattern to handle offsets of memory operationns -def SDTIL_AddAddrri: SDTypeProfile<1, 2, [ - SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisSameAs<0, 2> - ]>; -def SDTIL_AddAddrir : SDTypeProfile<1, 2, [ - SDTCisInt<0>, SDTCisPtrTy<2>, SDTCisSameAs<0, 1> - ]>; - -def SDTIL_LCreate : SDTypeProfile<1, 2, [ - SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2> - ]>; -def SDTIL_LCreate2 : SDTypeProfile<1, 2, [ - SDTCisVT<0, v2i64>, SDTCisVT<1, v2i32>, SDTCisSameAs<1, 2> - ]>; -def SDTIL_LComp : SDTypeProfile<1, 1, [ - SDTCisVT<0, i32>, SDTCisVT<1, i64> - ]>; -def SDTIL_LComp2 : SDTypeProfile<1, 1, [ - SDTCisVT<0, v2i32>, SDTCisVT<1, v2i64> - ]>; -def SDTIL_DCreate : SDTypeProfile<1, 2, [ - SDTCisVT<0, f64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2> - ]>; -def SDTIL_DComp : SDTypeProfile<1, 1, [ - SDTCisVT<0, i32>, SDTCisVT<1, f64> - ]>; -def SDTIL_DCreate2 : SDTypeProfile<1, 2, [ - SDTCisVT<0, v2f64>, SDTCisVT<1, v2i32>, SDTCisSameAs<1, 2> - ]>; -def SDTIL_DComp2 : SDTypeProfile<1, 1, [ - SDTCisVT<0, v2i32>, SDTCisVT<1, v2f64> - ]>; -//===----------------------------------------------------------------------===// -// Flow Control Profile Types -//===----------------------------------------------------------------------===// -// Profile for Normal Call -def SDTIL_Call : SDTypeProfile<0, 1, [ - SDTCisVT<0, i32> - ]>; -// Branch instruction where second and third are basic blocks -def SDTIL_BRCond : SDTypeProfile<0, 2, [ - SDTCisVT<0, OtherVT> - ]>; -// Comparison instruction -def SDTIL_Cmp : SDTypeProfile<1, 3, [ - SDTCisSameAs<0, 2>, SDTCisSameAs<2,3>, SDTCisVT<1, i32> - ]>; - - -//===----------------------------------------------------------------------===// -// Call Sequence Profiles -//===----------------------------------------------------------------------===// -def SDTIL_CallSeqStart : SDCallSeqStart< [ - SDTCisVT<0, i32> - ]>; -def SDTIL_CallSeqEnd : SDCallSeqEnd< [ - SDTCisVT<0, i32>, SDTCisVT<1, i32> - ]>; - -//===----------------------------------------------------------------------===// -// Image Operation Profiles -//===----------------------------------------------------------------------===// -def SDTIL_ImageRead : SDTypeProfile<1, 3, - [SDTCisVT<0, v4i32>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVT<3, v4f32>]>; -def SDTIL_ImageWrite : SDTypeProfile<0, 3, - [SDTCisPtrTy<0>, SDTCisVT<1, v2i32>, SDTCisVT<2, v4i32>]>; -def SDTIL_ImageWrite3D : SDTypeProfile<0, 3, - [SDTCisPtrTy<0>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>]>; -def SDTIL_ImageInfo : SDTypeProfile<1, 1, - [SDTCisVT<0, v4i32>, SDTCisPtrTy<1>]>; -//===----------------------------------------------------------------------===// -// Atomic Operation Profiles -//===----------------------------------------------------------------------===// -def SDTIL_UniAtomNoRet : SDTypeProfile<0, 2, [ - SDTCisPtrTy<0>, SDTCisVT<1, i32> - ]>; -def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [ - SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32> - ]>; -def SDTIL_TriAtomNoRet : SDTypeProfile<0, 4, [ - SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32> - ]>; -def SDTIL_UniAtom : SDTypeProfile<1, 2, [ - SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, i32> - ]>; -def SDTIL_BinAtom : SDTypeProfile<1, 3, [ - SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVT<3, i32> - ]>; -def SDTIL_TriAtom : SDTypeProfile<1, 4, [ - SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, - SDTCisVT<3, i32>, SDTCisVT<4, i32> - ]>; - -def SDTIL_BinAtomFloat : SDTypeProfile<1, 3, [ - SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, f32>, SDTCisVT<3, f32> - ]>; -def SDTIL_BinAtomNoRetFloat : SDTypeProfile<0, 3, [ - SDTCisPtrTy<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32> - ]>; - -def SDTIL_Append : SDTypeProfile<1, 1, [ - SDTCisVT<0, i32>, SDTCisPtrTy<1> - ]>; diff --git a/src/gallium/drivers/radeon/AMDILTokenDesc.td b/src/gallium/drivers/radeon/AMDILTokenDesc.td deleted file mode 100644 index 2dafb2cd559..00000000000 --- a/src/gallium/drivers/radeon/AMDILTokenDesc.td +++ /dev/null @@ -1,120 +0,0 @@ -//===-- AMDILTokenDesc.td - AMDIL Token Definitions --*- tablegen -*-----===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===--------------------------------------------------------------------===// - -include "AMDILEnumeratedTypes.td" - -// Each token is 32 bits as specified in section 2.1 of the IL spec -class ILToken <bits<32> n> { - field bits<32> _bits = n; -} - -// Section 2.2.1 - IL Language Token -class ILLang<bits<8> client_type> : ILToken<0> { - let _bits{0-7} = client_type; -} - -// Section 2.2.2 - IL Version Token -class ILVersion<bits<8> minor_version, bits<8> major_version, ILShader shader_type> : ILToken<0> { - let _bits{0-7} = minor_version; - let _bits{8-15} = major_version; - let _bits{16-23} = shader_type.Value; -} - -// Section 2.2.3 - IL Opcode Token -class ILOpcode<ILOpCode opcode, bits<14> control, bit sec_mod_pre, bit pri_mod_pre> : ILToken<0> { - let _bits{0-15} = opcode.Value; - let _bits{16-29} = control; - let _bits{30} = sec_mod_pre; - let _bits{31} = pri_mod_pre; -} - -// Section 2.2.4 - IL Destination Token -class ILDst<AMDILReg register_num, ILRegType register_type, bit mod_pre, bits<2> relative_address, bit dimension, bit immediate_pre, bit extended> : ILToken<0> { - let _bits{0-15} = register_num.Value; - let _bits{16-21} = register_type.Value; - let _bits{22} = mod_pre; - let _bits{23-24} = relative_address; - let _bits{25} = dimension; - let _bits{26} = immediate_pre; - let _bits{31} = extended; -} - -// Section 2.2.5 - IL Destination Modifier Token -class ILDstMod<ILModDstComp x, ILModDstComp y, ILModDstComp z, ILModDstComp w, bit clamp, ILShiftScale shift_scale> : ILToken<0> { - let _bits{0-1} = x.Value; - let _bits{2-3} = y.Value; - let _bits{4-5} = z.Value; - let _bits{6-7} = w.Value; - let _bits{8} = clamp; - //let _bits{9-12} = shift_scale; -} - -// Section 2.2.6 - IL Source Token -class ILSrc<AMDILReg register_num, ILRegType register_type, bit mod_pre, bits<2> relative_address, bit dimension, bit immediate_pre, bit extended> : ILToken<0> { - let _bits{0-15} = register_num.Value; - let _bits{16-21} = register_type.Value; - let _bits{22} = mod_pre; - let _bits{23-24} = relative_address; - let _bits{25} = dimension; - let _bits{26} = immediate_pre; - let _bits{31} = extended; -} - -// Section 2.2.7 - IL Source Modifier Token -class ILSrcMod<ILComponentSelect swizzle_x, bit negate_x, ILComponentSelect swizzle_y, bit negate_y, - ILComponentSelect swizzle_z, bit negate_z, ILComponentSelect swizzle_w, bit negate_w, - bit invert, bit bias, bit x2, bit sign, bit abs, ILDivComp divComp, - bits<8> clamp> : ILToken<0> { - let _bits{0-2} = swizzle_x.Value; - let _bits{3} = negate_x; - let _bits{4-6} = swizzle_y.Value; - let _bits{7} = negate_y; - let _bits{8-10} = swizzle_z.Value; - let _bits{11} = negate_z; - let _bits{12-14} = swizzle_w.Value; - let _bits{15} = negate_w; - let _bits{16} = invert; - let _bits{17} = bias; - let _bits{18} = x2; - let _bits{19} = sign; - let _bits{20} = abs; - let _bits{21-23} = divComp.Value; - let _bits{24-31} = clamp; -} - -// Section 2.2.8 - IL Relative Address Token -class ILRelAddr<AMDILReg address_register, bit loop_relative, ILAddressing component> : ILToken<0> { - let _bits{0-15} = address_register.Value; - let _bits{16} = loop_relative; - let _bits{17-19} = component.Value; -} - -// IL Literal Token -class ILLiteral<bits<32> val> : ILToken<0> { - let _bits = val; -} - -// All tokens required for a destination register -class ILDstReg<ILDst Reg, ILDstMod Mod, ILRelAddr Rel, ILSrc Reg_Rel, ILSrcMod Reg_Rel_Mod> { - ILDst reg = Reg; - ILDstMod mod = Mod; - ILRelAddr rel = Rel; - ILSrc reg_rel = Reg_Rel; - ILSrcMod reg_rel_mod = Reg_Rel_Mod; -} - -// All tokens required for a source register -class ILSrcReg<ILSrc Reg, ILSrcMod Mod, ILRelAddr Rel, ILSrc Reg_Rel, ILSrcMod Reg_Rel_Mod> { - ILSrc reg = Reg; - ILSrcMod mod = Mod; - ILRelAddr rel = Rel; - ILSrc reg_rel = Reg_Rel; - ILSrcMod reg_rel_mod = Reg_Rel_Mod; -} - |