diff options
| author | Marek Olšák <[email protected]> | 2016-10-21 13:31:40 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-03-30 14:44:33 +0200 |
| commit | e572835fea5ec7ae3b029a5e438889d1da99985a (patch) | |
| tree | 85fa193337daaf427357b6e9e5c7096f3d4790d6 /src/gallium | |
| parent | a71139470c85580ff15b2404a50380d85453e550 (diff) | |
winsys/amdgpu: update amdgpu_addr_create for GFX9
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 46 |
1 files changed, 29 insertions, 17 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index ede8ba619f7..0f51a5485dd 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -36,6 +36,9 @@ #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A #endif +#ifndef CIASICIDGFXENGINE_ARCTICISLAND +#define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D +#endif static int amdgpu_surface_sanity(const struct pipe_resource *tex) { @@ -107,32 +110,41 @@ ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws) addrCreateInput.size = sizeof(ADDR_CREATE_INPUT); addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT); - regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3; regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg; - regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2; - - regValue.backendDisables = ws->amdinfo.enabled_rb_pipes_mask; - regValue.pTileConfig = ws->amdinfo.gb_tile_mode; - regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode); - if (ws->info.chip_class == SI) { - regValue.pMacroTileConfig = NULL; - regValue.noOfMacroEntries = 0; + createFlags.value = 0; + + if (ws->info.chip_class >= GFX9) { + addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND; + regValue.blockVarSizeLog2 = 0; } else { - regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode; - regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode); - } + regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3; + regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2; - createFlags.value = 0; - createFlags.useTileIndex = 1; - createFlags.useHtileSliceAlign = 1; + regValue.backendDisables = ws->amdinfo.enabled_rb_pipes_mask; + regValue.pTileConfig = ws->amdinfo.gb_tile_mode; + regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode); + if (ws->info.chip_class == SI) { + regValue.pMacroTileConfig = NULL; + regValue.noOfMacroEntries = 0; + } else { + regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode; + regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode); + } + + createFlags.useTileIndex = 1; + createFlags.useHtileSliceAlign = 1; + + addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND; + addrCreateInput.chipFamily = ws->family; + addrCreateInput.chipRevision = ws->rev_id; + } - addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND; addrCreateInput.chipFamily = ws->family; addrCreateInput.chipRevision = ws->rev_id; - addrCreateInput.createFlags = createFlags; addrCreateInput.callbacks.allocSysMem = allocSysMem; addrCreateInput.callbacks.freeSysMem = freeSysMem; addrCreateInput.callbacks.debugPrint = 0; + addrCreateInput.createFlags = createFlags; addrCreateInput.regValue = regValue; addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput); |