radeon/llvm: Remove AMDIL LOADCONST* instructions

This obsoletes the R600LowerInstruction and SIPropagateImmReads passes.

13 files changed, 33 insertions, 322 deletions

diff --git a/src/gallium/drivers/radeon/AMDGPU.h b/src/gallium/drivers/radeon/AMDGPU.h
index 0f42cb744d3..9d81bc22336 100644
--- a/src/gallium/drivers/radeon/AMDGPU.h
+++ b/src/gallium/drivers/radeon/AMDGPU.h
@@ -22,11 +22,9 @@ class AMDGPUTargetMachine;
 // R600 Passes
 FunctionPass* createR600KernelParametersPass(const TargetData* TD);
 FunctionPass *createR600CodeEmitterPass(formatted_raw_ostream &OS);
-FunctionPass *createR600LowerInstructionsPass(TargetMachine &tm);
 
 // SI Passes
 FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
-FunctionPass *createSIPropagateImmReadsPass(TargetMachine &tm);
 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
 
 // Passes common to R600 and SI
diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
index 0601fbc0aa6..b4d2a2f5ea1 100644
--- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
@@ -135,9 +135,7 @@ bool AMDGPUPassConfig::addInstSelector() {
 bool AMDGPUPassConfig::addPreRegAlloc() {
   const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
 
-  if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
-    PM->add(createR600LowerInstructionsPass(*TM));
-  } else {
+  if (ST.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) {
     PM->add(createSIAssignInterpRegsPass(*TM));
   }
   PM->add(createAMDGPULowerInstructionsPass(*TM));
@@ -154,12 +152,8 @@ bool AMDGPUPassConfig::addPreSched2() {
 }
 
 bool AMDGPUPassConfig::addPreEmitPass() {
-  const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
   PM->add(createAMDILCFGPreparationPass(*TM));
   PM->add(createAMDILCFGStructurizerPass(*TM));
-  if (ST.device()->getGeneration() == AMDILDeviceInfo::HD7XXX) {
-    PM->add(createSIPropagateImmReadsPass(*TM));
-  }
 
   return false;
 }
diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp
index afb9170cdd2..018f97e8def 100644
--- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp
@@ -490,43 +490,6 @@ AMDILTargetLowering::LowerMemArgument(
 //===----------------------------------------------------------------------===//
 // TargetLowering Implementation Help Functions End
 //===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// Instruction generation functions
-//===----------------------------------------------------------------------===//
-MachineOperand
-AMDILTargetLowering::convertToReg(MachineOperand op) const
-{
-  if (op.isReg()) {
-    return op;
-  } else if (op.isImm()) {
-    uint32_t loadReg
-      = genVReg(op.getParent()->getDesc().OpInfo[0].RegClass);
-    generateMachineInst(AMDIL::LOADCONST_i32, loadReg)
-      .addImm(op.getImm());
-    op.ChangeToRegister(loadReg, false);
-  } else if (op.isFPImm()) {
-    uint32_t loadReg
-      = genVReg(op.getParent()->getDesc().OpInfo[0].RegClass);
-    generateMachineInst(AMDIL::LOADCONST_f32, loadReg)
-      .addFPImm(op.getFPImm());
-    op.ChangeToRegister(loadReg, false);
-  } else if (op.isMBB()) {
-    op.ChangeToRegister(0, false);
-  } else if (op.isFI()) {
-    op.ChangeToRegister(0, false);
-  } else if (op.isCPI()) {
-    op.ChangeToRegister(0, false);
-  } else if (op.isJTI()) {
-    op.ChangeToRegister(0, false);
-  } else if (op.isGlobal()) {
-    op.ChangeToRegister(0, false);
-  } else if (op.isSymbol()) {
-    op.ChangeToRegister(0, false);
-  }/* else if (op.isMetadata()) {
-      op.ChangeToRegister(0, false);
-      }*/
-  return op;
-}
 
 //===----------------------------------------------------------------------===//
 // TargetLowering Class Implementation Begins
diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.td b/src/gallium/drivers/radeon/AMDILInstrInfo.td
index 7086e53a0c0..969618e1afc 100644
--- a/src/gallium/drivers/radeon/AMDILInstrInfo.td
+++ b/src/gallium/drivers/radeon/AMDILInstrInfo.td
@@ -106,10 +106,3 @@ include "AMDILIntrinsics.td"
 // Instructions support
 //===--------------------------------------------------------------------===//
 include "AMDILInstructions.td"
-
-//===--------------------------------------------------------------------===//
-// Instruction Pattern support - This Must be the last include in the file
-// as it requires items defined in other files
-//===--------------------------------------------------------------------===//
-include "AMDILInstrPatterns.td"
-
diff --git a/src/gallium/drivers/radeon/AMDILInstrPatterns.td b/src/gallium/drivers/radeon/AMDILInstrPatterns.td
deleted file mode 100644
index a1e7e1fa258..00000000000
--- a/src/gallium/drivers/radeon/AMDILInstrPatterns.td
+++ /dev/null
@@ -1,35 +0,0 @@
-//===- AMDILInstrPatterns.td - AMDIL Target ------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//==-----------------------------------------------------------------------===//
-//===--------------------------------------------------------------------===//
-// This file holds all the custom patterns that are used by the amdil backend
-//
-//===--------------------------------------------------------------------===//
-//===--------------------------------------------------------------------===//
-// Custom patterns for conversion operations
-//===--------------------------------------------------------------------===////
-// float ==> long patterns
-// unsigned: f32 -> i64
-def FTOUL : Pat<(i64 (fp_to_uint GPRF32:$src)),
-    (LCREATE (FTOU GPRF32:$src), (LOADCONST_i32 0))>;
-// unsigned: i64 -> f32
-def ULTOF : Pat<(f32 (uint_to_fp GPRI64:$src)),
-    (UTOF (LLO GPRI64:$src))>;
-
-// LLVM isn't lowering this correctly, so writing a pattern that
-// matches it isntead.
-def : Pat<(build_vector (i32 imm:$src)),
-    (VCREATE_v4i32 (LOADCONST_i32 imm:$src))>;
-
-// Calls:
-def : Pat<(IL_call tglobaladdr:$dst),
-    (CALL tglobaladdr:$dst)>;
-def : Pat<(IL_call texternalsym:$dst),
-    (CALL texternalsym:$dst)>;
-def : Pat<(IL_call tconstpool:$dst),
-  (CALL tconstpool:$dst)>;
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td
index 0b26ac3a3af..586d18d0105 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -10,7 +10,6 @@
 // Operations in this file are generic to all data types
 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
-  defm LOADCONST  : ILConstant<"mov $dst, $val">;
   defm MOVE       : UnaryOpMC<IL_OP_MOV, IL_mov>;
   defm PHIMOVE    : UnaryOpMC<IL_OP_MOV, IL_phimov>;
 }
diff --git a/src/gallium/drivers/radeon/AMDILRegisterInfo.cpp b/src/gallium/drivers/radeon/AMDILRegisterInfo.cpp
index af2113b1526..51f6135b2fc 100644
--- a/src/gallium/drivers/radeon/AMDILRegisterInfo.cpp
+++ b/src/gallium/drivers/radeon/AMDILRegisterInfo.cpp
@@ -100,47 +100,7 @@ AMDILRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     int SPAdj,
     RegScavenger *RS) const
 {
-  assert(SPAdj == 0 && "Unexpected");
-  MachineInstr &MI = *II;
-  MachineFunction &MF = *MI.getParent()->getParent();
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  unsigned int y = MI.getNumOperands();
-  for (unsigned int x = 0; x < y; ++x) {
-    if (!MI.getOperand(x).isFI()) {
-      continue;
-    }
-    const AMDILInstrInfo * AMDILII =
-                         static_cast<const AMDILInstrInfo *>(TM.getInstrInfo());
-    bool def = AMDILII->isStoreInst(&MI);
-    int FrameIndex = MI.getOperand(x).getIndex();
-    int64_t Offset = MFI->getObjectOffset(FrameIndex);
-    //int64_t Size = MF.getFrameInfo()->getObjectSize(FrameIndex);
-    // An optimization is to only use the offsets if the size
-    // is larger than 4, which means we are storing an array
-    // instead of just a pointer. If we are size 4 then we can
-    // just do register copies since we don't need to worry about
-    // indexing dynamically
-    MachineInstr *nMI = MF.CreateMachineInstr(
-        TII.get(AMDIL::LOADCONST_i32), MI.getDebugLoc());
-    nMI->addOperand(MachineOperand::CreateReg(AMDIL::DFP, true));
-    nMI->addOperand(
-        MachineOperand::CreateImm(Offset));
-    MI.getParent()->insert(II, nMI);
-    nMI = MF.CreateMachineInstr(
-        TII.get(AMDIL::ADD_INT), MI.getDebugLoc());
-    nMI->addOperand(MachineOperand::CreateReg(AMDIL::DFP, true));
-    nMI->addOperand(MachineOperand::CreateReg(AMDIL::DFP, false));
-    nMI->addOperand(MachineOperand::CreateReg(AMDIL::FP, false));
-    
-    MI.getParent()->insert(II, nMI);
-    if (MI.getOperand(x).isReg() == false)  {
-      MI.getOperand(x).ChangeToRegister(
-          nMI->getOperand(0).getReg(), def);
-    } else {
-      MI.getOperand(x).setReg(
-          nMI->getOperand(0).getReg());
-    }
-  }
+  assert(!"Implement");
 }
 
 void
diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources
index 7ba09802b6d..9742e6b7790 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -41,7 +41,6 @@ CPP_SOURCES := \
 	R600ISelLowering.cpp		\
 	R600InstrInfo.cpp		\
 	R600KernelParameters.cpp	\
-	R600LowerInstructions.cpp	\
 	R600MachineFunctionInfo.cpp	\
 	R600RegisterInfo.cpp		\
 	SIAssignInterpRegs.cpp		\
@@ -49,7 +48,6 @@ CPP_SOURCES := \
 	SIInstrInfo.cpp			\
 	SIISelLowering.cpp		\
 	SIMachineFunctionInfo.cpp	\
-	SIPropagateImmReads.cpp		\
 	SIRegisterInfo.cpp		\
 	MCTargetDesc/AMDILMCAsmInfo.cpp	\
 	MCTargetDesc/AMDILMCTargetDesc.cpp	\
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 921d5650060..27744d1ab66 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -371,6 +371,25 @@ def FLOOR : R600_1OP <
 
 def MOV : R600_1OP <0x19, "MOV", []>;
 
+class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19,
+  (outs R600_Reg32:$dst),
+  (ins R600_Reg32:$alu_literal, immType:$imm),
+  "MOV_IMM $dst, $imm",
+  [], AnyALU
+>;
+
+def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
+def : Pat <
+  (imm:$val),
+  (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val)
+>;
+
+def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
+def : Pat <
+  (fpimm:$val),
+  (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val)
+>;
+
 def KILLGT : R600_2OP <
   0x2D, "KILLGT",
   []
@@ -821,7 +840,7 @@ let Predicates = [isEGorCayman] in {
   
 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
   (intr R600_Reg32:$src),
-  (trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src))
+  (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
 >;
 
   def MULADD_eg : MULADD_Common<0x14>;
diff --git a/src/gallium/drivers/radeon/R600LowerInstructions.cpp b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
deleted file mode 100644
index cd03e56026e..00000000000
--- a/src/gallium/drivers/radeon/R600LowerInstructions.cpp
+++ /dev/null
@@ -1,106 +0,0 @@
-//===-- R600LowerInstructions.cpp - Lower unsupported AMDIL instructions --===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This pass lowers AMDIL MachineInstrs that aren't supported by the R600
-// target to either supported AMDIL MachineInstrs or R600 MachineInstrs.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AMDGPU.h"
-#include "AMDGPUInstrInfo.h"
-#include "AMDGPUUtil.h"
-#include "AMDIL.h"
-#include "AMDILRegisterInfo.h"
-#include "R600InstrInfo.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Constants.h"
-#include "llvm/Target/TargetInstrInfo.h"
-
-#include <stdio.h>
-
-using namespace llvm;
-
-namespace {
-  class R600LowerInstructionsPass : public MachineFunctionPass {
-
-  private:
-    static char ID;
-    const R600InstrInfo * TII;
-
-  public:
-    R600LowerInstructionsPass(TargetMachine &tm) :
-      MachineFunctionPass(ID),
-      TII(static_cast<const R600InstrInfo*>(tm.getInstrInfo()))
-      { }
-
-    const char *getPassName() const { return "R600 Lower Instructions"; }
-    virtual bool runOnMachineFunction(MachineFunction &MF);
-
-  };
-} /* End anonymous namespace */
-
-char R600LowerInstructionsPass::ID = 0;
-
-FunctionPass *llvm::createR600LowerInstructionsPass(TargetMachine &tm) {
-  return new R600LowerInstructionsPass(tm);
-}
-
-bool R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
-{
-  for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
-                                                  BB != BB_E; ++BB) {
-    MachineBasicBlock &MBB = *BB;
-    for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
-         I != MBB.end(); I = Next, Next = llvm::next(I) ) {
-
-      MachineInstr &MI = *I;
-      switch(MI.getOpcode()) {
-      case AMDIL::LOADCONST_f32:
-      case AMDIL::LOADCONST_i32:
-        {
-          bool canInline = false;
-          unsigned inlineReg;
-          MachineOperand & dstOp = MI.getOperand(0);
-          MachineOperand & immOp = MI.getOperand(1);
-          if (immOp.isFPImm()) {
-            const ConstantFP * cfp = immOp.getFPImm();
-            if (cfp->isZero()) {
-              canInline = true;
-              inlineReg = AMDIL::ZERO;
-            } else if (cfp->isExactlyValue(1.0f)) {
-              canInline = true;
-              inlineReg = AMDIL::ONE;
-            } else if (cfp->isExactlyValue(0.5f)) {
-              canInline = true;
-              inlineReg = AMDIL::HALF;
-            }
-          }
-
-          if (canInline) {
-            BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::COPY))
-                    .addOperand(dstOp)
-                    .addReg(inlineReg);
-          } else {
-            BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::MOV))
-                    .addOperand(dstOp)
-                    .addReg(AMDIL::ALU_LITERAL_X)
-                    .addOperand(immOp);
-          }
-          break;
-        }
-      default:
-        continue;
-      }
-      MI.eraseFromParent();
-    }
-  }
-  return false;
-}
diff --git a/src/gallium/drivers/radeon/SIInstrInfo.cpp b/src/gallium/drivers/radeon/SIInstrInfo.cpp
index cd4e227e33b..40a1891b1a6 100644
--- a/src/gallium/drivers/radeon/SIInstrInfo.cpp
+++ b/src/gallium/drivers/radeon/SIInstrInfo.cpp
@@ -109,7 +109,7 @@ unsigned SIInstrInfo::getISAOpcode(unsigned AMDILopcode) const
 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
                                            int64_t Imm) const
 {
-  MachineInstr * MI = MF->CreateMachineInstr(get(AMDIL::V_MOV_IMM), DebugLoc());
+  MachineInstr * MI = MF->CreateMachineInstr(get(AMDIL::V_MOV_IMM_I32), DebugLoc());
   MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
   MachineInstrBuilder(MI).addImm(Imm);
 
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
index fc8ec4a3394..4408777a5f1 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -773,22 +773,25 @@ def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
 
-def V_MOV_IMM : VOP1 <
+class V_MOV_IMM <Operand immType, SDNode immNode> : VOP1 <
   0x1,
   (outs VReg_32:$dst),
-  (ins f32imm:$src0),
+  (ins immType:$src0),
   "V_MOV_IMM",
-   []
+   [(set VReg_32:$dst, (immNode:$src0))]
 >;
 
+def V_MOV_IMM_I32 : V_MOV_IMM<i32imm, imm>;
+def V_MOV_IMM_F32 : V_MOV_IMM<f32imm, fpimm>;
+
 def S_MOV_IMM_I32 : SOP1 <
   0x3,
   (outs SReg_32:$dst),
   (ins i32Literal:$src0),
-  "S_MOV_IMM",
-  [] > {
-  let neverHasSideEffects = 1;
-}
+  "S_MOV_IMM_I32",
+  [(set SReg_32:$dst, (imm:$src0))]
+>;
+
 
 let isCodeGenOnly = 1, isPseudo = 1 in {
 
diff --git a/src/gallium/drivers/radeon/SIPropagateImmReads.cpp b/src/gallium/drivers/radeon/SIPropagateImmReads.cpp
deleted file mode 100644
index 39c9532d4de..00000000000
--- a/src/gallium/drivers/radeon/SIPropagateImmReads.cpp
+++ /dev/null
@@ -1,75 +0,0 @@
-//===-- SIPropagateImmReads.cpp - Lower Immediate Reads Pass --------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// We can't do this in the ConvertToISA pass, because later passes might
-// create LOADCONST_* instructions that we would miss.  This is why we need 
-// a separate pass for this.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AMDGPU.h"
-#include "AMDGPUUtil.h"
-#include "SIInstrInfo.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-
-using namespace llvm;
-
-namespace {
-
-class SIPropagateImmReadsPass : public MachineFunctionPass {
-
-private:
-  static char ID;
-  TargetMachine &TM;
-
-public:
-  SIPropagateImmReadsPass(TargetMachine &tm) :
-    MachineFunctionPass(ID), TM(tm) { }
-
-  virtual bool runOnMachineFunction(MachineFunction &MF);
-};
-
-} // End anonymous namespace
-
-char SIPropagateImmReadsPass::ID = 0;
-
-FunctionPass *llvm::createSIPropagateImmReadsPass(TargetMachine &tm) {
-  return new SIPropagateImmReadsPass(tm);
-}
-
-bool SIPropagateImmReadsPass::runOnMachineFunction(MachineFunction &MF)
-{
-  const SIInstrInfo * TII = static_cast<const SIInstrInfo*>(TM.getInstrInfo());
-
-  for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
-                                                  BB != BB_E; ++BB) {
-    MachineBasicBlock &MBB = *BB;
-    for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
-         I != MBB.end(); I = Next, Next = llvm::next(I)) {
-      MachineInstr &MI = *I;
-
-      switch (MI.getOpcode()) {
-      case AMDIL::LOADCONST_f32:
-      case AMDIL::LOADCONST_i32:
-      case AMDIL::LOADCONST_i64:
-        break;
-      default:
-        continue;
-      }
-
-      // XXX: Create and use S_MOV_IMM for SREGs
-      BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::V_MOV_IMM))
-          .addOperand(MI.getOperand(0))
-          .addOperand(MI.getOperand(1));
-
-      MI.eraseFromParent();
-    }
-  }
-  return false;
-}