diff options
author | Dave Airlie <[email protected]> | 2017-10-10 06:27:10 +1000 |
---|---|---|
committer | Dave Airlie <[email protected]> | 2017-10-11 07:39:32 +1000 |
commit | ce0ee31890be189fc394454a7c87b745f8c1ac9e (patch) | |
tree | da42d9db173fa0a911492507eb1b62316108b590 /src/gallium | |
parent | 80bbdb148335c55303960bab841d98f4fbd1feea (diff) |
r600: drop tc_L2_dirty bit, this was SI only.
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r-- | src/gallium/drivers/r600/r600_buffer_common.c | 2 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600_pipe_common.h | 12 | ||||
-rw-r--r-- | src/gallium/drivers/r600/r600_query.c | 1 |
3 files changed, 0 insertions, 15 deletions
diff --git a/src/gallium/drivers/r600/r600_buffer_common.c b/src/gallium/drivers/r600/r600_buffer_common.c index f35bc2c813b..a6e3b7fcf15 100644 --- a/src/gallium/drivers/r600/r600_buffer_common.c +++ b/src/gallium/drivers/r600/r600_buffer_common.c @@ -234,7 +234,6 @@ bool r600_alloc_resource(struct r600_common_screen *rscreen, pb_reference(&old_buf, NULL); util_range_set_empty(&res->valid_buffer_range); - res->TC_L2_dirty = false; /* Print debug information. */ if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) { @@ -607,7 +606,6 @@ r600_alloc_buffer_struct(struct pipe_screen *screen, rbuffer->buf = NULL; rbuffer->bind_history = 0; - rbuffer->TC_L2_dirty = false; util_range_init(&rbuffer->valid_buffer_range); return rbuffer; } diff --git a/src/gallium/drivers/r600/r600_pipe_common.h b/src/gallium/drivers/r600/r600_pipe_common.h index 87c48e33e31..a6406cfdb23 100644 --- a/src/gallium/drivers/r600/r600_pipe_common.h +++ b/src/gallium/drivers/r600/r600_pipe_common.h @@ -165,18 +165,6 @@ struct r600_resource { */ struct util_range valid_buffer_range; - /* For buffers only. This indicates that a write operation has been - * performed by TC L2, but the cache hasn't been flushed. - * Any hw block which doesn't use or bypasses TC L2 should check this - * flag and flush the cache before using the buffer. - * - * For example, TC L2 must be flushed if a buffer which has been - * modified by a shader store instruction is about to be used as - * an index buffer. The reason is that VGT DMA index fetching doesn't - * use TC L2. - */ - bool TC_L2_dirty; - /* Whether the resource has been exported via resource_get_handle. */ unsigned external_usage; /* PIPE_HANDLE_USAGE_* */ diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c index 86e6d097869..aa3e36f56f7 100644 --- a/src/gallium/drivers/r600/r600_query.c +++ b/src/gallium/drivers/r600/r600_query.c @@ -1739,7 +1739,6 @@ static void r600_query_hw_get_result_resource(struct r600_common_context *rctx, ssbo[2].buffer_offset = offset; ssbo[2].buffer_size = 8; - ((struct r600_resource *)resource)->TC_L2_dirty = true; } rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo); |