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authorEric Anholt <[email protected]>2014-11-20 19:41:26 -0800
committerEric Anholt <[email protected]>2014-11-24 12:37:33 -0800
commitfa74ec7e98edb185806967fb17dd2d885727aa95 (patch)
treead2e8ff9e8f12a4aa8035d895593229ef3d04f49 /src/gallium
parent2b4fe85f0ea613463b8bba3149183eca97e98e75 (diff)
vc4: Add a note about a piece of errata I've learned about.
Right now in my environment I've only got a small CMA area, so this constraint ends up holding.
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/vc4/vc4_draw.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/gallium/drivers/vc4/vc4_draw.c b/src/gallium/drivers/vc4/vc4_draw.c
index e70506b6245..2d824624b5f 100644
--- a/src/gallium/drivers/vc4/vc4_draw.c
+++ b/src/gallium/drivers/vc4/vc4_draw.c
@@ -48,6 +48,10 @@ vc4_start_draw(struct vc4_context *vc4)
* BO allocations align to that anyway), then for some reason the
* simulator wants an extra page available, even if you have overflow
* memory set up.
+ *
+ * XXX: The binner only does 28-bit addressing math, so the tile alloc
+ * and tile state should be in the same BO and that BO needs to not
+ * cross a 256MB boundary, somehow.
*/
uint32_t tile_alloc_size = 32 * tilew * tileh;
tile_alloc_size = align(tile_alloc_size, 4096);