nv50,nvc0: clean up flushes

5 files changed, 28 insertions, 38 deletions

diff --git a/src/gallium/drivers/nouveau/nouveau_fence.c b/src/gallium/drivers/nouveau/nouveau_fence.c
index 18bdb18ad41..d8f59dce9ed 100644
--- a/src/gallium/drivers/nouveau/nouveau_fence.c
+++ b/src/gallium/drivers/nouveau/nouveau_fence.c
@@ -90,6 +90,9 @@ nouveau_fence_emit(struct nouveau_fence *fence)
 
    assert(fence->state == NOUVEAU_FENCE_STATE_AVAILABLE);
 
+   /* set this now, so that if fence.emit triggers a flush we don't recurse */
+   fence->state = NOUVEAU_FENCE_STATE_EMITTED;
+
    screen->fence.emit(&screen->base, fence->sequence);
 
    ++fence->ref;
@@ -100,8 +103,6 @@ nouveau_fence_emit(struct nouveau_fence *fence)
       screen->fence.head = fence;
 
    screen->fence.tail = fence;
-
-   fence->state = NOUVEAU_FENCE_STATE_EMITTED;
 }
 
 void
@@ -215,6 +216,8 @@ nouveau_fence_wait(struct nouveau_fence *fence)
 void
 nouveau_fence_next(struct nouveau_screen *screen)
 {
-   nouveau_fence_emit(screen->fence.current);
+   if (screen->fence.current->state < NOUVEAU_FENCE_STATE_EMITTED)
+      nouveau_fence_emit(screen->fence.current);
+
    nouveau_fence_new(screen, &screen->fence.current, FALSE);
 }
diff --git a/src/gallium/drivers/nv50/nv50_context.c b/src/gallium/drivers/nv50/nv50_context.c
index 204e9bef113..930cee7c1e7 100644
--- a/src/gallium/drivers/nv50/nv50_context.c
+++ b/src/gallium/drivers/nv50/nv50_context.c
@@ -33,22 +33,17 @@ static void
 nv50_flush(struct pipe_context *pipe,
            struct pipe_fence_handle **fence)
 {
-   struct nv50_context *nv50 = nv50_context(pipe);
-   struct nouveau_channel *chan = nv50->screen->base.channel;
-
-   /* XXX This flag wasn't set by the state tracker anyway. */
-   /*if (flags & PIPE_FLUSH_TEXTURE_CACHE) {
-      BEGIN_RING(chan, RING_3D_(NV50_GRAPH_WAIT_FOR_IDLE), 1);
-      OUT_RING  (chan, 0);
-      BEGIN_RING(chan, RING_3D(TEX_CACHE_CTL), 1);
-      OUT_RING  (chan, 0x20);
-   }*/
+   struct nouveau_screen *screen = &nv50_context(pipe)->screen->base;
 
    if (fence)
-      nouveau_fence_ref(nv50->screen->base.fence.current,
-                        (struct nouveau_fence **)fence);
+      nouveau_fence_ref(screen->fence.current, (struct nouveau_fence **)fence);
+
+   /* Try to emit before firing to avoid having to flush again right after
+    * in case we have to wait on this fence.
+    */
+   nouveau_fence_emit(screen->fence.current);
 
-   FIRE_RING(chan);
+   FIRE_RING(screen->channel);
 }
 
 void
diff --git a/src/gallium/drivers/nv50/nv50_state_validate.c b/src/gallium/drivers/nv50/nv50_state_validate.c
index bf46296e7ef..4ae58b156b6 100644
--- a/src/gallium/drivers/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nv50/nv50_state_validate.c
@@ -43,8 +43,9 @@ nv50_validate_fb(struct nv50_context *nv50)
       mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
       mt->base.status &= NOUVEAU_BUFFER_STATUS_GPU_READING;
 
+      /* only register for writing, otherwise we'd always serialize here */
       nv50_bufctx_add_resident(nv50, NV50_BUFCTX_FRAME, &mt->base,
-                               NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
+                               NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
    }
 
    if (fb->zsbuf) {
@@ -74,7 +75,7 @@ nv50_validate_fb(struct nv50_context *nv50)
       mt->base.status &= NOUVEAU_BUFFER_STATUS_GPU_READING;
 
       nv50_bufctx_add_resident(nv50, NV50_BUFCTX_FRAME, &mt->base,
-                               NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
+                               NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
    } else {
       BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
       OUT_RING  (chan, 0);
diff --git a/src/gallium/drivers/nvc0/nvc0_context.c b/src/gallium/drivers/nvc0/nvc0_context.c
index e4014b0d7ce..5d2168e600b 100644
--- a/src/gallium/drivers/nvc0/nvc0_context.c
+++ b/src/gallium/drivers/nvc0/nvc0_context.c
@@ -33,27 +33,17 @@ static void
 nvc0_flush(struct pipe_context *pipe,
            struct pipe_fence_handle **fence)
 {
-   struct nvc0_context *nvc0 = nvc0_context(pipe);
-   struct nouveau_channel *chan = nvc0->screen->base.channel;
-
-   /* XXX This flag wasn't set by the state tracker anyway. */
-   /*if (flags & PIPE_FLUSH_TEXTURE_CACHE) {
-      BEGIN_RING(chan, RING_3D(SERIALIZE), 1);
-      OUT_RING  (chan, 0);
-      BEGIN_RING(chan, RING_3D(TEX_CACHE_CTL), 1);
-      OUT_RING  (chan, 0x00);
-   } else*/
-   /* XXX FLUSH_FRAME is now implicit. */
-   /*if ((flags & PIPE_FLUSH_RENDER_CACHE) && !(flags & PIPE_FLUSH_FRAME)) {
-      BEGIN_RING(chan, RING_3D(SERIALIZE), 1);
-      OUT_RING  (chan, 0);
-   }*/
+   struct nouveau_screen *screen = &nvc0_context(pipe)->screen->base;
 
    if (fence)
-      nouveau_fence_ref(nvc0->screen->base.fence.current,
-                        (struct nouveau_fence **)fence);
+      nouveau_fence_ref(screen->fence.current, (struct nouveau_fence **)fence);
+
+   /* Try to emit before firing to avoid having to flush again right after
+    * in case we have to wait on this fence.
+    */
+   nouveau_fence_emit(screen->fence.current);
 
-   FIRE_RING(chan);
+   FIRE_RING(screen->channel);
 }
 
 static void
diff --git a/src/gallium/drivers/nvc0/nvc0_state_validate.c b/src/gallium/drivers/nvc0/nvc0_state_validate.c
index 4daa968de5a..b38d2d9dcc6 100644
--- a/src/gallium/drivers/nvc0/nvc0_state_validate.c
+++ b/src/gallium/drivers/nvc0/nvc0_state_validate.c
@@ -93,8 +93,9 @@ nvc0_validate_fb(struct nvc0_context *nvc0)
         mt->base.status |=  NOUVEAU_BUFFER_STATUS_GPU_WRITING;
         mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
 
+        /* only register for writing, otherwise we'd always serialize here */
         nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_FRAME, &mt->base,
-                                 NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
+                                 NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
     }
 
     if (fb->zsbuf) {
@@ -127,7 +128,7 @@ nvc0_validate_fb(struct nvc0_context *nvc0)
         mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
 
         nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_FRAME, &mt->base,
-                                 NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
+                                 NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
     } else {
         BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
         OUT_RING  (chan, 0);