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authorRob Clark <[email protected]>2019-12-03 13:44:35 -0800
committerRob Clark <[email protected]>2019-12-04 13:08:52 -0800
commit937b9055698be0dfdb7d2e0673a989e2ecc05912 (patch)
tree03c22d0d152a5c63f301e62314615649a25b75dc /src/gallium
parent4e47c205b9749aebb258075da36d176e1d453eb4 (diff)
freedreno/ir3: fix neverball assert in case of unused VS inputs
The logic to ensure VS and BS inputs are aligned wasn't accounting for unused inputs in VS. This *usually* doesn't happen, but it seems it can in the case of ARB programs? Fixes assert: ``` fd6_program_create: Assertion `bs->inputs[i].regid == vs->inputs[i].regid' failed. ``` Fixes: 882d53d8e36 ("freedreno/ir3+a6xx: same VBO state for draw/binning") Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_program.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index a37d1431d6c..888a4b91d90 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -256,9 +256,6 @@ setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *stat
OUT_RING(ring, state->fs->image_mapping.num_ibo);
}
-#define VALIDREG(r) ((r) != regid(63,0))
-#define CONDREG(r, val) COND(VALIDREG(r), (val))
-
static inline uint32_t
next_regid(uint32_t reg, uint32_t increment)
{