diff options
| author | Connor Abbott <[email protected]> | 2019-12-20 15:16:54 +0100 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-01-24 09:23:27 +0000 |
| commit | 3cf1d6b8db1287bf5e8647dfef21a58ff01750c1 (patch) | |
| tree | 83dd3df9842ad1d0d60ace65821cf89f6b1f79b0 /src/gallium | |
| parent | a31bcf2be6eeb74797ee1c989f866e3365c670e1 (diff) | |
freedreno: Document CP_COND_REG_EXEC more
The vulkan blob uses the RENDER_MODE mode to condition a blit on the
render mode in traces of a dEQP triangle test.
Reviewed-by: Rob Clark <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index e8f0992f310..74052baa5e1 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -462,8 +462,8 @@ emit_vsc_overflow_test(struct fd_batch *batch) A6XX_CP_REG_TEST_0_WAIT_FOR_ME); OUT_PKT7(ring, CP_COND_REG_EXEC, 2); - OUT_RING(ring, 0x10000000); - OUT_RING(ring, 7); /* conditionally execute next 7 dwords */ + OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST)); + OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(7)); /* if (b0 set) */ { /* @@ -569,8 +569,8 @@ emit_conditional_ib(struct fd_batch *batch, struct fd_tile *tile, A6XX_CP_REG_TEST_0_WAIT_FOR_ME); OUT_PKT7(ring, CP_COND_REG_EXEC, 2); - OUT_RING(ring, 0x10000000); - OUT_RING(ring, 4 * count); /* conditionally execute next 4*count dwords */ + OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST)); + OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(4 * count)); for (unsigned i = 0; i < count; i++) { uint32_t dwords; @@ -857,8 +857,8 @@ fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile) A6XX_CP_REG_TEST_0_WAIT_FOR_ME); OUT_PKT7(ring, CP_COND_REG_EXEC, 2); - OUT_RING(ring, 0x10000000); - OUT_RING(ring, 11); /* conditionally execute next 11 dwords */ + OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST)); + OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(11)); /* if (no overflow) */ { OUT_PKT7(ring, CP_SET_BIN_DATA5, 7); @@ -1333,8 +1333,8 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile) A6XX_CP_REG_TEST_0_WAIT_FOR_ME); OUT_PKT7(ring, CP_COND_REG_EXEC, 2); - OUT_RING(ring, 0x10000000); - OUT_RING(ring, 2); /* conditionally execute next 2 dwords */ + OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST)); + OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(2)); /* if (no overflow) */ { OUT_PKT7(ring, CP_SET_MARKER, 1); |