diff options
| author | Boyan Ding <[email protected]> | 2017-04-10 22:56:03 +0800 |
|---|---|---|
| committer | Ilia Mirkin <[email protected]> | 2017-04-13 02:25:08 -0400 |
| commit | 48d00779d00d64b46bea44a26e736455ff801d3a (patch) | |
| tree | f89289a78cd3bdd0afaf45aa628f991a24346a62 /src/gallium | |
| parent | f7787f224f401ea736037b74a413af50c226445e (diff) | |
nvc0/ir: Implement TGSI_SEMANTIC_SUBGROUP_*
Signed-off-by: Boyan Ding <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp index 3ed7d345c4b..1bd01a9a32f 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp @@ -450,6 +450,12 @@ static nv50_ir::SVSemantic translateSysVal(uint sysval) case TGSI_SEMANTIC_BASEINSTANCE: return nv50_ir::SV_BASEINSTANCE; case TGSI_SEMANTIC_DRAWID: return nv50_ir::SV_DRAWID; case TGSI_SEMANTIC_WORK_DIM: return nv50_ir::SV_WORK_DIM; + case TGSI_SEMANTIC_SUBGROUP_INVOCATION: return nv50_ir::SV_LANEID; + case TGSI_SEMANTIC_SUBGROUP_EQ_MASK: return nv50_ir::SV_LANEMASK_EQ; + case TGSI_SEMANTIC_SUBGROUP_LT_MASK: return nv50_ir::SV_LANEMASK_LT; + case TGSI_SEMANTIC_SUBGROUP_LE_MASK: return nv50_ir::SV_LANEMASK_LE; + case TGSI_SEMANTIC_SUBGROUP_GT_MASK: return nv50_ir::SV_LANEMASK_GT; + case TGSI_SEMANTIC_SUBGROUP_GE_MASK: return nv50_ir::SV_LANEMASK_GE; default: assert(0); return nv50_ir::SV_CLOCK; @@ -1667,6 +1673,8 @@ private: Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c); Symbol *dstToSym(tgsi::Instruction::DstRegister, int c); + bool isSubGroupMask(uint8_t semantic); + bool handleInstruction(const struct tgsi_full_instruction *); void exportOutputs(); inline Subroutine *getSubroutine(unsigned ip); @@ -1996,6 +2004,21 @@ Converter::adjustTempIndex(int arrayId, int &idx, int &idx2d) const idx += it->second; } +bool +Converter::isSubGroupMask(uint8_t semantic) +{ + switch (semantic) { + case TGSI_SEMANTIC_SUBGROUP_EQ_MASK: + case TGSI_SEMANTIC_SUBGROUP_LT_MASK: + case TGSI_SEMANTIC_SUBGROUP_LE_MASK: + case TGSI_SEMANTIC_SUBGROUP_GT_MASK: + case TGSI_SEMANTIC_SUBGROUP_GE_MASK: + return true; + default: + return false; + } +} + Value * Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr) { @@ -2041,6 +2064,10 @@ Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr) if (info->sv[idx].sn == TGSI_SEMANTIC_THREAD_ID && info->prop.cp.numThreads[swz] == 1) return loadImm(NULL, 0u); + if (isSubGroupMask(info->sv[idx].sn) && swz > 0) + return loadImm(NULL, 0u); + if (info->sv[idx].sn == TGSI_SEMANTIC_SUBGROUP_SIZE) + return loadImm(NULL, 32u); ld = mkOp1(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c)); ld->perPatch = info->sv[idx].patch; return ld->getDef(0); |