radeon/llvm: Remove AMDIL GLOBALLOAD* instructions

6 files changed, 24 insertions, 128 deletions

diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.cpp b/src/gallium/drivers/radeon/AMDILInstrInfo.cpp
index 8e27ae3433a..0ac56b5186d 100644
--- a/src/gallium/drivers/radeon/AMDILInstrInfo.cpp
+++ b/src/gallium/drivers/radeon/AMDILInstrInfo.cpp
@@ -531,7 +531,6 @@ switch (MI->getOpcode()) {
     default:
       break;
       ExpandCaseToByteShortTypes(AMDIL::LOCALLOAD);
-      ExpandCaseToByteShortTypes(AMDIL::GLOBALLOAD);
       ExpandCaseToByteShortTypes(AMDIL::REGIONLOAD);
       ExpandCaseToByteShortTypes(AMDIL::PRIVATELOAD);
       ExpandCaseToByteShortTypes(AMDIL::CPOOLLOAD);
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td
index 0197e9418f3..09b651c1919 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -791,7 +791,6 @@ let Predicates = [Has32BitPtr] in {
     //===---------------------------------------------------------------------===//
     // Load Memory Operations
     //===---------------------------------------------------------------------===//
-    defm GLOBALLOAD         : LOAD<"!global load"            , global_load>;
     defm GLOBALZEXTLOAD     : LOAD<"!global zext load"       , global_zext_load>;
     defm GLOBALSEXTLOAD     : LOAD<"!global sext load"       , global_sext_load>;
     defm GLOBALAEXTLOAD     : LOAD<"!global aext load"       , global_aext_load>;
@@ -1082,7 +1081,6 @@ let Predicates = [Has64BitPtr] in {
     //===---------------------------------------------------------------------===//
     // Load Memory Operations
     //===---------------------------------------------------------------------===//
-    defm GLOBALLOAD64       : LOAD64<"!global load"            , global_load>;
     defm GLOBALZEXTLOAD64   : LOAD64<"!global zext load"       , global_zext_load>;
     defm GLOBALSEXTLOAD64   : LOAD64<"!global sext load"       , global_sext_load>;
     defm GLOBALAEXTLOAD64   : LOAD64<"!global aext load"       , global_aext_load>;
diff --git a/src/gallium/drivers/radeon/R600CodeEmitter.cpp b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
index b13fd8bd2e6..e8d0efefff5 100644
--- a/src/gallium/drivers/radeon/R600CodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
@@ -202,7 +202,8 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
                 emit(inst);
                 break;
               }
-            case AMDIL::VTX_READ_eg:
+            case AMDIL::VTX_READ_PARAM_eg:
+            case AMDIL::VTX_READ_GLOBAL_eg:
               {
                 emitByte(INSTR_VTX);
                 // inst
@@ -212,7 +213,7 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
                 emitByte(2);
 
                 // buffer_id
-                emitByte(MI.getOperand(2).getImm());
+                emitByte(MI.getOpcode() == AMDIL::VTX_READ_PARAM_eg ? 0 : 1);
 
                 // src_gpr
                 emitByte(getHWReg(MI.getOperand(1).getReg()));
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 2347ac73b8f..1d4747fcfbe 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -226,15 +226,15 @@ void R600TargetLowering::lowerImplicitParameter(MachineInstr *MI, MachineBasicBl
     MachineRegisterInfo & MRI, unsigned dword_offset) const
 {
   MachineBasicBlock::iterator I = *MI;
-  unsigned offsetReg = MRI.createVirtualRegister(&AMDIL::R600_TReg32_XRegClass);
+  unsigned PtrReg = MRI.createVirtualRegister(&AMDIL::R600_TReg32_XRegClass);
   MRI.setRegClass(MI->getOperand(0).getReg(), &AMDIL::R600_TReg32_XRegClass);
 
-  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDIL::MOV), offsetReg)
+  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDIL::MOV), PtrReg)
           .addReg(AMDIL::ALU_LITERAL_X)
           .addImm(dword_offset * 4);
 
-  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDIL::VTX_READ_eg))
+  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDIL::VTX_READ_PARAM_eg))
           .addOperand(MI->getOperand(0))
-          .addReg(offsetReg)
+          .addReg(PtrReg)
           .addImm(0);
 }
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 2f6378d8e53..1b2768de7ed 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -41,7 +41,11 @@ class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
   let Namespace = "AMDIL";
 }
 
-def MEMri : Operand<iPTRAny> {
+def MEMxi : Operand<iPTR> {
+  let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
+}
+
+def MEMrr : Operand<iPTR> {
   let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
 }
 
@@ -787,90 +791,20 @@ def RAT_WRITE_CACHELESS_eg :
   let BARRIER     = 1;
 }
 
-def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst),
-                                (ins R600_TReg32_X:$src, i32imm:$buffer_id),
-                                "VTX_READ_eg $dst, $src", []>
-{
-/*
-  bits<7> DST_GPR;
-  bits<7> SRC_GPR;
-  bits<8> BUFFER_ID;
-*/
-  /* If any of these field below need to be calculated at compile time, and
-   * a ins operand for them and move them to the list of operands above. */
-
-  /* XXX: This instruction is manual encoded, so none of these values are used.
-   */
-/*
-  bits<5> VC_INST          = 0; //VC_INST_FETCH
-  bits<2> FETCH_TYPE       = 2;
-  bits<1> FETCH_WHOLE_QUAD = 1;
-  bits<1> SRC_REL          = 0;
-  bits<2> SRC_SEL_X        = 0;
-  bits<6> MEGA_FETCH_COUNT = 4;
-*/
-/*
-
-  bits<1> DST_REL          = 0;
-  bits<3> DST_SEL_X        = 0;
-  bits<3> DST_SEL_Y        = 7; //Masked
-  bits<3> DST_SEL_Z        = 7; //Masked
-  bits<3> DST_SEL_W        = 7; //Masked
-  bits<1> USE_CONST_FIELDS = 1; //Masked
-  bits<6> DATA_FORMAT      = 0;
-  bits<2> NUM_FORMAT_ALL   = 0;
-  bits<1> FORMAT_COMP_ALL  = 0;
-  bits<1> SRF_MODE_ALL     = 0;
-*/
-
-/*
-  let Inst{4-0}   = VC_INST;
-  let Inst{6-5}   = FETCH_TYPE;
-  let Inst{7}     = FETCH_WHOLE_QUAD;
-  let Inst{15-8}  = BUFFER_ID;
-  let Inst{22-16} = SRC_GPR;
-  let Inst{23}    = SRC_REL;
-  let Inst{25-24} = SRC_SEL_X;
-  let Inst{31-26} = MEGA_FETCH_COUNT;
-*/
-  /* DST_GPR is OK to leave uncommented, because LLVM 3.0 only prevents you
-   * from statically setting bits > 31.  This field will be set by
-   * getMachineValueOp which can set bits > 31.
-   */
-//  let Inst{32-38} = DST_GPR;
-
-  /* XXX: Uncomment for LLVM 3.1 which supports 64-bit instructions */
-
-/*
-  let Inst{39}    = DST_REL;
-  let Inst{40}    = 0; //Reserved
-  let Inst{43-41} = DST_SEL_X;
-  let Inst{46-44} = DST_SEL_Y;
-  let Inst{49-47} = DST_SEL_Z;
-  let Inst{52-50} = DST_SEL_W;
-  let Inst{53}    = USE_CONST_FIELDS;
-  let Inst{59-54} = DATA_FORMAT;
-  let Inst{61-60} = NUM_FORMAT_ALL;
-  let Inst{62}    = FORMAT_COMP_ALL;
-  let Inst{63}    = SRF_MODE_ALL;
-*/
-}
-
-/* XXX: Need to convert PTR to rat_id */
-/*
-def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr),
-           (RAT_WRITE_CACHELESS_eg (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
-                                                  (f32 R600_Reg32:$value),
-                                                   sel_x),
-                                    (f32 ZERO), 0, R600_Reg32:$ptr)>;
-*/
+class VTX_READ_eg <int buffer_id, list<dag> pattern> : InstR600ISA <
+  (outs R600_TReg32_X:$dst),
+  (ins MEMxi:$ptr),
+  "VTX_READ_eg $dst, $ptr",
+  pattern
+>;
 
-class VTX_Param_Read_Pattern <ValueType vt> : Pat <
-    (vt (load_param ADDRParam:$mem)),
-    (VTX_READ_eg (i32 R600_Reg32:$mem), 0)>;
+def VTX_READ_PARAM_eg : VTX_READ_eg <0,
+  [(set (i32 R600_TReg32_X:$dst), (load_param ADDRParam:$ptr))]
+>;
 
-def : VTX_Param_Read_Pattern <f32>;
-def : VTX_Param_Read_Pattern <i32>;
+def VTX_READ_GLOBAL_eg : VTX_READ_eg <1,
+  [(set (i32 R600_TReg32_X:$dst), (global_load ADDRParam:$ptr))]
+>;
 
 } // End isEG Predicate
 
@@ -1073,18 +1007,6 @@ def MASK_WRITE : AMDGPUShaderInst <
 
 } // End usesCustomInserter = 1
 
-let isPseudo = 1 in {
-
-def LOAD_VTX : AMDGPUShaderInst <
-    (outs R600_Reg32:$dst),
-    (ins MEMri:$mem),
-    "LOAD_VTX",
-    [(set (i32 R600_Reg32:$dst), (load_param ADDRParam:$mem))]
->;
-
-
-} //End isPseudo
-
 //===----------------------------------------------------------------------===//
 // ISel Patterns
 //===----------------------------------------------------------------------===//
diff --git a/src/gallium/drivers/radeon/R600LowerInstructions.cpp b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
index 61fd4f6db8a..932825ac3b6 100644
--- a/src/gallium/drivers/radeon/R600LowerInstructions.cpp
+++ b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
@@ -99,30 +99,6 @@ bool R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
         }
 */        /* XXX: This is an optimization */
 
-      case AMDIL::GLOBALLOAD_f32:
-      case AMDIL::GLOBALLOAD_i32:
-        {
-          MachineOperand &ptrOperand = MI.getOperand(1);
-          MachineOperand &indexOperand = MI.getOperand(2);
-          unsigned indexReg =
-                   MRI->createVirtualRegister(&AMDIL::R600_TReg32_XRegClass);
-
-          /* Calculate the address with in the VTX buffer */
-          calcAddress(ptrOperand, indexOperand, indexReg, MBB, I);
-
-          /* Make sure the VTX_READ_eg writes to the X chan */
-          MRI->setRegClass(MI.getOperand(0).getReg(),
-                          &AMDIL::R600_TReg32_XRegClass);
-
-          /* Add the VTX_READ_eg instruction */
-          BuildMI(MBB, I, MBB.findDebugLoc(I),
-                          TII->get(AMDIL::VTX_READ_eg))
-                  .addOperand(MI.getOperand(0))
-                  .addReg(indexReg)
-                  .addImm(1);
-          break;
-        }
-
       case AMDIL::GLOBALSTORE_i32:
       case AMDIL::GLOBALSTORE_f32:
         {