diff options
| author | Marek Olšák <[email protected]> | 2016-06-01 18:35:33 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-06-04 15:42:33 +0200 |
| commit | ade16e1f5d046f6407c4f0046efb8363520adcf0 (patch) | |
| tree | 01ddb53b1043f2a3b45576ae81875e262129ae6c /src/gallium | |
| parent | 7746903d3a68c97e86b88d5aa16995015b4db4ba (diff) | |
r600g: properly sync CP with CP DMA on R6xx
This will allow removing useless cache & IB flushes.
Reviewed-by: Alex Deucher <[email protected]>
Tested-by: Grazvydas Ignotas <[email protected]>
Tested-by: Dieter Nützel <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/r600/r600_hw_context.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index 6df1360a034..808bd27607f 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -405,7 +405,9 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx, unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT); unsigned src_reloc, dst_reloc; - r600_need_cs_space(rctx, 10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE); + r600_need_cs_space(rctx, + 10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0) + + 3, FALSE); /* Flush the caches for the first copy only. */ if (rctx->b.flags) { @@ -440,6 +442,11 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx, dst_offset += byte_count; } + /* CP_DMA_CP_SYNC doesn't wait for idle on R6xx, but this does. */ + if (rctx->b.chip_class == R600) + radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, + S_008040_WAIT_CP_DMA_IDLE(1)); + /* Invalidate the read caches. */ rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE | R600_CONTEXT_INV_VERTEX_CACHE | |