diff options
| author | Dave Airlie <[email protected]> | 2015-07-13 09:12:18 +0100 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2015-07-25 01:06:42 +0100 |
| commit | 7b40d92f0d0661c05c1afa59555905b2c37e594f (patch) | |
| tree | ae9d011f696ae0ed6a4ee9cd730cb66ab00487cb /src/gallium | |
| parent | b0654e368b1741083055efd281b981db4fb5724b (diff) | |
radeonsi: ubo indexing support (v2)
This is required as part of ARB_gpu_shader5.
no backend changes are required for this, or if
any are, it's the same ones as for samplers.
v2: use get_indirect_index (Marek)
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index d4a7d3b3617..81f7bdb3472 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -1191,7 +1191,7 @@ static LLVMValueRef fetch_constant( const struct tgsi_ind_register *ireg = ®->Indirect; unsigned buf, idx; - LLVMValueRef addr; + LLVMValueRef addr, bufp; LLVMValueRef result; if (swizzle == LP_CHAN_ALL) { @@ -1206,7 +1206,7 @@ static LLVMValueRef fetch_constant( buf = reg->Register.Dimension ? reg->Dimension.Index : 0; idx = reg->Register.Index * 4 + swizzle; - if (!reg->Register.Indirect) { + if (!reg->Register.Indirect && !reg->Dimension.Indirect) { if (type != TGSI_TYPE_DOUBLE) return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]); else { @@ -1216,13 +1216,22 @@ static LLVMValueRef fetch_constant( } } + if (reg->Register.Dimension && reg->Dimension.Indirect) { + LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST); + LLVMValueRef index; + index = get_indirect_index(si_shader_ctx, ®->DimIndirect, + reg->Dimension.Index); + bufp = build_indexed_load_const(si_shader_ctx, ptr, index); + } else + bufp = si_shader_ctx->const_resource[buf]; + addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle]; addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg"); addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16); addr = lp_build_add(&bld_base->uint_bld, addr, lp_build_const_int32(base->gallivm, idx * 4)); - result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf], + result = buffer_load_const(base->gallivm->builder, bufp, addr, bld_base->base.elem_type); if (type != TGSI_TYPE_DOUBLE) |