diff options
author | Eric Anholt <eric@anholt.net> | 2014-09-05 13:16:25 -0700 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2014-09-09 07:29:16 -0700 |
commit | 1663a8937499c4dd32fd5654b8bff4420e0d7679 (patch) | |
tree | 13f00df95ea6adfeeadb8f7aee974773865ddbec /src/gallium | |
parent | 2cbdbeb4fad16e2dfd340d8dd5f58a528edbede3 (diff) |
vc4: Don't forget to do initial tile clearing for depth/stencil.
Diffstat (limited to 'src/gallium')
-rw-r--r-- | src/gallium/drivers/vc4/vc4_context.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/gallium/drivers/vc4/vc4_context.c b/src/gallium/drivers/vc4/vc4_context.c index 91ff7d784e9..17a65452c80 100644 --- a/src/gallium/drivers/vc4/vc4_context.c +++ b/src/gallium/drivers/vc4/vc4_context.c @@ -75,8 +75,13 @@ vc4_setup_rcl(struct vc4_context *vc4) * stored. If the clear values changed between frames, then the tile * buffer has stale clear values in it, so we have to do a store in * None mode (no writes) so that we trigger the tile buffer clear. + * + * Excess clearing is only a performance cost, since per-tile contents + * will be loaded/stored in the loop below. */ - if (vc4->cleared & PIPE_CLEAR_COLOR0) { + if (vc4->cleared & (PIPE_CLEAR_COLOR0 | + PIPE_CLEAR_DEPTH | + PIPE_CLEAR_STENCIL)) { cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES); cl_u8(&vc4->rcl, 0); cl_u8(&vc4->rcl, 0); |