Merge remote-tracking branch 'origin/master' into pipe-video

Conflicts:
	configure.ac
	src/gallium/drivers/r600/r600_state_inlines.h
	src/gallium/tests/trivial/Makefile
	src/gallium/winsys/g3dvl/dri/XF86dri.c
	src/gallium/winsys/g3dvl/dri/driclient.c
	src/gallium/winsys/g3dvl/dri/driclient.h
	src/gallium/winsys/g3dvl/dri/xf86dri.h
	src/gallium/winsys/g3dvl/dri/xf86dristr.h
	src/gallium/winsys/r600/drm/r600_bo.c

14 files changed, 159 insertions, 132 deletions

diff --git a/src/gallium/winsys/i915/drm/SConscript b/src/gallium/winsys/i915/drm/SConscript
index d8f5885b62c..15c97998fd8 100644
--- a/src/gallium/winsys/i915/drm/SConscript
+++ b/src/gallium/winsys/i915/drm/SConscript
@@ -2,7 +2,7 @@ Import('*')
 
 env = env.Clone()
 
-env.ParseConfig('pkg-config --cflags libdrm')
+env.PkgUseModules('DRM')
 
 i915drm_sources = [
     'i915_drm_batchbuffer.c',
diff --git a/src/gallium/winsys/i915/drm/i915_drm_fence.c b/src/gallium/winsys/i915/drm/i915_drm_fence.c
index 30ebf4835ea..650ccfcd876 100644
--- a/src/gallium/winsys/i915/drm/i915_drm_fence.c
+++ b/src/gallium/winsys/i915/drm/i915_drm_fence.c
@@ -52,9 +52,13 @@ static int
 i915_drm_fence_signalled(struct i915_winsys *iws,
                           struct pipe_fence_handle *fence)
 {
-   assert(0);
+   struct i915_drm_fence *f = (struct i915_drm_fence *)fence;
 
-   return 0;
+   /* fence already expired */
+   if (!f->bo)
+	   return 1;
+
+   return !drm_intel_bo_busy(f->bo);
 }
 
 static int
diff --git a/src/gallium/winsys/i965/drm/SConscript b/src/gallium/winsys/i965/drm/SConscript
index 785be449f70..a0f32ded402 100644
--- a/src/gallium/winsys/i965/drm/SConscript
+++ b/src/gallium/winsys/i965/drm/SConscript
@@ -2,7 +2,7 @@ Import('*')
 
 env = env.Clone()
 
-env.ParseConfig('pkg-config --cflags libdrm')
+env.PkgUseModules('DRM')
 
 i965drm_sources = [
     'i965_drm_buffer.c',
diff --git a/src/gallium/winsys/r600/drm/SConscript b/src/gallium/winsys/r600/drm/SConscript
index cc9a06a2393..f55bb265226 100644
--- a/src/gallium/winsys/r600/drm/SConscript
+++ b/src/gallium/winsys/r600/drm/SConscript
@@ -13,11 +13,7 @@ r600_sources = [
     'r600_bomgr.c',
 ]
 
-try:
-    env.ParseConfig('pkg-config --cflags libdrm_radeon')
-except OSError:
-    print 'warning: not building r600g'
-    Return()
+env.PkgUseModules('DRM_RADEON')
 
 env.Append(CPPPATH = '#/src/gallium/drivers/r600')
 
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index e4ab690c560..4d9dd505c41 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -42,34 +42,34 @@
 
 static const struct r600_reg evergreen_config_reg_list[] = {
 	{R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
-	{R_008A14_PA_CL_ENHANCE, 0, 0, 0},
-	{R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C18_SQ_THREAD_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C20_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C24_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C28_SQ_STACK_RESOURCE_MGMT_3, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C18_SQ_THREAD_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C20_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C24_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C28_SQ_STACK_RESOURCE_MGMT_3, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 };
 
 
 static const struct r600_reg cayman_config_reg_list[] = {
 	{R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
-	{R_008A14_PA_CL_ENHANCE, 0, 0, 0},
-	{R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 };
 
 static const struct r600_reg evergreen_ctl_const_list[] = {
@@ -856,7 +856,7 @@ static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
 	return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET);
 }
 
-/* SHADER SAMPLER BORDER R600/R700 */
+/* SHADER SAMPLER BORDER EG/CM */
 static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 offset, unsigned id)
 {
 	struct r600_reg r600_shader_sampler_border[] = {
@@ -1121,7 +1121,6 @@ static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_c
 	 * will end up using the new border color. */
 	if (dirty & R600_BLOCK_STATUS_DIRTY)
 		evergreen_context_ps_partial_flush(ctx);
-
 	if (dirty)
 		r600_context_dirty_block(ctx, block, dirty, 4);
 }
diff --git a/src/gallium/winsys/r600/drm/r600_bo.c b/src/gallium/winsys/r600/drm/r600_bo.c
index d7e27e07e3b..4098a6e1998 100644
--- a/src/gallium/winsys/r600/drm/r600_bo.c
+++ b/src/gallium/winsys/r600/drm/r600_bo.c
@@ -38,31 +38,39 @@ struct r600_bo *r600_bo(struct radeon *radeon,
 {
 	struct r600_bo *bo;
 	struct radeon_bo *rbo;
-	uint32_t initial_domain;
+	uint32_t initial_domain, domains;
 	  
+	/* Staging resources particpate in transfers and blits only
+	 * and are used for uploads and downloads from regular
+	 * resources.  We generate them internally for some transfers.
+	 */
+	if (usage == PIPE_USAGE_STAGING)
+		domains = RADEON_GEM_DOMAIN_CPU | RADEON_GEM_DOMAIN_GTT;
+	else
+		domains = (RADEON_GEM_DOMAIN_CPU |
+				RADEON_GEM_DOMAIN_GTT |
+				RADEON_GEM_DOMAIN_VRAM);
+
 	if (binding & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
 		bo = r600_bomgr_bo_create(radeon->bomgr, size, alignment, *radeon->cfence);
 		if (bo) {
+			bo->domains = domains;
 			return bo;
 		}
 	}
 
-	if (binding & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
+	switch(usage) {
+	case PIPE_USAGE_DYNAMIC:
+	case PIPE_USAGE_STREAM:
+	case PIPE_USAGE_STAGING:
 		initial_domain = RADEON_GEM_DOMAIN_GTT;
-	} else {
-		switch(usage) {
-		case PIPE_USAGE_DYNAMIC:
-		case PIPE_USAGE_STREAM:
-		case PIPE_USAGE_STAGING:
-			initial_domain = RADEON_GEM_DOMAIN_GTT;
-			break;
-		case PIPE_USAGE_DEFAULT:
-		case PIPE_USAGE_STATIC:
-		case PIPE_USAGE_IMMUTABLE:
-		default:
-			initial_domain = RADEON_GEM_DOMAIN_VRAM;
-			break;
-		}
+		break;
+	case PIPE_USAGE_DEFAULT:
+	case PIPE_USAGE_STATIC:
+	case PIPE_USAGE_IMMUTABLE:
+	default:
+		initial_domain = RADEON_GEM_DOMAIN_VRAM;
+		break;
 	}
 	rbo = radeon_bo(radeon, 0, size, alignment, initial_domain);
 	if (rbo == NULL) {
@@ -72,35 +80,12 @@ struct r600_bo *r600_bo(struct radeon *radeon,
 	bo = calloc(1, sizeof(struct r600_bo));
 	bo->size = size;
 	bo->alignment = alignment;
+	bo->domains = domains;
 	bo->bo = rbo;
 	if (binding & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
 		r600_bomgr_bo_init(radeon->bomgr, bo);
 	}
 
-	/* Staging resources particpate in transfers and blits only
-	 * and are used for uploads and downloads from regular
-	 * resources.  We generate them internally for some transfers.
-	 */
-	switch (usage) {
-        case PIPE_USAGE_DEFAULT:
-		bo->domains = RADEON_GEM_DOMAIN_CPU |
-				RADEON_GEM_DOMAIN_GTT |
-				RADEON_GEM_DOMAIN_VRAM;
-                break;
-
-        case PIPE_USAGE_DYNAMIC:
-        case PIPE_USAGE_STREAM:
-        case PIPE_USAGE_STAGING:
-		bo->domains = RADEON_GEM_DOMAIN_CPU |
-                                RADEON_GEM_DOMAIN_GTT;
-		break;
-
-        case PIPE_USAGE_STATIC:
-        case PIPE_USAGE_IMMUTABLE:
-		bo->domains = RADEON_GEM_DOMAIN_VRAM;
-		break;
-        }
-
 	pipe_reference_init(&bo->reference, 1);
 	return bo;
 }
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
index 03fe385334c..4602f7f2a4b 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -156,7 +156,20 @@ static int eg_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
 		return -EINVAL;
 	}
 
-	radeon->tiling_info.num_banks = (tiling_config & 0xf0) >> 4;
+	switch ((tiling_config & 0xf0) >> 4) {
+	case 0:
+		radeon->tiling_info.num_banks = 4;
+		break;
+	case 1:
+		radeon->tiling_info.num_banks = 8;
+		break;
+	case 2:
+		radeon->tiling_info.num_banks = 16;
+		break;
+	default:
+		return -EINVAL;
+
+	}
 
 	switch ((tiling_config & 0xf00) >> 8) {
 	case 0:
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 711ce18c6ca..a21beeeba3c 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -40,6 +40,17 @@
 
 #define GROUP_FORCE_NEW_BLOCK	0
 
+static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
+{
+	if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
+		return;
+
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
+
+	ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
+}
+
 void r600_init_cs(struct r600_context *ctx)
 {
 	/* R6xx requires this packet at the start of each command buffer */
@@ -51,6 +62,8 @@ void r600_init_cs(struct r600_context *ctx)
 	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0);
 	ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
 	ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
+
+	ctx->init_dwords = ctx->pm4_cdwords;
 }
 
 static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
@@ -116,6 +129,9 @@ static void r600_init_block(struct r600_context *ctx,
 				LIST_ADDTAIL(&block->list,&ctx->dirty);
 			}
 		}
+		if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
+			block->flags |= REG_FLAG_FLUSH_CHANGE;
+		}
 
 		if (reg[i+j].flags & REG_FLAG_NEED_BO) {
 			block->nbo++;
@@ -206,17 +222,17 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
 /* R600/R700 configuration */
 static const struct r600_reg r600_config_reg_list[] = {
 	{R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
-	{R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS, 0, 0},
-	{R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+	{R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
 };
 
 static const struct r600_reg r600_ctl_const_list[] = {
@@ -1008,6 +1024,10 @@ void r600_context_dirty_block(struct r600_context *ctx,
 			LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
 		}
 		LIST_ADDTAIL(&block->list,&ctx->dirty);
+
+		if (block->flags & REG_FLAG_FLUSH_CHANGE) {
+			r600_context_ps_partial_flush(ctx);
+		}
 	}
 }
 
@@ -1187,16 +1207,6 @@ static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx,
 		r600_context_dirty_block(ctx, block, dirty, 2);
 }
 
-static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
-{
-	if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
-		return;
-
-	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
-	ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
-
-	ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
-}
 
 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
 {
@@ -1490,7 +1500,7 @@ void r600_context_flush(struct r600_context *ctx)
 	int r;
 	struct r600_block *enable_block = NULL;
 
-	if (!ctx->pm4_cdwords)
+	if (ctx->pm4_cdwords == ctx->init_dwords)
 		return;
 
 	/* suspend queries */
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
index 45bc64fcf9a..69f7251c043 100644
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -69,6 +69,7 @@ struct radeon {
 #define REG_FLAG_NOT_R600 8
 #define REG_FLAG_ENABLE_ALWAYS 16
 #define BLOCK_FLAG_RESOURCE 32
+#define REG_FLAG_FLUSH_CHANGE 64
 
 struct r600_reg {
 	unsigned			offset;
diff --git a/src/gallium/winsys/radeon/drm/SConscript b/src/gallium/winsys/radeon/drm/SConscript
index 39a8c711b84..2edb1e94645 100644
--- a/src/gallium/winsys/radeon/drm/SConscript
+++ b/src/gallium/winsys/radeon/drm/SConscript
@@ -8,11 +8,7 @@ radeon_sources = [
     'radeon_drm_winsys.c',
 ]
 
-try:
-    env.ParseConfig('pkg-config --cflags libdrm')
-except:
-    print 'warning: not building Gallium Radeon'
-    Return()
+env.PkgUseModules('DRM')
 
 radeonwinsys = env.ConvenienceLibrary(
     target ='radeonwinsys',
diff --git a/src/gallium/winsys/svga/drm/SConscript b/src/gallium/winsys/svga/drm/SConscript
index b049ea60aa8..3e25c8aa748 100644
--- a/src/gallium/winsys/svga/drm/SConscript
+++ b/src/gallium/winsys/svga/drm/SConscript
@@ -2,7 +2,7 @@ Import('*')
 
 env = env.Clone()
 
-env.ParseConfig('pkg-config --cflags libdrm')
+env.PkgUseModules('DRM')
 
 if env['gcc']:
     env.Append(CCFLAGS = ['-fvisibility=hidden'])
diff --git a/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.c b/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.c
index f4f4cd7969b..38d88f63aa2 100644
--- a/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.c
+++ b/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.c
@@ -54,10 +54,8 @@ struct fbdev_sw_winsys
    struct sw_winsys base;
 
    int fd;
-   enum pipe_format format;
 
    struct fb_fix_screeninfo finfo;
-   void *fbmem;
    unsigned rows;
    unsigned stride;
 };
@@ -77,22 +75,53 @@ fbdev_sw_winsys(struct sw_winsys *ws)
 static void
 fbdev_displaytarget_display(struct sw_winsys *ws,
                             struct sw_displaytarget *dt,
-                            void *context_private)
+                            void *winsys_private)
 {
    struct fbdev_sw_winsys *fbdev = fbdev_sw_winsys(ws);
-   struct fbdev_sw_displaytarget *fbdt = fbdev_sw_displaytarget(dt);
-   unsigned rows, len, i;
+   struct fbdev_sw_displaytarget *src = fbdev_sw_displaytarget(dt);
+   const struct fbdev_sw_drawable *dst =
+      (const struct fbdev_sw_drawable *) winsys_private;
+   unsigned height, row_offset, row_len, i;
+   void *fbmem;
+
+   /* FIXME format conversion */
+   if (dst->format != src->format) {
+      assert(0);
+      return;
+   }
 
-   rows = MIN2(fbdt->height, fbdev->rows);
-   len = util_format_get_stride(fbdt->format, fbdt->width);
-   len = MIN2(len, fbdev->stride);
+   height = dst->height;
+   if (dst->y + dst->height > fbdev->rows) {
+      /* nothing to copy */
+      if (dst->y >= fbdev->rows)
+         return;
 
-   for (i = 0; i < rows; i++) {
-      void *dst = fbdev->fbmem + fbdev->stride * i;
-      void *src = fbdt->data + fbdt->stride * i;
+      height = fbdev->rows - dst->y;
+   }
+
+   row_offset = util_format_get_stride(dst->format, dst->x);
+   row_len = util_format_get_stride(dst->format, dst->width);
+   if (row_offset + row_len > fbdev->stride) {
+      /* nothing to copy */
+      if (row_offset >= fbdev->stride)
+         return;
 
-      memcpy(dst, src, len);
+      row_len = fbdev->stride - row_offset;
    }
+
+   fbmem = mmap(0, fbdev->finfo.smem_len,
+         PROT_WRITE, MAP_SHARED, fbdev->fd, 0);
+   if (fbmem == MAP_FAILED)
+      return;
+
+   for (i = 0; i < height; i++) {
+      char *from = (char *) src->data + src->stride * i;
+      char *to = (char *) fbmem + fbdev->stride * (dst->y + i) + row_offset;
+
+      memcpy(to, from, row_len);
+   }
+
+   munmap(fbmem, fbdev->finfo.smem_len);
 }
 
 static void
@@ -133,13 +162,9 @@ fbdev_displaytarget_create(struct sw_winsys *ws,
                            unsigned alignment,
                            unsigned *stride)
 {
-   struct fbdev_sw_winsys *fbdev = fbdev_sw_winsys(ws);
    struct fbdev_sw_displaytarget *fbdt;
    unsigned nblocksy, size, format_stride;
 
-   if (fbdev->format != format)
-      return NULL;
-
    fbdt = CALLOC_STRUCT(fbdev_sw_displaytarget);
    if (!fbdt)
       return NULL;
@@ -170,8 +195,7 @@ fbdev_is_displaytarget_format_supported(struct sw_winsys *ws,
                                         unsigned tex_usage,
                                         enum pipe_format format)
 {
-   struct fbdev_sw_winsys *fbdev = fbdev_sw_winsys(ws);
-   return (fbdev->format == format);
+   return TRUE;
 }
 
 static void
@@ -179,12 +203,11 @@ fbdev_destroy(struct sw_winsys *ws)
 {
    struct fbdev_sw_winsys *fbdev = fbdev_sw_winsys(ws);
 
-   munmap(fbdev->fbmem, fbdev->finfo.smem_len);
    FREE(fbdev);
 }
 
 struct sw_winsys *
-fbdev_create_sw_winsys(int fd, enum pipe_format format)
+fbdev_create_sw_winsys(int fd)
 {
    struct fbdev_sw_winsys *fbdev;
 
@@ -193,19 +216,11 @@ fbdev_create_sw_winsys(int fd, enum pipe_format format)
       return NULL;
 
    fbdev->fd = fd;
-   fbdev->format = format;
    if (ioctl(fbdev->fd, FBIOGET_FSCREENINFO, &fbdev->finfo)) {
       FREE(fbdev);
       return NULL;
    }
 
-   fbdev->fbmem = mmap(0, fbdev->finfo.smem_len,
-         PROT_WRITE, MAP_SHARED, fbdev->fd, 0);
-   if (fbdev->fbmem == MAP_FAILED) {
-      FREE(fbdev);
-      return NULL;
-   }
-
    fbdev->rows = fbdev->finfo.smem_len / fbdev->finfo.line_length;
    fbdev->stride = fbdev->finfo.line_length;
 
diff --git a/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.h b/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.h
index d958ab9db3e..59d8a8f5cfe 100644
--- a/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.h
+++ b/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.h
@@ -32,7 +32,14 @@
 struct sw_winsys;
 enum pipe_format;
 
+/* for pipe_screen::flush_frontbuffer */
+struct fbdev_sw_drawable {
+   enum pipe_format format;
+   unsigned x, y;
+   unsigned width, height;
+};
+
 struct sw_winsys *
-fbdev_create_sw_winsys(int fd, enum pipe_format format);
+fbdev_create_sw_winsys(int fd);
 
 #endif /* FBDEV_SW_WINSYS */
diff --git a/src/gallium/winsys/sw/wayland/wayland_sw_winsys.h b/src/gallium/winsys/sw/wayland/wayland_sw_winsys.h
index 5e3cfd0bf23..bedd2408f05 100644
--- a/src/gallium/winsys/sw/wayland/wayland_sw_winsys.h
+++ b/src/gallium/winsys/sw/wayland/wayland_sw_winsys.h
@@ -27,6 +27,7 @@
 #define WAYLAND_SW_WINSYS
 
 struct sw_winsys;
+struct wl_display;
 
 struct winsys_handle {
    int fd;