diff options
author | Marek Olšák <[email protected]> | 2017-07-18 16:08:44 -0400 |
---|---|---|
committer | Christian König <[email protected]> | 2017-08-31 14:55:21 +0200 |
commit | 8b3a257851905ff444d981e52938cbf2b36ba830 (patch) | |
tree | de5c62f1052f5a0e025ebadc7599d1d4e6e79ebb /src/gallium/winsys | |
parent | 5ae2de81c8350272c122ea38e6bb4c0a41d58921 (diff) |
radeonsi: set a per-buffer flag that disables inter-process sharing (v4)
For lower overhead in the CS ioctl.
Winsys allocators are not used with interprocess-sharable resources.
v2: It shouldn't crash anymore, but the kernel will reject the new flag.
v3 (christian): Rename the flag, avoid sending those buffers in the BO list.
v4 (christian): Remove setting the kernel flag for now
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium/winsys')
-rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 30 | ||||
-rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 27 |
2 files changed, 33 insertions, 24 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index 1323be8356e..883a7c18e3e 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -1138,7 +1138,7 @@ amdgpu_bo_create(struct radeon_winsys *rws, { struct amdgpu_winsys *ws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo; - unsigned usage = 0, pb_cache_bucket; + unsigned usage = 0, pb_cache_bucket = 0; /* VRAM implies WC. This is not optional. */ assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC); @@ -1193,19 +1193,23 @@ no_slab: size = align64(size, ws->info.gart_page_size); alignment = align(alignment, ws->info.gart_page_size); - int heap = radeon_get_heap_index(domain, flags); - assert(heap >= 0 && heap < RADEON_MAX_CACHED_HEAPS); - usage = 1 << heap; /* Only set one usage bit for each heap. */ + bool use_reusable_pool = flags & RADEON_FLAG_NO_INTERPROCESS_SHARING; - pb_cache_bucket = radeon_get_pb_cache_bucket_index(heap); - assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); + if (use_reusable_pool) { + int heap = radeon_get_heap_index(domain, flags); + assert(heap >= 0 && heap < RADEON_MAX_CACHED_HEAPS); + usage = 1 << heap; /* Only set one usage bit for each heap. */ - /* Get a buffer from the cache. */ - bo = (struct amdgpu_winsys_bo*) - pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, usage, - pb_cache_bucket); - if (bo) - return &bo->base; + pb_cache_bucket = radeon_get_pb_cache_bucket_index(heap); + assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); + + /* Get a buffer from the cache. */ + bo = (struct amdgpu_winsys_bo*) + pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, usage, + pb_cache_bucket); + if (bo) + return &bo->base; + } /* Create a new one. */ bo = amdgpu_create_bo(ws, size, alignment, usage, domain, flags, @@ -1220,7 +1224,7 @@ no_slab: return NULL; } - bo->u.real.use_reusable_pool = true; + bo->u.real.use_reusable_pool = use_reusable_pool; return &bo->base; } diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index 8027a5f1ce8..15e9d38e33a 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -914,7 +914,7 @@ radeon_winsys_bo_create(struct radeon_winsys *rws, { struct radeon_drm_winsys *ws = radeon_drm_winsys(rws); struct radeon_bo *bo; - unsigned usage = 0, pb_cache_bucket; + unsigned usage = 0, pb_cache_bucket = 0; assert(!(flags & RADEON_FLAG_SPARSE)); /* not supported */ @@ -969,17 +969,22 @@ no_slab: size = align(size, ws->info.gart_page_size); alignment = align(alignment, ws->info.gart_page_size); - int heap = radeon_get_heap_index(domain, flags); - assert(heap >= 0 && heap < RADEON_MAX_CACHED_HEAPS); - usage = 1 << heap; /* Only set one usage bit for each heap. */ + bool use_reusable_pool = flags & RADEON_FLAG_NO_INTERPROCESS_SHARING; - pb_cache_bucket = radeon_get_pb_cache_bucket_index(heap); - assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); + /* Shared resources don't use cached heaps. */ + if (use_reusable_pool) { + int heap = radeon_get_heap_index(domain, flags); + assert(heap >= 0 && heap < RADEON_MAX_CACHED_HEAPS); + usage = 1 << heap; /* Only set one usage bit for each heap. */ - bo = radeon_bo(pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, - usage, pb_cache_bucket)); - if (bo) - return &bo->base; + pb_cache_bucket = radeon_get_pb_cache_bucket_index(heap); + assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); + + bo = radeon_bo(pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, + usage, pb_cache_bucket)); + if (bo) + return &bo->base; + } bo = radeon_create_bo(ws, size, alignment, usage, domain, flags, pb_cache_bucket); @@ -994,7 +999,7 @@ no_slab: return NULL; } - bo->u.real.use_reusable_pool = true; + bo->u.real.use_reusable_pool = use_reusable_pool; mtx_lock(&ws->bo_handles_mutex); util_hash_table_set(ws->bo_handles, (void*)(uintptr_t)bo->handle, bo); |