gallium/radeon: rename bo_size -> surf_size, bo_alignment -> surf_alignment

these names were misleading.

Reviewed-by: Nicolai Hähnle <[email protected]>

2 files changed, 9 insertions, 9 deletions

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index e6a26188677..27c425cd0ac 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -189,7 +189,7 @@ static int compute_level(struct amdgpu_winsys *ws,
    }
 
    surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
-   surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
+   surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
    surf_level->slice_size = AddrSurfInfoOut->sliceSize;
    surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
    surf_level->nblk_x = AddrSurfInfoOut->pitch;
@@ -214,7 +214,7 @@ static int compute_level(struct amdgpu_winsys *ws,
    else
       surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
 
-   surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
+   surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 
    /* Clear DCC fields at the beginning. */
    surf_level->dcc_offset = 0;
@@ -484,7 +484,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
       }
    }
 
-   surf->bo_size = 0;
+   surf->surf_size = 0;
    surf->dcc_size = 0;
    surf->dcc_alignment = 1;
    surf->htile_size = 0;
@@ -499,7 +499,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
          return r;
 
       if (level == 0) {
-         surf->bo_alignment = AddrSurfInfoOut.baseAlign;
+         surf->surf_alignment = AddrSurfInfoOut.baseAlign;
          surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
          set_micro_tile_mode(surf, &ws->info);
 
@@ -552,7 +552,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
     * complicated.
     */
    if (surf->dcc_size && tex->last_level > 0) {
-      surf->dcc_size = align64(surf->bo_size >> 8,
+      surf->dcc_size = align64(surf->surf_size >> 8,
                                ws->info.pipe_interleave_bytes *
                                ws->info.num_tile_pipes);
    }
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index e35f8a4e72e..fed96ee88eb 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -146,8 +146,8 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
             assert(0);
     }
 
-    surf_drm->bo_size = surf_ws->bo_size;
-    surf_drm->bo_alignment = surf_ws->bo_alignment;
+    surf_drm->bo_size = surf_ws->surf_size;
+    surf_drm->bo_alignment = surf_ws->surf_alignment;
 
     surf_drm->bankw = surf_ws->bankw;
     surf_drm->bankh = surf_ws->bankh;
@@ -178,8 +178,8 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
     surf_ws->bpe = surf_drm->bpe;
     surf_ws->flags = surf_drm->flags;
 
-    surf_ws->bo_size = surf_drm->bo_size;
-    surf_ws->bo_alignment = surf_drm->bo_alignment;
+    surf_ws->surf_size = surf_drm->bo_size;
+    surf_ws->surf_alignment = surf_drm->bo_alignment;
 
     surf_ws->bankw = surf_drm->bankw;
     surf_ws->bankh = surf_drm->bankh;