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authorDave Airlie <[email protected]>2010-09-01 14:56:04 +1000
committerDave Airlie <[email protected]>2010-09-01 14:56:04 +1000
commit1fa7245c348cb7aced81f1672140f64cb6450e2f (patch)
treeb053fbdcd99b786eebcfe40f0f3e22d62c403c56 /src/gallium/winsys
parentd7e2509692d3aa8afb8d2236a4f28b6ab502ec62 (diff)
Revert "r600g: precompute some of the hw state"
This reverts commit de0b76cab22caa9fc7260f80acb8f151ccced6c5, its pre-computes the texture state wrong, you can't just use an array of levels, since you can have FBOs to depth texture slices inside a level as well it would get really messy quickly. Probably need to split commits like this up into pieces for each piece of state, so we can revert bits easier in case of regressions. This also break 5 piglit tests, and valgrind starts to warn about invalid read/writes after this.
Diffstat (limited to 'src/gallium/winsys')
-rw-r--r--src/gallium/winsys/r600/drm/r600_state.c9
-rw-r--r--src/gallium/winsys/r600/drm/r600_states.h28
-rw-r--r--src/gallium/winsys/r600/drm/radeon_priv.h20
-rw-r--r--src/gallium/winsys/r600/drm/radeon_state.c62
4 files changed, 32 insertions, 87 deletions
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index f6a428e884d..e3d0116a2d1 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -80,7 +80,7 @@ struct radeon_stype_info r600_stypes[] = {
{ R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, SUB_NONE(VGT_EVENT) },
{ R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, SUB_NONE(VGT_EVENT) },
{ R600_STATE_DB, 1, 0, r600_state_pm4_db, SUB_NONE(DB) },
- { R600_STATE_UCP, 1, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
+ { R600_STATE_CLIP, 6, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
{ R600_STATE_VGT, 1, 0, r600_state_pm4_vgt, SUB_NONE(VGT) },
{ R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, SUB_NONE(DRAW) },
};
@@ -381,6 +381,13 @@ static int r600_state_pm4_draw(struct radeon_state *state)
if (r)
return r;
state->pm4[state->cpm4++] = state->bo[0]->handle;
+ } else if (state->nimmd) {
+ state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_IMMD, state->nimmd + 1);
+ state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
+ state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
+ for (i = 0; i < state->nimmd; i++) {
+ state->pm4[state->cpm4++] = state->immd[i];
+ }
} else {
state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index 09d79d498d8..51b69b92206 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -284,30 +284,10 @@ static const struct radeon_register R600_names_VS_CONSTANT[] = {
};
static const struct radeon_register R600_names_UCP[] = {
- {0x00028E20, 0, 0, "PA_CL_UCP0_X"},
- {0x00028E24, 0, 0, "PA_CL_UCP0_Y"},
- {0x00028E28, 0, 0, "PA_CL_UCP0_Z"},
- {0x00028E2C, 0, 0, "PA_CL_UCP0_W"},
- {0x00028E30, 0, 0, "PA_CL_UCP1_X"},
- {0x00028E34, 0, 0, "PA_CL_UCP1_Y"},
- {0x00028E38, 0, 0, "PA_CL_UCP1_Z"},
- {0x00028E3C, 0, 0, "PA_CL_UCP1_W"},
- {0x00028E40, 0, 0, "PA_CL_UCP2_X"},
- {0x00028E44, 0, 0, "PA_CL_UCP2_Y"},
- {0x00028E48, 0, 0, "PA_CL_UCP2_Z"},
- {0x00028E4C, 0, 0, "PA_CL_UCP2_W"},
- {0x00028E50, 0, 0, "PA_CL_UCP3_X"},
- {0x00028E54, 0, 0, "PA_CL_UCP3_Y"},
- {0x00028E58, 0, 0, "PA_CL_UCP3_Z"},
- {0x00028E5C, 0, 0, "PA_CL_UCP3_W"},
- {0x00028E60, 0, 0, "PA_CL_UCP4_X"},
- {0x00028E64, 0, 0, "PA_CL_UCP4_Y"},
- {0x00028E68, 0, 0, "PA_CL_UCP4_Z"},
- {0x00028E6C, 0, 0, "PA_CL_UCP4_W"},
- {0x00028E70, 0, 0, "PA_CL_UCP5_X"},
- {0x00028E74, 0, 0, "PA_CL_UCP5_Y"},
- {0x00028E78, 0, 0, "PA_CL_UCP5_Z"},
- {0x00028E7C, 0, 0, "PA_CL_UCP5_W"},
+ {0x00028e20, 0, 0, "PA_CL_UCP0_X"},
+ {0x00028e24, 0, 0, "PA_CL_UCP0_Y"},
+ {0x00028e28, 0, 0, "PA_CL_UCP0_Z"},
+ {0x00028e2c, 0, 0, "PA_CL_UCP0_W"},
};
static const struct radeon_register R600_names_PS_RESOURCE[] = {
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index af5319efd1f..66ee5f21771 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -38,19 +38,19 @@ struct radeon_register {
};
struct radeon_sub_type {
- int shader_type;
- const struct radeon_register *regs;
- unsigned nstates;
+ int shader_type;
+ const struct radeon_register *regs;
+ unsigned nstates;
};
struct radeon_stype_info {
- unsigned stype;
- unsigned num;
- unsigned stride;
- radeon_state_pm4_t pm4;
- struct radeon_sub_type reginfo[R600_SHADER_MAX];
- unsigned base_id;
- unsigned npm4;
+ unsigned stype;
+ unsigned num;
+ unsigned stride;
+ radeon_state_pm4_t pm4;
+ struct radeon_sub_type reginfo[R600_SHADER_MAX];
+ unsigned base_id;
+ unsigned npm4;
};
struct radeon {
diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c
index d4e622cf7fd..ef09fdfb960 100644
--- a/src/gallium/winsys/r600/drm/radeon_state.c
+++ b/src/gallium/winsys/r600/drm/radeon_state.c
@@ -80,57 +80,13 @@ struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 stype, u32 i
state->refcount = 1;
state->npm4 = found->npm4;
state->nstates = found->reginfo[shader_index].nstates;
- return state;
-}
-
-int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type)
-{
- struct radeon_stype_info *found = NULL;
- int i, j, shader_index = -1;
-
- if (state == NULL)
- return 0;
- /* traverse the stype array */
- for (i = 0; i < state->radeon->nstype; i++) {
- /* if the type doesn't match, if the shader doesn't match */
- if (stype != state->radeon->stype[i].stype)
- continue;
- if (shader_type) {
- for (j = 0; j < 4; j++) {
- if (state->radeon->stype[i].reginfo[j].shader_type == shader_type) {
- shader_index = j;
- break;
- }
- }
- if (shader_index == -1)
- continue;
- } else {
- if (state->radeon->stype[i].reginfo[0].shader_type)
- continue;
- else
- shader_index = 0;
- }
- if (id > state->radeon->stype[i].num)
- continue;
-
- found = &state->radeon->stype[i];
- break;
- }
-
- if (!found) {
- fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type);
- return -EINVAL;
- }
-
- if (found->reginfo[shader_index].nstates != state->nstates) {
- fprintf(stderr, "invalid type change from (%d %d %d) to (%d %d %d)\n",
- state->stype->stype, state->id, state->shader_index, stype, id, shader_index);
+ state->states = calloc(1, state->nstates * 4);
+ state->pm4 = calloc(1, found->npm4 * 4);
+ if (state->states == NULL || state->pm4 == NULL) {
+ radeon_state_decref(state);
+ return NULL;
}
-
- state->stype = found;
- state->id = id;
- state->shader_index = shader_index;
- return radeon_state_pm4(state);
+ return state;
}
struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
@@ -178,6 +134,9 @@ struct radeon_state *radeon_state_decref(struct radeon_state *state)
for (i = 0; i < state->nbo; i++) {
state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]);
}
+ free(state->immd);
+ free(state->states);
+ free(state->pm4);
memset(state, 0, sizeof(*state));
free(state);
return NULL;
@@ -220,9 +179,8 @@ int radeon_state_pm4(struct radeon_state *state)
{
int r;
- if (state == NULL)
+ if (state == NULL || state->cpm4)
return 0;
- state->cpm4 = 0;
r = state->stype->pm4(state);
if (r) {
fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n",