diff options
| author | Marek Olšák <[email protected]> | 2019-12-27 15:53:12 -0500 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2020-01-03 15:07:11 -0500 |
| commit | ba10fb3f7f41f7ec9e260117a3e037dadd57b9b5 (patch) | |
| tree | 6595cd47ac008207f42eb8d6670726f7690d5a2d /src/gallium/winsys | |
| parent | 1de06e540a1de6d857c5fd804e21a26840458c02 (diff) | |
radeonsi: preserve the scanout flag for shared resources on gfx9 and gfx10
Closes: #2195
Closes: #2294
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Diffstat (limited to 'src/gallium/winsys')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index 32ac276d2b6..8bbdb9b2eb0 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -1204,6 +1204,9 @@ static unsigned eg_tile_split_rev(unsigned eg_tile_split) } } +#define AMDGPU_TILING_SCANOUT_SHIFT 63 +#define AMDGPU_TILING_SCANOUT_MASK 0x1 + static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf, struct radeon_bo_metadata *md) { @@ -1226,6 +1229,7 @@ static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf, md->u.gfx9.dcc_offset_256B = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); md->u.gfx9.dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX); md->u.gfx9.dcc_independent_64B = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_64B); + md->u.gfx9.scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT); } else { md->u.legacy.microtile = RADEON_LAYOUT_LINEAR; md->u.legacy.macrotile = RADEON_LAYOUT_LINEAR; @@ -1263,6 +1267,7 @@ static void amdgpu_buffer_set_metadata(struct pb_buffer *_buf, tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, md->u.gfx9.dcc_offset_256B); tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, md->u.gfx9.dcc_pitch_max); tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, md->u.gfx9.dcc_independent_64B); + tiling_flags |= AMDGPU_TILING_SET(SCANOUT, md->u.gfx9.scanout); } else { if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */ |