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authorJerome Glisse <jglisse@redhat.com>2010-08-29 21:01:51 -0400
committerJerome Glisse <jglisse@redhat.com>2010-08-30 15:00:55 -0400
commitde0b76cab22caa9fc7260f80acb8f151ccced6c5 (patch)
treea8a5788f88ecf8b293b69daa435b564718a469ed /src/gallium/winsys
parent0bba7796a33d3c47295a9676dc82984da1615fe5 (diff)
r600g: precompute some of the hw state
Idea is to build hw state at pipe state creation and reuse them while keeping a non PM4 packet interface btw winsys & pipe driver. This commit also force rebuild of pm4 packet on each call to radeon_state_pm4 which in turn slow down everythings, this will be addressed. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Diffstat (limited to 'src/gallium/winsys')
-rw-r--r--src/gallium/winsys/r600/drm/r600_state.c9
-rw-r--r--src/gallium/winsys/r600/drm/r600_states.h28
-rw-r--r--src/gallium/winsys/r600/drm/radeon_priv.h20
-rw-r--r--src/gallium/winsys/r600/drm/radeon_state.c62
4 files changed, 87 insertions, 32 deletions
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index e3d0116a2d1..f6a428e884d 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -80,7 +80,7 @@ struct radeon_stype_info r600_stypes[] = {
{ R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, SUB_NONE(VGT_EVENT) },
{ R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, SUB_NONE(VGT_EVENT) },
{ R600_STATE_DB, 1, 0, r600_state_pm4_db, SUB_NONE(DB) },
- { R600_STATE_CLIP, 6, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
+ { R600_STATE_UCP, 1, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
{ R600_STATE_VGT, 1, 0, r600_state_pm4_vgt, SUB_NONE(VGT) },
{ R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, SUB_NONE(DRAW) },
};
@@ -381,13 +381,6 @@ static int r600_state_pm4_draw(struct radeon_state *state)
if (r)
return r;
state->pm4[state->cpm4++] = state->bo[0]->handle;
- } else if (state->nimmd) {
- state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_IMMD, state->nimmd + 1);
- state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
- state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
- for (i = 0; i < state->nimmd; i++) {
- state->pm4[state->cpm4++] = state->immd[i];
- }
} else {
state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index 51b69b92206..09d79d498d8 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -284,10 +284,30 @@ static const struct radeon_register R600_names_VS_CONSTANT[] = {
};
static const struct radeon_register R600_names_UCP[] = {
- {0x00028e20, 0, 0, "PA_CL_UCP0_X"},
- {0x00028e24, 0, 0, "PA_CL_UCP0_Y"},
- {0x00028e28, 0, 0, "PA_CL_UCP0_Z"},
- {0x00028e2c, 0, 0, "PA_CL_UCP0_W"},
+ {0x00028E20, 0, 0, "PA_CL_UCP0_X"},
+ {0x00028E24, 0, 0, "PA_CL_UCP0_Y"},
+ {0x00028E28, 0, 0, "PA_CL_UCP0_Z"},
+ {0x00028E2C, 0, 0, "PA_CL_UCP0_W"},
+ {0x00028E30, 0, 0, "PA_CL_UCP1_X"},
+ {0x00028E34, 0, 0, "PA_CL_UCP1_Y"},
+ {0x00028E38, 0, 0, "PA_CL_UCP1_Z"},
+ {0x00028E3C, 0, 0, "PA_CL_UCP1_W"},
+ {0x00028E40, 0, 0, "PA_CL_UCP2_X"},
+ {0x00028E44, 0, 0, "PA_CL_UCP2_Y"},
+ {0x00028E48, 0, 0, "PA_CL_UCP2_Z"},
+ {0x00028E4C, 0, 0, "PA_CL_UCP2_W"},
+ {0x00028E50, 0, 0, "PA_CL_UCP3_X"},
+ {0x00028E54, 0, 0, "PA_CL_UCP3_Y"},
+ {0x00028E58, 0, 0, "PA_CL_UCP3_Z"},
+ {0x00028E5C, 0, 0, "PA_CL_UCP3_W"},
+ {0x00028E60, 0, 0, "PA_CL_UCP4_X"},
+ {0x00028E64, 0, 0, "PA_CL_UCP4_Y"},
+ {0x00028E68, 0, 0, "PA_CL_UCP4_Z"},
+ {0x00028E6C, 0, 0, "PA_CL_UCP4_W"},
+ {0x00028E70, 0, 0, "PA_CL_UCP5_X"},
+ {0x00028E74, 0, 0, "PA_CL_UCP5_Y"},
+ {0x00028E78, 0, 0, "PA_CL_UCP5_Z"},
+ {0x00028E7C, 0, 0, "PA_CL_UCP5_W"},
};
static const struct radeon_register R600_names_PS_RESOURCE[] = {
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index 66ee5f21771..af5319efd1f 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -38,19 +38,19 @@ struct radeon_register {
};
struct radeon_sub_type {
- int shader_type;
- const struct radeon_register *regs;
- unsigned nstates;
+ int shader_type;
+ const struct radeon_register *regs;
+ unsigned nstates;
};
struct radeon_stype_info {
- unsigned stype;
- unsigned num;
- unsigned stride;
- radeon_state_pm4_t pm4;
- struct radeon_sub_type reginfo[R600_SHADER_MAX];
- unsigned base_id;
- unsigned npm4;
+ unsigned stype;
+ unsigned num;
+ unsigned stride;
+ radeon_state_pm4_t pm4;
+ struct radeon_sub_type reginfo[R600_SHADER_MAX];
+ unsigned base_id;
+ unsigned npm4;
};
struct radeon {
diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c
index ef09fdfb960..d4e622cf7fd 100644
--- a/src/gallium/winsys/r600/drm/radeon_state.c
+++ b/src/gallium/winsys/r600/drm/radeon_state.c
@@ -80,15 +80,59 @@ struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 stype, u32 i
state->refcount = 1;
state->npm4 = found->npm4;
state->nstates = found->reginfo[shader_index].nstates;
- state->states = calloc(1, state->nstates * 4);
- state->pm4 = calloc(1, found->npm4 * 4);
- if (state->states == NULL || state->pm4 == NULL) {
- radeon_state_decref(state);
- return NULL;
- }
return state;
}
+int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type)
+{
+ struct radeon_stype_info *found = NULL;
+ int i, j, shader_index = -1;
+
+ if (state == NULL)
+ return 0;
+ /* traverse the stype array */
+ for (i = 0; i < state->radeon->nstype; i++) {
+ /* if the type doesn't match, if the shader doesn't match */
+ if (stype != state->radeon->stype[i].stype)
+ continue;
+ if (shader_type) {
+ for (j = 0; j < 4; j++) {
+ if (state->radeon->stype[i].reginfo[j].shader_type == shader_type) {
+ shader_index = j;
+ break;
+ }
+ }
+ if (shader_index == -1)
+ continue;
+ } else {
+ if (state->radeon->stype[i].reginfo[0].shader_type)
+ continue;
+ else
+ shader_index = 0;
+ }
+ if (id > state->radeon->stype[i].num)
+ continue;
+
+ found = &state->radeon->stype[i];
+ break;
+ }
+
+ if (!found) {
+ fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type);
+ return -EINVAL;
+ }
+
+ if (found->reginfo[shader_index].nstates != state->nstates) {
+ fprintf(stderr, "invalid type change from (%d %d %d) to (%d %d %d)\n",
+ state->stype->stype, state->id, state->shader_index, stype, id, shader_index);
+ }
+
+ state->stype = found;
+ state->id = id;
+ state->shader_index = shader_index;
+ return radeon_state_pm4(state);
+}
+
struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
{
return radeon_state_shader(radeon, type, id, 0);
@@ -134,9 +178,6 @@ struct radeon_state *radeon_state_decref(struct radeon_state *state)
for (i = 0; i < state->nbo; i++) {
state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]);
}
- free(state->immd);
- free(state->states);
- free(state->pm4);
memset(state, 0, sizeof(*state));
free(state);
return NULL;
@@ -179,8 +220,9 @@ int radeon_state_pm4(struct radeon_state *state)
{
int r;
- if (state == NULL || state->cpm4)
+ if (state == NULL)
return 0;
+ state->cpm4 = 0;
r = state->stype->pm4(state);
if (r) {
fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n",