diff options
| author | Marek Olšák <[email protected]> | 2017-06-29 18:49:48 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-07-04 15:40:37 +0200 |
| commit | 0f13451da30a6ae298af297de18db595b791b62c (patch) | |
| tree | 6817d4b3d548e0090d35dd70a7d68bd56c161d4c /src/gallium/winsys | |
| parent | d4fac1e1d7f7c43663d64e826e946f6da2da7a73 (diff) | |
gallium/radeon: clean up pb_cache bucket/usage determination
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/winsys')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 21 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 21 |
2 files changed, 10 insertions, 32 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index 8e1bc8ed987..4c47f378de9 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -1188,22 +1188,11 @@ no_slab: size = align64(size, ws->info.gart_page_size); alignment = align(alignment, ws->info.gart_page_size); - /* Only set one usage bit each for domains and flags, or the cache manager - * might consider different sets of domains / flags compatible - */ - if (domain == RADEON_DOMAIN_VRAM_GTT) - usage = 1 << 2; - else - usage = domain >> 1; - assert(flags < sizeof(usage) * 8 - 3); - usage |= 1 << (flags + 3); - - /* Determine the pb_cache bucket for minimizing pb_cache misses. */ - pb_cache_bucket = 0; - if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */ - pb_cache_bucket += 1; - if (flags == RADEON_FLAG_GTT_WC) /* WC */ - pb_cache_bucket += 2; + int heap = radeon_get_heap_index(domain, flags); + assert(heap >= 0 && heap < RADEON_MAX_CACHED_HEAPS); + usage = 1 << heap; /* Only set one usage bit for each heap. */ + + pb_cache_bucket = radeon_get_pb_cache_bucket_index(heap); assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); /* Get a buffer from the cache. */ diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index 91f09b9f5d6..aa3fb788efc 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -969,22 +969,11 @@ no_slab: size = align(size, ws->info.gart_page_size); alignment = align(alignment, ws->info.gart_page_size); - /* Only set one usage bit each for domains and flags, or the cache manager - * might consider different sets of domains / flags compatible - */ - if (domain == RADEON_DOMAIN_VRAM_GTT) - usage = 1 << 2; - else - usage = (unsigned)domain >> 1; - assert(flags < sizeof(usage) * 8 - 3); - usage |= 1 << (flags + 3); - - /* Determine the pb_cache bucket for minimizing pb_cache misses. */ - pb_cache_bucket = 0; - if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */ - pb_cache_bucket += 1; - if (flags == RADEON_FLAG_GTT_WC) /* WC */ - pb_cache_bucket += 2; + int heap = radeon_get_heap_index(domain, flags); + assert(heap >= 0 && heap < RADEON_MAX_CACHED_HEAPS); + usage = 1 << heap; /* Only set one usage bit for each heap. */ + + pb_cache_bucket = radeon_get_pb_cache_bucket_index(heap); assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); bo = radeon_bo(pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, |