diff options
| author | Marek Olšák <[email protected]> | 2018-03-06 15:03:09 -0500 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-03-08 14:58:16 -0500 |
| commit | a4a113b5bc8e3248ebcfeac6f9c9ff24e85caadd (patch) | |
| tree | aa12e01cf1f8240a65f5a99531c1e6cc2c86fef9 /src/gallium/winsys | |
| parent | 35cd86d4e999149dcb51585c0e2a3a50a74c7bcb (diff) | |
winsys/amdgpu: pad compute IBs
v2: pad with PKT2 NOPs on SI
Reviewed-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src/gallium/winsys')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index d9a95c05093..a3feeb93026 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -1528,6 +1528,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs, } break; case RING_GFX: + case RING_COMPUTE: /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */ if (ws->info.gfx_ib_pad_with_type2) { while (rcs->current.cdw & 7) @@ -1536,7 +1537,8 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs, while (rcs->current.cdw & 7) radeon_emit(rcs, 0xffff1000); /* type3 nop packet */ } - ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4; + if (cs->ring_type == RING_GFX) + ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4; break; case RING_UVD: case RING_UVD_ENC: |