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authorMarek Olšák <[email protected]>2016-06-03 20:40:30 +0200
committerMarek Olšák <[email protected]>2016-06-08 00:22:45 +0200
commitaa7fe7044328039903993dde6edb32b7953ae9b0 (patch)
tree526b8903759ffcd65107621877b63273eec8931b /src/gallium/winsys
parent60e93ddd0675e525333ae928e94be31b973409de (diff)
radeonsi: add per-level dcc_enabled flags
Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/gallium/winsys')
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_surface.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index f609bf43f35..52b3fa88336 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -226,6 +226,10 @@ static int compute_level(struct amdgpu_winsys *ws,
surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
+ /* Clear DCC fields at the beginning. */
+ surf_level->dcc_offset = 0;
+ surf_level->dcc_enabled = false;
+
if (AddrSurfInfoIn->flags.dccCompatible) {
AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
@@ -239,15 +243,14 @@ static int compute_level(struct amdgpu_winsys *ws,
if (ret == ADDR_OK) {
surf_level->dcc_offset = surf->dcc_size;
+ surf_level->dcc_enabled = true;
surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
} else {
surf->dcc_size = 0;
- surf_level->dcc_offset = 0;
}
} else {
surf->dcc_size = 0;
- surf_level->dcc_offset = 0;
}
return 0;
@@ -344,7 +347,8 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
!(surf->flags & RADEON_SURF_SCANOUT) &&
!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
- !compressed && AddrDccIn.numSamples <= 1;
+ !compressed && AddrDccIn.numSamples <= 1 &&
+ surf->last_level == 0;
AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;