Merge remote-tracking branch 'origin/master' into pipe-video

5 files changed, 518 insertions, 58 deletions

diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 2a2c37ff606..cf8ae5185b4 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -57,6 +57,19 @@ static const struct r600_reg evergreen_config_reg_list[] = {
 	{R_00913C_SPI_CONFIG_CNTL_1, 0, 0, 0},
 };
 
+
+static const struct r600_reg cayman_config_reg_list[] = {
+	{R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
+	{R_008A14_PA_CL_ENHANCE, 0, 0, 0},
+	{R_008C00_SQ_CONFIG, 0, 0, 0},
+	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
+	{CM_R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0, 0},
+	{CM_R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0, 0},
+	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
+	{R_009100_SPI_CONFIG_CNTL, 0, 0, 0},
+	{R_00913C_SPI_CONFIG_CNTL_1, 0, 0, 0},
+};
+
 static const struct r600_reg evergreen_ctl_const_list[] = {
 	{R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
 	{R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
@@ -189,6 +202,7 @@ static const struct r600_reg evergreen_context_reg_list[] = {
 	{R_028610_PA_CL_UCP5_Y, 0, 0, 0},
 	{R_028614_PA_CL_UCP5_Z, 0, 0, 0},
 	{R_028618_PA_CL_UCP5_W, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 	{R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0},
 	{R_028620_SPI_VS_OUT_ID_1, 0, 0, 0},
 	{R_028624_SPI_VS_OUT_ID_2, 0, 0, 0},
@@ -199,6 +213,7 @@ static const struct r600_reg evergreen_context_reg_list[] = {
 	{R_028638_SPI_VS_OUT_ID_7, 0, 0, 0},
 	{R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0},
 	{R_028640_SPI_VS_OUT_ID_9, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 	{R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
 	{R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
 	{R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
@@ -231,6 +246,7 @@ static const struct r600_reg evergreen_context_reg_list[] = {
 	{R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
 	{R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
 	{R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 	{R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
 	{R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
 	{R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
@@ -421,6 +437,385 @@ static const struct r600_reg evergreen_context_reg_list[] = {
 	{R_028EAC_CB_COLOR11_DIM, 0, 0, 0},
 };
 
+static const struct r600_reg cayman_context_reg_list[] = {
+	{R_028000_DB_RENDER_CONTROL, 0, 0, 0},
+	{R_028004_DB_COUNT_CONTROL, 0, 0, 0},
+	{R_028008_DB_DEPTH_VIEW, 0, 0, 0},
+	{R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0},
+	{R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
+	{R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
+	{R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
+	{R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028044_DB_STENCIL_INFO, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028058_DB_DEPTH_SIZE, 0, 0, 0},
+	{R_02805C_DB_DEPTH_SLICE, 0, 0, 0},
+	{R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
+	{R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
+	{R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
+	{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
+	{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
+	{R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
+	{R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
+	{R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
+	{R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
+	{R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
+	{R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
+	{R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
+	{R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
+	{R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
+	{R_028230_PA_SC_EDGERULE, 0, 0, 0},
+	{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0},
+	{R_028238_CB_TARGET_MASK, 0, 0, 0},
+	{R_02823C_CB_SHADER_MASK, 0, 0, 0},
+	{R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
+	{R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
+	{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
+	{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
+	{R_028350_SX_MISC, 0, 0, 0},
+	{R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
+	{R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
+	{R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
+	{R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
+	{R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
+	{R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
+	{R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
+	{R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
+	{R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
+	{R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
+	{R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
+	{R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
+	{R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
+	{R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
+	{R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
+	{R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
+	{R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
+	{R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
+	{R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
+	{R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
+	{R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
+	{R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
+	{R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
+	{R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
+	{R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
+	{R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
+	{R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
+	{R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
+	{R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
+	{R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
+	{R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
+	{R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
+	{R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
+	{R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
+	{R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
+	{R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
+	{R_028408_VGT_INDX_OFFSET, 0, 0, 0},
+	{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
+	{R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
+	{R_028414_CB_BLEND_RED, 0, 0, 0},
+	{R_028418_CB_BLEND_GREEN, 0, 0, 0},
+	{R_02841C_CB_BLEND_BLUE, 0, 0, 0},
+	{R_028420_CB_BLEND_ALPHA, 0, 0, 0},
+	{R_028430_DB_STENCILREFMASK, 0, 0, 0},
+	{R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
+	{R_028438_SX_ALPHA_REF, 0, 0, 0},
+	{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
+	{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
+	{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
+	{R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
+	{R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
+	{R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
+	{R_0285BC_PA_CL_UCP0_X, 0, 0, 0},
+	{R_0285C0_PA_CL_UCP0_Y, 0, 0, 0},
+	{R_0285C4_PA_CL_UCP0_Z, 0, 0, 0},
+	{R_0285C8_PA_CL_UCP0_W, 0, 0, 0},
+	{R_0285CC_PA_CL_UCP1_X, 0, 0, 0},
+	{R_0285D0_PA_CL_UCP1_Y, 0, 0, 0},
+	{R_0285D4_PA_CL_UCP1_Z, 0, 0, 0},
+	{R_0285D8_PA_CL_UCP1_W, 0, 0, 0},
+	{R_0285DC_PA_CL_UCP2_X, 0, 0, 0},
+	{R_0285E0_PA_CL_UCP2_Y, 0, 0, 0},
+	{R_0285E4_PA_CL_UCP2_Z, 0, 0, 0},
+	{R_0285E8_PA_CL_UCP2_W, 0, 0, 0},
+	{R_0285EC_PA_CL_UCP3_X, 0, 0, 0},
+	{R_0285F0_PA_CL_UCP3_Y, 0, 0, 0},
+	{R_0285F4_PA_CL_UCP3_Z, 0, 0, 0},
+	{R_0285F8_PA_CL_UCP3_W, 0, 0, 0},
+	{R_0285FC_PA_CL_UCP4_X, 0, 0, 0},
+	{R_028600_PA_CL_UCP4_Y, 0, 0, 0},
+	{R_028604_PA_CL_UCP4_Z, 0, 0, 0},
+	{R_028608_PA_CL_UCP4_W, 0, 0, 0},
+	{R_02860C_PA_CL_UCP5_X, 0, 0, 0},
+	{R_028610_PA_CL_UCP5_Y, 0, 0, 0},
+	{R_028614_PA_CL_UCP5_Z, 0, 0, 0},
+	{R_028618_PA_CL_UCP5_W, 0, 0, 0},
+	{R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0},
+	{R_028620_SPI_VS_OUT_ID_1, 0, 0, 0},
+	{R_028624_SPI_VS_OUT_ID_2, 0, 0, 0},
+	{R_028628_SPI_VS_OUT_ID_3, 0, 0, 0},
+	{R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0},
+	{R_028630_SPI_VS_OUT_ID_5, 0, 0, 0},
+	{R_028634_SPI_VS_OUT_ID_6, 0, 0, 0},
+	{R_028638_SPI_VS_OUT_ID_7, 0, 0, 0},
+	{R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0},
+	{R_028640_SPI_VS_OUT_ID_9, 0, 0, 0},
+	{R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
+	{R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
+	{R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
+	{R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
+	{R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
+	{R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
+	{R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
+	{R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
+	{R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
+	{R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
+	{R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
+	{R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
+	{R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
+	{R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
+	{R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
+	{R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
+	{R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
+	{R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
+	{R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
+	{R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
+	{R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
+	{R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
+	{R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
+	{R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
+	{R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
+	{R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
+	{R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
+	{R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
+	{R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
+	{R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
+	{R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
+	{R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
+	{R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
+	{R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
+	{R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
+	{R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
+	{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
+	{R_0286D8_SPI_INPUT_Z, 0, 0, 0},
+	{R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
+	{R_0286E0_SPI_BARYC_CNTL, 0, 0, 0},
+	{R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0},
+	{R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0},
+	{R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
+	{R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
+	{R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
+	{R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
+	{R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
+	{R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
+	{R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
+	{R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
+	{R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
+	{CM_R_028804_DB_EQAA, 0, 0, 0},
+	{R_028808_CB_COLOR_CONTROL, 0, 0, 0},
+	{R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
+	{R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
+	{R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
+	{R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
+	{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
+	{R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
+	{R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0},
+	{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0},
+	{R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0},
+	{R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0},
+	{R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0},
+	{R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0},
+	{R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0},
+	{CM_R_0288E8_SQ_LDS_ALLOC, 0, 0, 0},
+	{R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0},
+	{R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
+	{R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
+	{R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
+	{R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
+	{R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
+	{R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
+	{R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
+	{R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0},
+	{R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0},
+	{R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0},
+	{R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
+	{R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
+	{R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
+	{R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
+	{R_028A14_VGT_HOS_CNTL, 0, 0, 0},
+	{R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
+	{R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
+	{R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
+	{R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
+	{R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
+	{R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
+	{R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
+	{R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
+	{R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
+	{R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
+	{R_028A40_VGT_GS_MODE, 0, 0, 0},
+	{R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0},
+	{R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0},
+	{R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
+	{R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
+	{R_028ABC_DB_HTILE_SURFACE, 0, 0, 0},
+	{R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0},
+	{R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
+	{R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0},
+	{R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0},
+	{R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0},
+	{R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
+	{R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
+	{R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
+	{R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
+	{R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
+	{R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
+	{R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0},
+	{R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0},
+	{CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0, 0, 0},
+	{CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0, 0, 0},
+	{CM_R_028BDC_PA_SC_LINE_CNTL, 0, 0, 0},
+	{CM_R_028BE0_PA_SC_AA_CONFIG, 0, 0, 0},
+	{CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0, 0},
+	{CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
+	{CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
+	{CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
+	{CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
+	{CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0, 0, 0},
+	{CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0, 0, 0},
+	{CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0, 0, 0},
+	{CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0, 0, 0},
+	{CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0, 0, 0},
+	{CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0, 0, 0},
+	{CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0, 0, 0},
+	{CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0, 0, 0},
+	{CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0, 0, 0},
+	{CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0, 0, 0},
+	{CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0, 0, 0},
+	{CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0, 0, 0},
+	{CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0, 0, 0},
+	{CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0, 0, 0},
+	{CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0, 0, 0},
+	{CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0, 0, 0},
+	{CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0, 0, 0},
+	{CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028C64_CB_COLOR0_PITCH, 0, 0, 0},
+	{R_028C68_CB_COLOR0_SLICE, 0, 0, 0},
+	{R_028C6C_CB_COLOR0_VIEW, 0, 0, 0},
+	{R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028C78_CB_COLOR0_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028CA0_CB_COLOR1_PITCH, 0, 0, 0},
+	{R_028CA4_CB_COLOR1_SLICE, 0, 0, 0},
+	{R_028CA8_CB_COLOR1_VIEW, 0, 0, 0},
+	{R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028CB4_CB_COLOR1_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028CDC_CB_COLOR2_PITCH, 0, 0, 0},
+	{R_028CE0_CB_COLOR2_SLICE, 0, 0, 0},
+	{R_028CE4_CB_COLOR2_VIEW, 0, 0, 0},
+	{R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028CF0_CB_COLOR2_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028D18_CB_COLOR3_PITCH, 0, 0, 0},
+	{R_028D1C_CB_COLOR3_SLICE, 0, 0, 0},
+	{R_028D20_CB_COLOR3_VIEW, 0, 0, 0},
+	{R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028D2C_CB_COLOR3_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028D54_CB_COLOR4_PITCH, 0, 0, 0},
+	{R_028D58_CB_COLOR4_SLICE, 0, 0, 0},
+	{R_028D5C_CB_COLOR4_VIEW, 0, 0, 0},
+	{R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028D68_CB_COLOR4_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028D90_CB_COLOR5_PITCH, 0, 0, 0},
+	{R_028D94_CB_COLOR5_SLICE, 0, 0, 0},
+	{R_028D98_CB_COLOR5_VIEW, 0, 0, 0},
+	{R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028DA4_CB_COLOR5_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028DCC_CB_COLOR6_PITCH, 0, 0, 0},
+	{R_028DD0_CB_COLOR6_SLICE, 0, 0, 0},
+	{R_028DD4_CB_COLOR6_VIEW, 0, 0, 0},
+	{R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028DE0_CB_COLOR6_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E08_CB_COLOR7_PITCH, 0, 0, 0},
+	{R_028E0C_CB_COLOR7_SLICE, 0, 0, 0},
+	{R_028E10_CB_COLOR7_VIEW, 0, 0, 0},
+	{R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E1C_CB_COLOR7_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E44_CB_COLOR8_PITCH, 0, 0, 0},
+	{R_028E48_CB_COLOR8_SLICE, 0, 0, 0},
+	{R_028E4C_CB_COLOR8_VIEW, 0, 0, 0},
+	{R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E58_CB_COLOR8_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E60_CB_COLOR9_PITCH, 0, 0, 0},
+	{R_028E64_CB_COLOR9_SLICE, 0, 0, 0},
+	{R_028E68_CB_COLOR9_VIEW, 0, 0, 0},
+	{R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E74_CB_COLOR9_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E7C_CB_COLOR10_PITCH, 0, 0, 0},
+	{R_028E80_CB_COLOR10_SLICE, 0, 0, 0},
+	{R_028E84_CB_COLOR10_VIEW, 0, 0, 0},
+	{R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E90_CB_COLOR10_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E98_CB_COLOR11_PITCH, 0, 0, 0},
+	{R_028E9C_CB_COLOR11_SLICE, 0, 0, 0},
+	{R_028EA0_CB_COLOR11_VIEW, 0, 0, 0},
+	{R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028EAC_CB_COLOR11_DIM, 0, 0, 0},
+};
+
 /* SHADER RESOURCE R600/R700 */
 static int evergreen_state_resource_init(struct r600_context *ctx, u32 offset)
 {
@@ -483,8 +878,8 @@ static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 off
 		return r;
 	}
 	/* set proper offset */
-	range = &ctx->range[CTX_RANGE_ID(ctx, r600_shader_sampler_border[0].offset)];
-	block = range->blocks[CTX_BLOCK_ID(ctx, r600_shader_sampler_border[0].offset)];
+	range = &ctx->range[CTX_RANGE_ID(r600_shader_sampler_border[0].offset)];
+	block = range->blocks[CTX_BLOCK_ID(r600_shader_sampler_border[0].offset)];
 	block->pm4[1] = (offset - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
 	return 0;
 }
@@ -519,12 +914,20 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 	}
 
 	/* add blocks */
-	r = r600_context_add_block(ctx, evergreen_config_reg_list,
-				   Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
+	if (r600_get_family(radeon) == CHIP_CAYMAN) 
+		r = r600_context_add_block(ctx, cayman_config_reg_list,
+					   Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
+	else
+		r = r600_context_add_block(ctx, evergreen_config_reg_list,
+					   Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
 	if (r)
 		goto out_err;
-	r = r600_context_add_block(ctx, evergreen_context_reg_list,
-				   Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
+	if (r600_get_family(radeon) == CHIP_CAYMAN) 
+		r = r600_context_add_block(ctx, cayman_context_reg_list,
+					   Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
+	else
+		r = r600_context_add_block(ctx, evergreen_context_reg_list,
+					   Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
 	if (r)
 		goto out_err;
 	r = r600_context_add_block(ctx, evergreen_ctl_const_list,
@@ -603,6 +1006,8 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 		r = -ENOMEM;
 		goto out_err;
 	}
+
+	r600_init_cs(ctx);
 	/* save 16dwords space for fence mecanism */
 	ctx->pm4_ndwords -= 16;
 
@@ -646,8 +1051,8 @@ static inline void evergreen_context_pipe_state_set_sampler(struct r600_context
 	int i;
 	int dirty;
 
-	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
-	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	range = &ctx->range[CTX_RANGE_ID(offset)];
+	block = range->blocks[CTX_BLOCK_ID(offset)];
 	if (state == NULL) {
 		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
 		LIST_DELINIT(&block->list);
@@ -684,8 +1089,8 @@ static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_c
 	int i;
 	int dirty;
 
-	range = &ctx->range[CTX_RANGE_ID(ctx, fake_offset)];
-	block = range->blocks[CTX_BLOCK_ID(ctx, fake_offset)];
+	range = &ctx->range[CTX_RANGE_ID(fake_offset)];
+	block = range->blocks[CTX_BLOCK_ID(fake_offset)];
 	if (state == NULL) {
 		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
 		LIST_DELINIT(&block->list);
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
index 311324f4f71..03fe385334c 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -320,6 +320,8 @@ static struct radeon *radeon_new(int fd, unsigned device)
 	case CHIP_CYPRESS:
 	case CHIP_HEMLOCK:
 	case CHIP_PALM:
+	case CHIP_SUMO:
+	case CHIP_SUMO2:
 	case CHIP_BARTS:
 	case CHIP_TURKS:
 	case CHIP_CAICOS:
@@ -327,6 +329,11 @@ static struct radeon *radeon_new(int fd, unsigned device)
 		/* set default group bytes, overridden by tiling info ioctl */
 		radeon->tiling_info.group_bytes = 512;
 		break;
+	case CHIP_CAYMAN:
+		radeon->chip_class = CAYMAN;
+		/* set default group bytes, overridden by tiling info ioctl */
+		radeon->tiling_info.group_bytes = 512;
+		break;
 	default:
 		fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
 			__func__, radeon->device);
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 0618d2329e6..af80aa67a44 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -40,6 +40,19 @@
 
 #define GROUP_FORCE_NEW_BLOCK	0
 
+void r600_init_cs(struct r600_context *ctx)
+{
+	/* R6xx requires this packet at the start of each command buffer */
+	if (ctx->radeon->family < CHIP_RV770) {
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_START_3D_CMDBUF, 0, 0);
+		ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
+	}
+	/* All asics require this one */
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
+	ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
+}
+
 static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
 {
 	for (int i = 0; i < ctx->creloc; i++) {
@@ -82,6 +95,12 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
 			continue;
 		}
 
+		/* ignore regs not on R600 on R600 */
+		if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->radeon->family == CHIP_R600) {
+			n = 1;
+			continue;
+		}
+
 		/* register that need relocation are in their own group */
 		/* find number of consecutive registers */
 		n = 0;
@@ -102,14 +121,14 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
 		}
 		ctx->nblocks++;
 		for (int j = 0; j < n; j++) {
-			range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)];
+			range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
 			/* create block table if it doesn't exist */
 			if (!range->blocks)
 				range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
 			if (!range->blocks)
 				return -1;
 
-			range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block;
+			range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
 		}
 
 		/* initialize block */
@@ -321,14 +340,14 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
 	{R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
 	{R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
-	{R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
-	{R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
-	{R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
-	{R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
-	{R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
-	{R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
-	{R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
-	{R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
+	{R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0, 0},
+	{R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0, 0},
+	{R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0, 0},
+	{R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0, 0},
+	{R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0, 0},
+	{R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0, 0},
+	{R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0, 0},
+	{R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0, 0},
 	{R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
 	{R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
 	{R_028804_CB_BLEND_CONTROL, 0, 0, 0},
@@ -624,8 +643,8 @@ void r600_context_fini(struct r600_context *ctx)
 			block = ctx->range[i].blocks[j];
 			if (block) {
 				for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
-					range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
-					range->blocks[CTX_BLOCK_ID(ctx, offset)] = NULL;
+					range = &ctx->range[CTX_RANGE_ID(offset)];
+					range->blocks[CTX_BLOCK_ID(offset)] = NULL;
 				}
 				for (int k = 1; k <= block->nbo; k++) {
 					r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
@@ -774,6 +793,8 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
 		r = -ENOMEM;
 		goto out_err;
 	}
+
+	r600_init_cs(ctx);
 	/* save 16dwords space for fence mecanism */
 	ctx->pm4_ndwords -= 16;
 
@@ -886,8 +907,8 @@ void r600_context_reg(struct r600_context *ctx,
 	unsigned new_val;
 	int dirty;
 
-	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
-	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	range = &ctx->range[CTX_RANGE_ID(offset)];
+	block = range->blocks[CTX_BLOCK_ID(offset)];
 	id = (offset - block->start_offset) >> 2;
 
 	dirty = block->status & R600_BLOCK_STATUS_DIRTY;
@@ -919,7 +940,6 @@ void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block
 
 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
 {
-	struct r600_range *range;
 	struct r600_block *block;
 	unsigned new_val;
 	int dirty;
@@ -927,9 +947,8 @@ void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_stat
 		unsigned id, reloc_id;
 		struct r600_pipe_reg *reg = &state->regs[i];
 
-		range = &ctx->range[CTX_RANGE_ID(ctx, reg->offset)];
-		block = range->blocks[CTX_BLOCK_ID(ctx, reg->offset)];
-		id = (reg->offset - block->start_offset) >> 2;
+		block = reg->block;
+		id = reg->id;
 
 		dirty = block->status & R600_BLOCK_STATUS_DIRTY;
 
@@ -963,8 +982,8 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_
 	int dirty;
 	int num_regs = ctx->radeon->chip_class >= EVERGREEN ? 8 : 7;
 
-	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
-	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	range = &ctx->range[CTX_RANGE_ID(offset)];
+	block = range->blocks[CTX_BLOCK_ID(offset)];
 	if (state == NULL) {
 		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
 		if (block->reloc[1].bo)
@@ -1057,8 +1076,8 @@ static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx,
 	int i;
 	int dirty;
 
-	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
-	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	range = &ctx->range[CTX_RANGE_ID(offset)];
+	block = range->blocks[CTX_BLOCK_ID(offset)];
 	if (state == NULL) {
 		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
 		LIST_DELINIT(&block->list);
@@ -1093,8 +1112,8 @@ static inline void r600_context_pipe_state_set_sampler_border(struct r600_contex
 	int i;
 	int dirty;
 
-	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
-	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	range = &ctx->range[CTX_RANGE_ID(offset)];
+	block = range->blocks[CTX_BLOCK_ID(offset)];
 	if (state == NULL) {
 		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
 		LIST_DELINIT(&block->list);
@@ -1146,8 +1165,8 @@ struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
 	struct r600_block *block;
 	unsigned id;
 
-	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
-	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	range = &ctx->range[CTX_RANGE_ID(offset)];
+	block = range->blocks[CTX_BLOCK_ID(offset)];
 	offset -= block->start_offset;
 	id = block->pm4_bo_index[offset >> 2];
 	if (block->reloc[id].bo) {
@@ -1159,11 +1178,16 @@ struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
 {
 	int id;
+	int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
+	int cp_dwords = block->pm4_ndwords, start_dword;
+	int new_dwords;
 
-	if (block->nreg_dirty == 0 && block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS)) {
+	if (block->nreg_dirty == 0 && optional) {
 		goto out;
 	}
 
+	optional &= (block->nreg_dirty != block->nreg);
+
 	ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
 	for (int j = 0; j < block->nreg; j++) {
 		if (block->pm4_bo_index[j]) {
@@ -1181,18 +1205,22 @@ void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *
 		}
 	}
 	ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
-	memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, block->pm4_ndwords * 4);
-	ctx->pm4_cdwords += block->pm4_ndwords;
-
-	if (block->nreg_dirty != block->nreg && block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS)) {
-		int new_dwords = block->nreg_dirty;
-		uint32_t oldword, newword;
-		ctx->pm4_cdwords -= block->pm4_ndwords;
-		newword = oldword = ctx->pm4[ctx->pm4_cdwords];
+
+	if (optional) {
+		new_dwords = block->nreg_dirty;
+		start_dword = ctx->pm4_cdwords;
+		cp_dwords = new_dwords + 2;
+	}
+	memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
+	ctx->pm4_cdwords += cp_dwords;
+
+	if (optional) {
+		uint32_t newword;
+
+		newword = ctx->pm4[start_dword];
 		newword &= PKT_COUNT_C;
 		newword |= PKT_COUNT_S(new_dwords);
-		ctx->pm4[ctx->pm4_cdwords] = newword;
-		ctx->pm4_cdwords += new_dwords + 2;
+		ctx->pm4[start_dword] = newword;
 	}
 out:
 	block->status ^= R600_BLOCK_STATUS_DIRTY;
@@ -1231,7 +1259,7 @@ void r600_context_flush_dest_caches(struct r600_context *ctx)
 					0, cb[i]);
 	}
 	if (db) {
-		r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1), 0, db);
+		r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1), 0, db);
 	}
 	ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
 	ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
@@ -1381,6 +1409,8 @@ void r600_context_flush(struct r600_context *ctx)
 	ctx->pm4_cdwords = 0;
 	ctx->flags = 0;
 
+	r600_init_cs(ctx);
+
 	/* resume queries */
 	r600_context_queries_resume(ctx);
 
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
index 78b8190d6f5..9be5c358f85 100644
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -65,6 +65,7 @@ struct radeon {
 #define REG_FLAG_NEED_BO 1
 #define REG_FLAG_DIRTY_ALWAYS 2
 #define REG_FLAG_RV6XX_SBU 4
+#define REG_FLAG_NOT_R600 8
 
 struct r600_reg {
 	unsigned			offset;
@@ -165,6 +166,7 @@ int r600_setup_block_table(struct r600_context *ctx);
 void r600_context_reg(struct r600_context *ctx,
 		      unsigned offset, unsigned value,
 		      unsigned mask);
+void r600_init_cs(struct r600_context *ctx);
 /*
  * r600_bo.c
  */
@@ -187,16 +189,6 @@ struct r600_bo *r600_bomgr_bo_create(struct r600_bomgr *mgr,
  * helpers
  */
 
-/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
-/* there is a block entry for each register so 512 blocks */
-/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
-/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
-#define RANGE_OFFSET_START 0x8000
-#define HASH_SHIFT 9
-#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
-
-#define CTX_RANGE_ID(ctx, offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
-#define CTX_BLOCK_ID(ctx, offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
 
 /*
  * radeon_bo.c
diff --git a/src/gallium/winsys/r600/drm/radeon_pciid.c b/src/gallium/winsys/r600/drm/radeon_pciid.c
index 35db37aa1fd..5c41a10bdba 100644
--- a/src/gallium/winsys/r600/drm/radeon_pciid.c
+++ b/src/gallium/winsys/r600/drm/radeon_pciid.c
@@ -439,6 +439,17 @@ static const struct pci_id radeon_pci_id[] = {
 	{0x1002, 0x9614, CHIP_RS780},
 	{0x1002, 0x9615, CHIP_RS780},
 	{0x1002, 0x9616, CHIP_RS780},
+	{0x1002, 0x9640, CHIP_SUMO},
+	{0x1002, 0x9641, CHIP_SUMO},
+	{0x1002, 0x9642, CHIP_SUMO2},
+	{0x1002, 0x9643, CHIP_SUMO2},
+	{0x1002, 0x9644, CHIP_SUMO2},
+	{0x1002, 0x9645, CHIP_SUMO2},
+	{0x1002, 0x9647, CHIP_SUMO},
+	{0x1002, 0x9648, CHIP_SUMO},
+	{0x1002, 0x964a, CHIP_SUMO},
+	{0x1002, 0x964e, CHIP_SUMO},
+	{0x1002, 0x964f, CHIP_SUMO},
 	{0x1002, 0x9710, CHIP_RS880},
 	{0x1002, 0x9711, CHIP_RS880},
 	{0x1002, 0x9712, CHIP_RS880},
@@ -451,6 +462,21 @@ static const struct pci_id radeon_pci_id[] = {
 	{0x1002, 0x9805, CHIP_PALM},
 	{0x1002, 0x9806, CHIP_PALM},
 	{0x1002, 0x9807, CHIP_PALM},
+	{0x1002, 0x6700, CHIP_CAYMAN},
+	{0x1002, 0x6701, CHIP_CAYMAN},
+	{0x1002, 0x6702, CHIP_CAYMAN},
+	{0x1002, 0x6703, CHIP_CAYMAN},
+	{0x1002, 0x6704, CHIP_CAYMAN},
+	{0x1002, 0x6705, CHIP_CAYMAN},
+	{0x1002, 0x6706, CHIP_CAYMAN},
+	{0x1002, 0x6707, CHIP_CAYMAN},
+	{0x1002, 0x6708, CHIP_CAYMAN},
+	{0x1002, 0x6709, CHIP_CAYMAN},
+	{0x1002, 0x6718, CHIP_CAYMAN},
+	{0x1002, 0x6719, CHIP_CAYMAN},
+	{0x1002, 0x671C, CHIP_CAYMAN},
+	{0x1002, 0x671D, CHIP_CAYMAN},
+	{0x1002, 0x671F, CHIP_CAYMAN},
 	{0x1002, 0x6720, CHIP_BARTS},
 	{0x1002, 0x6721, CHIP_BARTS},
 	{0x1002, 0x6722, CHIP_BARTS},