diff options
| author | Christian König <[email protected]> | 2011-05-15 19:26:53 +0200 |
|---|---|---|
| committer | Christian König <[email protected]> | 2011-05-15 19:26:53 +0200 |
| commit | 828540e491d88b9b6217e6568873a78462919ae8 (patch) | |
| tree | c952145c1188cdf6b9c56902f8f5c189e090c278 /src/gallium/winsys | |
| parent | 3db6514357a7c634045ae7bc7bba7d7dbf9d58c5 (diff) | |
| parent | bd5b7a6f7113da38a2c1f07a4a71e9993666a567 (diff) | |
Merge remote-tracking branch 'origin/master' into pipe-video
Diffstat (limited to 'src/gallium/winsys')
| -rw-r--r-- | src/gallium/winsys/r600/drm/evergreen_hw_context.c | 821 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/r600_hw_context.c | 892 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/r600_priv.h | 25 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/radeon_bo.c | 13 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 100 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.h | 10 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_winsys.h | 16 | ||||
| -rw-r--r-- | src/gallium/winsys/svga/drm/vmw_screen_svga.c | 14 |
8 files changed, 998 insertions, 893 deletions
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c index 0a5b1a09336..2a2c37ff606 100644 --- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c +++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c @@ -41,432 +41,432 @@ #define GROUP_FORCE_NEW_BLOCK 0 static const struct r600_reg evergreen_config_reg_list[] = { - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008A14_PA_CL_ENHANCE, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C20_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C24_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C28_SQ_STACK_RESOURCE_MGMT_3, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_009100_SPI_CONFIG_CNTL, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_00913C_SPI_CONFIG_CNTL_1, 0, 0, 0}, + {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, + {R_008A14_PA_CL_ENHANCE, 0, 0, 0}, + {R_008C00_SQ_CONFIG, 0, 0, 0}, + {R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0}, + {R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0}, + {R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0}, + {R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 0, 0, 0}, + {R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, 0, 0, 0}, + {R_008C20_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0}, + {R_008C24_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0}, + {R_008C28_SQ_STACK_RESOURCE_MGMT_3, 0, 0, 0}, + {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0}, + {R_009100_SPI_CONFIG_CNTL, 0, 0, 0}, + {R_00913C_SPI_CONFIG_CNTL_1, 0, 0, 0}, }; static const struct r600_reg evergreen_ctl_const_list[] = { - {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, - {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, + {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, + {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, }; static const struct r600_reg evergreen_context_reg_list[] = { - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028000_DB_RENDER_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028004_DB_COUNT_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028008_DB_DEPTH_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028044_DB_STENCIL_INFO, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028058_DB_DEPTH_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02805C_DB_DEPTH_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285BC_PA_CL_UCP0_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C0_PA_CL_UCP0_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C4_PA_CL_UCP0_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C8_PA_CL_UCP0_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285CC_PA_CL_UCP1_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D0_PA_CL_UCP1_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D4_PA_CL_UCP1_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D8_PA_CL_UCP1_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285DC_PA_CL_UCP2_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E0_PA_CL_UCP2_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E4_PA_CL_UCP2_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E8_PA_CL_UCP2_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285EC_PA_CL_UCP3_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F0_PA_CL_UCP3_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F4_PA_CL_UCP3_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F8_PA_CL_UCP3_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285FC_PA_CL_UCP4_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028600_PA_CL_UCP4_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028604_PA_CL_UCP4_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028608_PA_CL_UCP4_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02860C_PA_CL_UCP5_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028610_PA_CL_UCP5_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028614_PA_CL_UCP5_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028618_PA_CL_UCP5_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_5, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_6, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_7, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028640_SPI_VS_OUT_ID_9, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E0_SPI_BARYC_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028ABC_DB_HTILE_SURFACE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C3C_PA_SC_AA_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C64_CB_COLOR0_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C68_CB_COLOR0_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C6C_CB_COLOR0_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C78_CB_COLOR0_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA0_CB_COLOR1_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA4_CB_COLOR1_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA8_CB_COLOR1_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CB4_CB_COLOR1_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CDC_CB_COLOR2_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE0_CB_COLOR2_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE4_CB_COLOR2_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CF0_CB_COLOR2_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D18_CB_COLOR3_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D1C_CB_COLOR3_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D20_CB_COLOR3_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D2C_CB_COLOR3_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D54_CB_COLOR4_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D58_CB_COLOR4_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D5C_CB_COLOR4_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D68_CB_COLOR4_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D90_CB_COLOR5_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D94_CB_COLOR5_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D98_CB_COLOR5_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DA4_CB_COLOR5_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DCC_CB_COLOR6_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD0_CB_COLOR6_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD4_CB_COLOR6_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DE0_CB_COLOR6_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E08_CB_COLOR7_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E0C_CB_COLOR7_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E10_CB_COLOR7_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E1C_CB_COLOR7_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E44_CB_COLOR8_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E48_CB_COLOR8_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E4C_CB_COLOR8_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E58_CB_COLOR8_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E60_CB_COLOR9_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E64_CB_COLOR9_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E68_CB_COLOR9_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E74_CB_COLOR9_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E7C_CB_COLOR10_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E80_CB_COLOR10_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E84_CB_COLOR10_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E90_CB_COLOR10_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E98_CB_COLOR11_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E9C_CB_COLOR11_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA0_CB_COLOR11_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EAC_CB_COLOR11_DIM, 0, 0, 0}, + {R_028000_DB_RENDER_CONTROL, 0, 0, 0}, + {R_028004_DB_COUNT_CONTROL, 0, 0, 0}, + {R_028008_DB_DEPTH_VIEW, 0, 0, 0}, + {R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0}, + {R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, + {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, + {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, + {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028044_DB_STENCIL_INFO, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028058_DB_DEPTH_SIZE, 0, 0, 0}, + {R_02805C_DB_DEPTH_SLICE, 0, 0, 0}, + {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, + {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, + {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, + {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, + {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, + {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, + {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, + {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, + {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, + {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, + {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, + {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, + {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, + {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, + {R_028230_PA_SC_EDGERULE, 0, 0, 0}, + {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0}, + {R_028238_CB_TARGET_MASK, 0, 0, 0}, + {R_02823C_CB_SHADER_MASK, 0, 0, 0}, + {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, + {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, + {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, + {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, + {R_028350_SX_MISC, 0, 0, 0}, + {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, + {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, + {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, + {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, + {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, + {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, + {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, + {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, + {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, + {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, + {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, + {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, + {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, + {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, + {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, + {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, + {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, + {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, + {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, + {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, + {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, + {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, + {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, + {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, + {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, + {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, + {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, + {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, + {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, + {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, + {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, + {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, + {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, + {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, + {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, + {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, + {R_028408_VGT_INDX_OFFSET, 0, 0, 0}, + {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, + {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, + {R_028414_CB_BLEND_RED, 0, 0, 0}, + {R_028418_CB_BLEND_GREEN, 0, 0, 0}, + {R_02841C_CB_BLEND_BLUE, 0, 0, 0}, + {R_028420_CB_BLEND_ALPHA, 0, 0, 0}, + {R_028430_DB_STENCILREFMASK, 0, 0, 0}, + {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, + {R_028438_SX_ALPHA_REF, 0, 0, 0}, + {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, + {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, + {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, + {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, + {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, + {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, + {R_0285BC_PA_CL_UCP0_X, 0, 0, 0}, + {R_0285C0_PA_CL_UCP0_Y, 0, 0, 0}, + {R_0285C4_PA_CL_UCP0_Z, 0, 0, 0}, + {R_0285C8_PA_CL_UCP0_W, 0, 0, 0}, + {R_0285CC_PA_CL_UCP1_X, 0, 0, 0}, + {R_0285D0_PA_CL_UCP1_Y, 0, 0, 0}, + {R_0285D4_PA_CL_UCP1_Z, 0, 0, 0}, + {R_0285D8_PA_CL_UCP1_W, 0, 0, 0}, + {R_0285DC_PA_CL_UCP2_X, 0, 0, 0}, + {R_0285E0_PA_CL_UCP2_Y, 0, 0, 0}, + {R_0285E4_PA_CL_UCP2_Z, 0, 0, 0}, + {R_0285E8_PA_CL_UCP2_W, 0, 0, 0}, + {R_0285EC_PA_CL_UCP3_X, 0, 0, 0}, + {R_0285F0_PA_CL_UCP3_Y, 0, 0, 0}, + {R_0285F4_PA_CL_UCP3_Z, 0, 0, 0}, + {R_0285F8_PA_CL_UCP3_W, 0, 0, 0}, + {R_0285FC_PA_CL_UCP4_X, 0, 0, 0}, + {R_028600_PA_CL_UCP4_Y, 0, 0, 0}, + {R_028604_PA_CL_UCP4_Z, 0, 0, 0}, + {R_028608_PA_CL_UCP4_W, 0, 0, 0}, + {R_02860C_PA_CL_UCP5_X, 0, 0, 0}, + {R_028610_PA_CL_UCP5_Y, 0, 0, 0}, + {R_028614_PA_CL_UCP5_Z, 0, 0, 0}, + {R_028618_PA_CL_UCP5_W, 0, 0, 0}, + {R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0}, + {R_028620_SPI_VS_OUT_ID_1, 0, 0, 0}, + {R_028624_SPI_VS_OUT_ID_2, 0, 0, 0}, + {R_028628_SPI_VS_OUT_ID_3, 0, 0, 0}, + {R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0}, + {R_028630_SPI_VS_OUT_ID_5, 0, 0, 0}, + {R_028634_SPI_VS_OUT_ID_6, 0, 0, 0}, + {R_028638_SPI_VS_OUT_ID_7, 0, 0, 0}, + {R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0}, + {R_028640_SPI_VS_OUT_ID_9, 0, 0, 0}, + {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, + {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, + {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, + {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, + {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, + {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, + {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, + {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, + {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, + {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, + {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, + {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, + {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, + {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, + {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, + {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, + {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, + {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, + {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, + {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, + {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, + {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, + {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, + {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, + {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, + {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, + {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, + {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, + {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, + {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, + {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, + {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, + {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, + {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, + {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, + {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, + {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, + {R_0286D8_SPI_INPUT_Z, 0, 0, 0}, + {R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, + {R_0286E0_SPI_BARYC_CNTL, 0, 0, 0}, + {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0}, + {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0}, + {R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, + {R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, + {R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, + {R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, + {R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, + {R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, + {R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, + {R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, + {R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, + {R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, + {R_028808_CB_COLOR_CONTROL, 0, 0, 0}, + {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, + {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, + {R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, + {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, + {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, + {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0}, + {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0}, + {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0}, + {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0}, + {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0}, + {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0}, + {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0}, + {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0}, + {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, + {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, + {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, + {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0}, + {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0}, + {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0}, + {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, + {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, + {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, + {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, + {R_028A14_VGT_HOS_CNTL, 0, 0, 0}, + {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, + {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, + {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, + {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, + {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, + {R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, + {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, + {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, + {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, + {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, + {R_028A40_VGT_GS_MODE, 0, 0, 0}, + {R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0}, + {R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0}, + {R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, + {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, + {R_028ABC_DB_HTILE_SURFACE, 0, 0, 0}, + {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0}, + {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, + {R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0}, + {R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0}, + {R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0}, + {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, + {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, + {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, + {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, + {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, + {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, + {R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0}, + {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0}, + {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, + {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, + {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, + {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, + {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, + {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, + {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, + {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, + {R_028C3C_PA_SC_AA_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028C64_CB_COLOR0_PITCH, 0, 0, 0}, + {R_028C68_CB_COLOR0_SLICE, 0, 0, 0}, + {R_028C6C_CB_COLOR0_VIEW, 0, 0, 0}, + {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028C78_CB_COLOR0_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028CA0_CB_COLOR1_PITCH, 0, 0, 0}, + {R_028CA4_CB_COLOR1_SLICE, 0, 0, 0}, + {R_028CA8_CB_COLOR1_VIEW, 0, 0, 0}, + {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028CB4_CB_COLOR1_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028CDC_CB_COLOR2_PITCH, 0, 0, 0}, + {R_028CE0_CB_COLOR2_SLICE, 0, 0, 0}, + {R_028CE4_CB_COLOR2_VIEW, 0, 0, 0}, + {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028CF0_CB_COLOR2_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028D18_CB_COLOR3_PITCH, 0, 0, 0}, + {R_028D1C_CB_COLOR3_SLICE, 0, 0, 0}, + {R_028D20_CB_COLOR3_VIEW, 0, 0, 0}, + {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028D2C_CB_COLOR3_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028D54_CB_COLOR4_PITCH, 0, 0, 0}, + {R_028D58_CB_COLOR4_SLICE, 0, 0, 0}, + {R_028D5C_CB_COLOR4_VIEW, 0, 0, 0}, + {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028D68_CB_COLOR4_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028D90_CB_COLOR5_PITCH, 0, 0, 0}, + {R_028D94_CB_COLOR5_SLICE, 0, 0, 0}, + {R_028D98_CB_COLOR5_VIEW, 0, 0, 0}, + {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028DA4_CB_COLOR5_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028DCC_CB_COLOR6_PITCH, 0, 0, 0}, + {R_028DD0_CB_COLOR6_SLICE, 0, 0, 0}, + {R_028DD4_CB_COLOR6_VIEW, 0, 0, 0}, + {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028DE0_CB_COLOR6_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028E08_CB_COLOR7_PITCH, 0, 0, 0}, + {R_028E0C_CB_COLOR7_SLICE, 0, 0, 0}, + {R_028E10_CB_COLOR7_VIEW, 0, 0, 0}, + {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028E1C_CB_COLOR7_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028E44_CB_COLOR8_PITCH, 0, 0, 0}, + {R_028E48_CB_COLOR8_SLICE, 0, 0, 0}, + {R_028E4C_CB_COLOR8_VIEW, 0, 0, 0}, + {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028E58_CB_COLOR8_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028E60_CB_COLOR9_PITCH, 0, 0, 0}, + {R_028E64_CB_COLOR9_SLICE, 0, 0, 0}, + {R_028E68_CB_COLOR9_VIEW, 0, 0, 0}, + {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028E74_CB_COLOR9_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028E7C_CB_COLOR10_PITCH, 0, 0, 0}, + {R_028E80_CB_COLOR10_SLICE, 0, 0, 0}, + {R_028E84_CB_COLOR10_VIEW, 0, 0, 0}, + {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028E90_CB_COLOR10_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028E98_CB_COLOR11_PITCH, 0, 0, 0}, + {R_028E9C_CB_COLOR11_SLICE, 0, 0, 0}, + {R_028EA0_CB_COLOR11_VIEW, 0, 0, 0}, + {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028EAC_CB_COLOR11_DIM, 0, 0, 0}, }; /* SHADER RESOURCE R600/R700 */ static int evergreen_state_resource_init(struct r600_context *ctx, u32 offset) { struct r600_reg r600_shader_resource[] = { - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030000_RESOURCE0_WORD0, 0, 0, 0}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030004_RESOURCE0_WORD1, 0, 0, 0}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_03000C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030010_RESOURCE0_WORD4, 0, 0, 0}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030014_RESOURCE0_WORD5, 0, 0, 0}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030018_RESOURCE0_WORD6, 0, 0, 0}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_03001C_RESOURCE0_WORD7, 0, 0, 0}, + {R_030000_RESOURCE0_WORD0, 0, 0, 0}, + {R_030004_RESOURCE0_WORD1, 0, 0, 0}, + {R_030008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {R_03000C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {R_030010_RESOURCE0_WORD4, 0, 0, 0}, + {R_030014_RESOURCE0_WORD5, 0, 0, 0}, + {R_030018_RESOURCE0_WORD6, 0, 0, 0}, + {R_03001C_RESOURCE0_WORD7, 0, 0, 0}, }; unsigned nreg = Elements(r600_shader_resource); for (int i = 0; i < nreg; i++) { r600_shader_resource[i].offset += offset; } - return r600_context_add_block(ctx, r600_shader_resource, nreg); + return r600_context_add_block(ctx, r600_shader_resource, nreg, PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET); } /* SHADER SAMPLER R600/R700 */ static int r600_state_sampler_init(struct r600_context *ctx, u32 offset) { struct r600_reg r600_shader_sampler[] = { - {PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, - {PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, - {PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, + {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, + {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, + {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, }; unsigned nreg = Elements(r600_shader_sampler); for (int i = 0; i < nreg; i++) { r600_shader_sampler[i].offset += offset; } - return r600_context_add_block(ctx, r600_shader_sampler, nreg); + return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET); } /* SHADER SAMPLER BORDER R600/R700 */ static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 offset, unsigned id) { struct r600_reg r600_shader_sampler_border[] = { - {PKT3_SET_CONFIG_REG, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, 0, R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, 0, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, 0, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, 0, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, + {R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0, 0}, + {R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, + {R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, + {R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, + {R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, }; unsigned nreg = Elements(r600_shader_sampler_border); unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C; @@ -478,7 +478,7 @@ static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 off r600_shader_sampler_border[i].offset -= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX; r600_shader_sampler_border[i].offset += fake_offset; } - r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg); + r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, 0); if (r) { return r; } @@ -496,13 +496,12 @@ static int evergreen_loop_const_init(struct r600_context *ctx, u32 offset) int i; for (i = 0; i < nreg; i++) { - r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST; - r600_loop_consts[i].offset_base = EVERGREEN_LOOP_CONST_OFFSET; r600_loop_consts[i].offset = EVERGREEN_LOOP_CONST_OFFSET + ((offset + i) * 4); r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS; r600_loop_consts[i].flush_flags = 0; + r600_loop_consts[i].flush_mask = 0; } - return r600_context_add_block(ctx, r600_loop_consts, nreg); + return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, EVERGREEN_LOOP_CONST_OFFSET); } int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon) @@ -513,29 +512,23 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon) ctx->radeon = radeon; LIST_INITHEAD(&ctx->query_list); - /* initialize hash */ - ctx->hash_size = 19; - ctx->hash_shift = 11; - for (int i = 0; i < 256; i++) { - ctx->range[i].start_offset = i << ctx->hash_shift; - ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1; - ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*)); - if (ctx->range[i].blocks == NULL) { - return -ENOMEM; - } + ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range)); + if (!ctx->range) { + r = -ENOMEM; + goto out_err; } /* add blocks */ r = r600_context_add_block(ctx, evergreen_config_reg_list, - Elements(evergreen_config_reg_list)); + Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET); if (r) goto out_err; r = r600_context_add_block(ctx, evergreen_context_reg_list, - Elements(evergreen_context_reg_list)); + Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET); if (r) goto out_err; r = r600_context_add_block(ctx, evergreen_ctl_const_list, - Elements(evergreen_ctl_const_list)); + Elements(evergreen_ctl_const_list), PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET); if (r) goto out_err; @@ -588,17 +581,9 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon) /* VS loop const */ evergreen_loop_const_init(ctx, 32); - /* setup block table */ - ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); - for (int i = 0, c = 0; i < 256; i++) { - for (int j = 0; j < (1 << ctx->hash_shift); j++) { - if (ctx->range[i].blocks[j]) { - assert(c < ctx->nblocks); - ctx->blocks[c++] = ctx->range[i].blocks[j]; - j += (ctx->range[i].blocks[j]->nreg << 2) - 1; - } - } - } + r = r600_setup_block_table(ctx); + if (r) + goto out_err; /* allocate cs variables */ ctx->nreloc = RADEON_CTX_MAX_PM4; diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c index 34ea2a6bacb..0618d2329e6 100644 --- a/src/gallium/winsys/r600/drm/r600_hw_context.c +++ b/src/gallium/winsys/r600/drm/r600_hw_context.c @@ -66,7 +66,8 @@ static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsig } } -int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg) +int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg, + unsigned opcode, unsigned offset_base) { struct r600_block *block; struct r600_range *range; @@ -102,14 +103,20 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, ctx->nblocks++; for (int j = 0; j < n; j++) { range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)]; + /* create block table if it doesn't exist */ + if (!range->blocks) + range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *)); + if (!range->blocks) + return -1; + range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block; } /* initialize block */ block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */ block->start_offset = reg[i].offset; - block->pm4[block->pm4_ndwords++] = PKT3(reg[i].opcode, n, 0); - block->pm4[block->pm4_ndwords++] = (block->start_offset - reg[i].offset_base) >> 2; + block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0); + block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2; block->reg = &block->pm4[block->pm4_ndwords]; block->pm4_ndwords += n; block->nreg = n; @@ -155,427 +162,427 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, /* R600/R700 configuration */ static const struct r600_reg r600_config_reg_list[] = { - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009508_TA_CNTL_AUX, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009714_VC_ENHANCE, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009830_DB_DEBUG, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0, 0}, + {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, + {R_008C00_SQ_CONFIG, 0, 0, 0}, + {R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0}, + {R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0}, + {R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0}, + {R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0}, + {R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0}, + {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0}, + {R_009508_TA_CNTL_AUX, 0, 0, 0}, + {R_009714_VC_ENHANCE, 0, 0, 0}, + {R_009830_DB_DEBUG, 0, 0, 0}, + {R_009838_DB_WATERMARKS, 0, 0, 0}, }; static const struct r600_reg r600_ctl_const_list[] = { - {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, - {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, + {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, + {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, }; static const struct r600_reg r600_context_reg_list[] = { - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB0_VGT_STRMOUT_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028060_CB_COLOR0_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028080_CB_COLOR0_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028100_CB_COLOR0_MASK, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028064_CB_COLOR1_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028084_CB_COLOR1_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028104_CB_COLOR1_MASK, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028068_CB_COLOR2_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028088_CB_COLOR2_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028108_CB_COLOR2_MASK, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02806C_CB_COLOR3_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02808C_CB_COLOR3_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02810C_CB_COLOR3_MASK, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028070_CB_COLOR4_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028090_CB_COLOR4_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028110_CB_COLOR4_MASK, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028074_CB_COLOR5_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028094_CB_COLOR5_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028114_CB_COLOR5_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028078_CB_COLOR6_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028098_CB_COLOR6_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028118_CB_COLOR6_MASK, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02807C_CB_COLOR7_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02809C_CB_COLOR7_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02811C_CB_COLOR7_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028120_CB_CLEAR_RED, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028124_CB_CLEAR_GREEN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028128_CB_CLEAR_BLUE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02812C_CB_CLEAR_ALPHA, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028424_CB_FOG_RED, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028428_CB_FOG_GREEN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02842C_CB_FOG_BLUE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0287A0_CB_SHADER_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028804_CB_BLEND_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C34_CB_CLRCMP_SRC, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C38_CB_CLRCMP_DST, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C3C_CB_CLRCMP_MSK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C48_PA_SC_AA_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028000_DB_DEPTH_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028004_DB_DEPTH_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D0C_DB_RENDER_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D24_DB_HTILE_SURFACE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E20_PA_CL_UCP0_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E24_PA_CL_UCP0_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E28_PA_CL_UCP0_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E2C_PA_CL_UCP0_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E30_PA_CL_UCP1_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E34_PA_CL_UCP1_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E38_PA_CL_UCP1_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E3C_PA_CL_UCP1_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E40_PA_CL_UCP2_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E44_PA_CL_UCP2_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E48_PA_CL_UCP2_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E4C_PA_CL_UCP2_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E50_PA_CL_UCP3_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E54_PA_CL_UCP3_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E58_PA_CL_UCP3_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E5C_PA_CL_UCP3_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E60_PA_CL_UCP4_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E64_PA_CL_UCP4_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E68_PA_CL_UCP4_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E6C_PA_CL_UCP4_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E70_PA_CL_UCP5_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E74_PA_CL_UCP5_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E78_PA_CL_UCP5_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E7C_PA_CL_UCP5_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028614_SPI_VS_OUT_ID_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028618_SPI_VS_OUT_ID_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_4, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_5, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_7, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_8, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_9, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0}, + {R_028350_SX_MISC, 0, 0, 0}, + {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, + {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, + {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, + {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0}, + {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0}, + {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, + {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, + {R_028A14_VGT_HOS_CNTL, 0, 0, 0}, + {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, + {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, + {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, + {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, + {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, + {R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, + {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, + {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, + {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, + {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, + {R_028A40_VGT_GS_MODE, 0, 0, 0}, + {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0}, + {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0}, + {R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, + {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, + {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0}, + {R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, + {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028060_CB_COLOR0_SIZE, 0, 0, 0}, + {R_028080_CB_COLOR0_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_028100_CB_COLOR0_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028064_CB_COLOR1_SIZE, 0, 0, 0}, + {R_028084_CB_COLOR1_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_028104_CB_COLOR1_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028068_CB_COLOR2_SIZE, 0, 0, 0}, + {R_028088_CB_COLOR2_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_028108_CB_COLOR2_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_02806C_CB_COLOR3_SIZE, 0, 0, 0}, + {R_02808C_CB_COLOR3_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_02810C_CB_COLOR3_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028070_CB_COLOR4_SIZE, 0, 0, 0}, + {R_028090_CB_COLOR4_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_028110_CB_COLOR4_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028074_CB_COLOR5_SIZE, 0, 0, 0}, + {R_028094_CB_COLOR5_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_028114_CB_COLOR5_MASK, 0, 0, 0}, + {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0}, + {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028078_CB_COLOR6_SIZE, 0, 0, 0}, + {R_028098_CB_COLOR6_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_028118_CB_COLOR6_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_02807C_CB_COLOR7_SIZE, 0, 0, 0}, + {R_02809C_CB_COLOR7_VIEW, 0, 0, 0}, + {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_02811C_CB_COLOR7_MASK, 0, 0, 0}, + {R_028120_CB_CLEAR_RED, 0, 0, 0}, + {R_028124_CB_CLEAR_GREEN, 0, 0, 0}, + {R_028128_CB_CLEAR_BLUE, 0, 0, 0}, + {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0}, + {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, + {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, + {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_02823C_CB_SHADER_MASK, 0, 0, 0}, + {R_028238_CB_TARGET_MASK, 0, 0, 0}, + {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, + {R_028414_CB_BLEND_RED, 0, 0, 0}, + {R_028418_CB_BLEND_GREEN, 0, 0, 0}, + {R_02841C_CB_BLEND_BLUE, 0, 0, 0}, + {R_028420_CB_BLEND_ALPHA, 0, 0, 0}, + {R_028424_CB_FOG_RED, 0, 0, 0}, + {R_028428_CB_FOG_GREEN, 0, 0, 0}, + {R_02842C_CB_FOG_BLUE, 0, 0, 0}, + {R_028430_DB_STENCILREFMASK, 0, 0, 0}, + {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, + {R_028438_SX_ALPHA_REF, 0, 0, 0}, + {R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, + {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0}, + {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0}, + {R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, + {R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, + {R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, + {R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, + {R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, + {R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, + {R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, + {R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, + {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0}, + {R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, + {R_028804_CB_BLEND_CONTROL, 0, 0, 0}, + {R_028808_CB_COLOR_CONTROL, 0, 0, 0}, + {R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, + {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, + {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, + {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0}, + {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0}, + {R_028C34_CB_CLRCMP_SRC, 0, 0, 0}, + {R_028C38_CB_CLRCMP_DST, 0, 0, 0}, + {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0}, + {R_028C48_PA_SC_AA_MASK, 0, 0, 0}, + {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, + {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0}, + {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0}, + {R_028000_DB_DEPTH_SIZE, 0, 0, 0}, + {R_028004_DB_DEPTH_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0}, + {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0}, + {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0}, + {R_028D24_DB_HTILE_SURFACE, 0, 0, 0}, + {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0}, + {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0}, + {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, + {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, + {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, + {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, + {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, + {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, + {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, + {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, + {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, + {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, + {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, + {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, + {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, + {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, + {R_028230_PA_SC_EDGERULE, 0, 0, 0}, + {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, + {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, + {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, + {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, + {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, + {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, + {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, + {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, + {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, + {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, + {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, + {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, + {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, + {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, + {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, + {R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, + {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, + {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, + {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, + {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, + {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, + {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0}, + {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0}, + {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, + {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, + {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, + {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, + {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, + {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, + {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, + {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, + {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, + {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, + {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, + {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, + {R_028E20_PA_CL_UCP0_X, 0, 0, 0}, + {R_028E24_PA_CL_UCP0_Y, 0, 0, 0}, + {R_028E28_PA_CL_UCP0_Z, 0, 0, 0}, + {R_028E2C_PA_CL_UCP0_W, 0, 0, 0}, + {R_028E30_PA_CL_UCP1_X, 0, 0, 0}, + {R_028E34_PA_CL_UCP1_Y, 0, 0, 0}, + {R_028E38_PA_CL_UCP1_Z, 0, 0, 0}, + {R_028E3C_PA_CL_UCP1_W, 0, 0, 0}, + {R_028E40_PA_CL_UCP2_X, 0, 0, 0}, + {R_028E44_PA_CL_UCP2_Y, 0, 0, 0}, + {R_028E48_PA_CL_UCP2_Z, 0, 0, 0}, + {R_028E4C_PA_CL_UCP2_W, 0, 0, 0}, + {R_028E50_PA_CL_UCP3_X, 0, 0, 0}, + {R_028E54_PA_CL_UCP3_Y, 0, 0, 0}, + {R_028E58_PA_CL_UCP3_Z, 0, 0, 0}, + {R_028E5C_PA_CL_UCP3_W, 0, 0, 0}, + {R_028E60_PA_CL_UCP4_X, 0, 0, 0}, + {R_028E64_PA_CL_UCP4_Y, 0, 0, 0}, + {R_028E68_PA_CL_UCP4_Z, 0, 0, 0}, + {R_028E6C_PA_CL_UCP4_W, 0, 0, 0}, + {R_028E70_PA_CL_UCP5_X, 0, 0, 0}, + {R_028E74_PA_CL_UCP5_Y, 0, 0, 0}, + {R_028E78_PA_CL_UCP5_Z, 0, 0, 0}, + {R_028E7C_PA_CL_UCP5_W, 0, 0, 0}, + {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, + {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, + {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, + {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, + {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, + {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, + {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, + {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, + {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, + {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, + {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, + {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, + {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, + {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, + {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, + {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, + {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, + {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, + {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, + {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, + {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, + {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, + {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, + {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, + {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, + {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, + {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, + {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, + {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, + {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, + {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, + {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, + {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0}, + {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0}, + {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0}, + {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0}, + {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0}, + {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0}, + {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0}, + {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0}, + {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0}, + {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0}, + {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0}, + {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0}, + {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0}, + {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, + {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, + {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, + {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, + {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, + {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, + {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, + {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, + {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, + {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, + {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, + {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, + {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, + {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, + {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, + {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, + {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, + {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, + {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, + {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, + {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, + {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, + {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, + {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, + {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, + {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, + {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, + {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, + {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, + {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, + {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, + {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, + {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, + {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, + {R_0286D8_SPI_INPUT_Z, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0}, + {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0}, + {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0}, + {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, + {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, + {R_028408_VGT_INDX_OFFSET, 0, 0, 0}, + {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, + {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0}, + {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0}, + {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0}, + {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0}, }; /* SHADER RESOURCE R600/R700 */ static int r600_state_resource_init(struct r600_context *ctx, u32 offset) { struct r600_reg r600_shader_resource[] = { - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038000_RESOURCE0_WORD0, 0, 0, 0}, - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038004_RESOURCE0_WORD1, 0, 0, 0}, - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_03800C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038010_RESOURCE0_WORD4, 0, 0, 0}, - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038014_RESOURCE0_WORD5, 0, 0, 0}, - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038018_RESOURCE0_WORD6, 0, 0, 0}, + {R_038000_RESOURCE0_WORD0, 0, 0, 0}, + {R_038004_RESOURCE0_WORD1, 0, 0, 0}, + {R_038008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {R_03800C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {R_038010_RESOURCE0_WORD4, 0, 0, 0}, + {R_038014_RESOURCE0_WORD5, 0, 0, 0}, + {R_038018_RESOURCE0_WORD6, 0, 0, 0}, }; unsigned nreg = Elements(r600_shader_resource); for (int i = 0; i < nreg; i++) { r600_shader_resource[i].offset += offset; } - return r600_context_add_block(ctx, r600_shader_resource, nreg); + return r600_context_add_block(ctx, r600_shader_resource, nreg, PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET); } /* SHADER SAMPLER R600/R700 */ static int r600_state_sampler_init(struct r600_context *ctx, u32 offset) { struct r600_reg r600_shader_sampler[] = { - {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, - {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, - {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, + {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, + {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, + {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, }; unsigned nreg = Elements(r600_shader_sampler); for (int i = 0; i < nreg; i++) { r600_shader_sampler[i].offset += offset; } - return r600_context_add_block(ctx, r600_shader_sampler, nreg); + return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET); } /* SHADER SAMPLER BORDER R600/R700 */ static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset) { struct r600_reg r600_shader_sampler_border[] = { - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, + {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, + {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, + {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, + {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, }; unsigned nreg = Elements(r600_shader_sampler_border); for (int i = 0; i < nreg; i++) { r600_shader_sampler_border[i].offset += offset; } - return r600_context_add_block(ctx, r600_shader_sampler_border, nreg); + return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET); } static int r600_loop_const_init(struct r600_context *ctx, u32 offset) @@ -585,14 +592,12 @@ static int r600_loop_const_init(struct r600_context *ctx, u32 offset) int i; for (i = 0; i < nreg; i++) { - r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST; - r600_loop_consts[i].offset_base = R600_LOOP_CONST_OFFSET; r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4); r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS; r600_loop_consts[i].flush_flags = 0; r600_loop_consts[i].flush_mask = 0; } - return r600_context_add_block(ctx, r600_loop_consts, nreg); + return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET); } static void r600_context_clear_fenced_bo(struct r600_context *ctx) @@ -612,8 +617,10 @@ void r600_context_fini(struct r600_context *ctx) struct r600_block *block; struct r600_range *range; - for (int i = 0; i < 256; i++) { - for (int j = 0; j < (1 << ctx->hash_shift); j++) { + for (int i = 0; i < NUM_RANGES; i++) { + if (!ctx->range[i].blocks) + continue; + for (int j = 0; j < (1 << HASH_SHIFT); j++) { block = ctx->range[i].blocks[j]; if (block) { for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) { @@ -628,6 +635,7 @@ void r600_context_fini(struct r600_context *ctx) } free(ctx->range[i].blocks); } + free(ctx->range); free(ctx->blocks); free(ctx->reloc); free(ctx->bo); @@ -637,6 +645,36 @@ void r600_context_fini(struct r600_context *ctx) memset(ctx, 0, sizeof(struct r600_context)); } +int r600_setup_block_table(struct r600_context *ctx) +{ + /* setup block table */ + ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); + if (!ctx->blocks) + return -ENOMEM; + for (int i = 0, c = 0; i < NUM_RANGES; i++) { + if (!ctx->range[i].blocks) + continue; + for (int j = 0, add; j < (1 << HASH_SHIFT); j++) { + if (!ctx->range[i].blocks[j]) + continue; + + add = 1; + for (int k = 0; k < c; k++) { + if (ctx->blocks[k] == ctx->range[i].blocks[j]) { + add = 0; + break; + } + } + if (add) { + assert(c < ctx->nblocks); + ctx->blocks[c++] = ctx->range[i].blocks[j]; + j += (ctx->range[i].blocks[j]->nreg) - 1; + } + } + } + return 0; +} + int r600_context_init(struct r600_context *ctx, struct radeon *radeon) { int r; @@ -645,30 +683,23 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon) ctx->radeon = radeon; LIST_INITHEAD(&ctx->query_list); - /* initialize hash */ - ctx->hash_size = 19; - ctx->hash_shift = 11; - for (int i = 0; i < 256; i++) { - ctx->range[i].start_offset = i << ctx->hash_shift; - ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1; - ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*)); - if (ctx->range[i].blocks == NULL) { - r = -ENOMEM; - goto out_err; - } + ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range)); + if (!ctx->range) { + r = -ENOMEM; + goto out_err; } /* add blocks */ r = r600_context_add_block(ctx, r600_config_reg_list, - Elements(r600_config_reg_list)); + Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET); if (r) goto out_err; r = r600_context_add_block(ctx, r600_context_reg_list, - Elements(r600_context_reg_list)); + Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET); if (r) goto out_err; r = r600_context_add_block(ctx, r600_ctl_const_list, - Elements(r600_ctl_const_list)); + Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET); if (r) goto out_err; @@ -721,26 +752,9 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon) /* VS loop const */ r600_loop_const_init(ctx, 32); - /* setup block table */ - ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); - for (int i = 0, c = 0; i < 256; i++) { - for (int j = 0, add; j < (1 << ctx->hash_shift); j++) { - if (ctx->range[i].blocks[j]) { - add = 1; - for (int k = 0; k < c; k++) { - if (ctx->blocks[k] == ctx->range[i].blocks[j]) { - add = 0; - break; - } - } - if (add) { - assert(c < ctx->nblocks); - ctx->blocks[c++] = ctx->range[i].blocks[j]; - j += (ctx->range[i].blocks[j]->nreg << 2) - 1; - } - } - } - } + r = r600_setup_block_table(ctx); + if (r) + goto out_err; /* allocate cs variables */ ctx->nreloc = RADEON_CTX_MAX_PM4; @@ -810,12 +824,17 @@ void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags, G_0085F0_DB_ACTION_ENA(flush_flags))) { if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) { /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */ - if (ctx->radeon->family == CHIP_RV670) { - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing); - ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */ - ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */ - ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */ - ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */ + if ((bo->binding & BO_BOUND_TEXTURE) && + (flush_flags & S_0085F0_CB_ACTION_ENA(1))) { + if ((ctx->radeon->family == CHIP_RV670) || + (ctx->radeon->family == CHIP_RS780) || + (ctx->radeon->family == CHIP_RS880)) { + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing); + ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */ + ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */ + ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */ + ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */ + } } ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, ctx->predicate_drawing); @@ -906,16 +925,17 @@ void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_stat int dirty; for (int i = 0; i < state->nregs; i++) { unsigned id, reloc_id; + struct r600_pipe_reg *reg = &state->regs[i]; - range = &ctx->range[CTX_RANGE_ID(ctx, state->regs[i].offset)]; - block = range->blocks[CTX_BLOCK_ID(ctx, state->regs[i].offset)]; - id = (state->regs[i].offset - block->start_offset) >> 2; + range = &ctx->range[CTX_RANGE_ID(ctx, reg->offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, reg->offset)]; + id = (reg->offset - block->start_offset) >> 2; dirty = block->status & R600_BLOCK_STATUS_DIRTY; new_val = block->reg[id]; - new_val &= ~state->regs[i].mask; - new_val |= state->regs[i].value; + new_val &= ~reg->mask; + new_val |= reg->value; if (new_val != block->reg[id]) { block->reg[id] = new_val; dirty |= R600_BLOCK_STATUS_DIRTY; @@ -925,8 +945,8 @@ void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_stat if (block->pm4_bo_index[id] && state->regs[i].bo) { /* find relocation */ reloc_id = block->pm4_bo_index[id]; - r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, state->regs[i].bo); - state->regs[i].bo->fence = ctx->radeon->fence; + r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, reg->bo); + reg->bo->fence = ctx->radeon->fence; /* always force dirty for relocs for now */ dirty |= R600_BLOCK_STATUS_DIRTY; } @@ -947,6 +967,9 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_ block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; if (state == NULL) { block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + if (block->reloc[1].bo) + block->reloc[1].bo->bo->binding &= ~BO_BOUND_TEXTURE; + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); LIST_DELINIT(&block->list); @@ -1000,6 +1023,7 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_ r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo); state->regs[2].bo->fence = ctx->radeon->fence; state->regs[3].bo->fence = ctx->radeon->fence; + state->regs[2].bo->bo->binding |= BO_BOUND_TEXTURE; } } r600_context_dirty_block(ctx, block, dirty, num_regs - 1); diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h index f8363f9272b..4f7e60c3413 100644 --- a/src/gallium/winsys/r600/drm/r600_priv.h +++ b/src/gallium/winsys/r600/drm/r600_priv.h @@ -67,14 +67,13 @@ struct radeon { #define REG_FLAG_RV6XX_SBU 4 struct r600_reg { - unsigned opcode; - unsigned offset_base; unsigned offset; unsigned flags; unsigned flush_flags; unsigned flush_mask; }; +#define BO_BOUND_TEXTURE 1 struct radeon_bo { struct pipe_reference reference; unsigned handle; @@ -90,6 +89,7 @@ struct radeon_bo { unsigned reloc_id; unsigned last_flush; unsigned name; + unsigned binding; }; struct r600_bo { @@ -145,6 +145,7 @@ int radeon_bo_get_tiling_flags(struct radeon *radeon, int radeon_bo_get_name(struct radeon *radeon, struct radeon_bo *bo, uint32_t *name); +int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo); /* * r600_hw_context.c @@ -154,12 +155,13 @@ void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *r void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags, unsigned flush_mask, struct r600_bo *rbo); struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset); -int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg); +int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg, + unsigned opcode, unsigned offset_base); void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset); void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block); void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block, int dirty, int index); - +int r600_setup_block_table(struct r600_context *ctx); void r600_context_reg(struct r600_context *ctx, unsigned offset, unsigned value, unsigned mask); @@ -184,14 +186,25 @@ struct r600_bo *r600_bomgr_bo_create(struct r600_bomgr *mgr, /* * helpers */ -#define CTX_RANGE_ID(ctx, offset) (((offset) >> (ctx)->hash_shift) & 255) -#define CTX_BLOCK_ID(ctx, offset) ((offset) & ((1 << (ctx)->hash_shift) - 1)) + +/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */ +/* there is a block entry for each register so 512 blocks */ +/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */ +/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/ +#define RANGE_OFFSET_START 0x8000 +#define HASH_SHIFT 9 +#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */ + +#define CTX_RANGE_ID(ctx, offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255) +#define CTX_BLOCK_ID(ctx, offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1)) /* * radeon_bo.c */ static inline int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo) { + if (bo->map_count == 0 && !bo->data) + return radeon_bo_fixed_map(radeon, bo); bo->map_count++; return 0; } diff --git a/src/gallium/winsys/r600/drm/radeon_bo.c b/src/gallium/winsys/r600/drm/radeon_bo.c index 13b1d50b6e5..cd817fc240b 100644 --- a/src/gallium/winsys/r600/drm/radeon_bo.c +++ b/src/gallium/winsys/r600/drm/radeon_bo.c @@ -33,7 +33,7 @@ #include "xf86drm.h" #include "radeon_drm.h" -static int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo) +int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo) { struct drm_radeon_gem_mmap args; void *ptr; @@ -64,8 +64,10 @@ static int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo) static void radeon_bo_fixed_unmap(struct radeon *radeon, struct radeon_bo *bo) { - munmap(bo->data, bo->size); - bo->data = NULL; + if (bo->data) { + munmap(bo->data, bo->size); + bo->data = NULL; + } } struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, @@ -127,11 +129,6 @@ struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, return NULL; } } - if (radeon_bo_fixed_map(radeon, bo)) { - R600_ERR("failed to map bo\n"); - radeon_bo_reference(radeon, &bo, NULL); - return bo; - } if (handle) util_hash_table_set(radeon->bo_handles, (void *)(uintptr_t)handle, bo); diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 37f6d18689d..3ac57d25b5e 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -48,22 +48,59 @@ #define RADEON_INFO_WANT_CMASK 8 #endif -/* Enable/disable feature access. Return TRUE on success. */ -static boolean radeon_set_fd_access(int fd, unsigned request, boolean enable) +/* Enable/disable feature access for one command stream. + * If enable == TRUE, return TRUE on success. + * Otherwise, return FALSE. + * + * We basically do the same thing kernel does, because we have to deal + * with multiple contexts (here command streams) backed by one winsys. */ +static boolean radeon_set_fd_access(struct radeon_drm_cs *applier, + struct radeon_drm_cs **owner, + pipe_mutex *mutex, + unsigned request, boolean enable) { struct drm_radeon_info info = {0}; unsigned value = enable ? 1 : 0; + pipe_mutex_lock(*mutex); + + /* Early exit if we are sure the request will fail. */ + if (enable) { + if (*owner) { + pipe_mutex_unlock(*mutex); + return FALSE; + } + } else { + if (*owner != applier) { + pipe_mutex_unlock(*mutex); + return FALSE; + } + } + + /* Pass through the request to the kernel. */ info.value = (unsigned long)&value; info.request = request; - - if (drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info)) != 0) + if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO, + &info, sizeof(info)) != 0) { + pipe_mutex_unlock(*mutex); return FALSE; + } - if (enable && !value) - return FALSE; + /* Update the rights in the winsys. */ + if (enable) { + if (value) { + *owner = applier; + fprintf(stderr, "radeon: Acquired Hyper-Z.\n"); + pipe_mutex_unlock(*mutex); + return TRUE; + } + } else { + *owner = NULL; + fprintf(stderr, "radeon: Released Hyper-Z.\n"); + } - return TRUE; + pipe_mutex_unlock(*mutex); + return FALSE; } /* Helper function to do the ioctls needed for setup and init. */ @@ -138,16 +175,6 @@ static void do_ioctls(struct radeon_drm_winsys *winsys) } winsys->z_pipes = target; - if (debug_get_bool_option("RADEON_HYPERZ", FALSE)) { - winsys->hyperz = radeon_set_fd_access(winsys->fd, - RADEON_INFO_WANT_HYPERZ, TRUE); - } - - if (debug_get_bool_option("RADEON_CMASK", FALSE)) { - winsys->aacompress = radeon_set_fd_access(winsys->fd, - RADEON_INFO_WANT_CMASK, TRUE); - } - retval = drmCommandWriteRead(winsys->fd, DRM_RADEON_GEM_INFO, &gem_info, sizeof(gem_info)); if (retval) { @@ -167,6 +194,9 @@ static void radeon_winsys_destroy(struct radeon_winsys *rws) { struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws; + pipe_mutex_destroy(ws->hyperz_owner_mutex); + pipe_mutex_destroy(ws->cmask_owner_mutex); + ws->cman->destroy(ws->cman); ws->kman->destroy(ws->kman); FREE(rws); @@ -198,14 +228,38 @@ static uint32_t radeon_get_value(struct radeon_winsys *rws, return ws->drm_major*100 + ws->drm_minor >= 206; case RADEON_VID_DRM_2_8_0: return ws->drm_major*100 + ws->drm_minor >= 208; - case RADEON_VID_CAN_HYPERZ: - return ws->hyperz; - case RADEON_VID_CAN_AACOMPRESS: - return ws->aacompress; } return 0; } +static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs, + enum radeon_feature_id fid, + boolean enable) +{ + struct radeon_drm_cs *cs = radeon_drm_cs(rcs); + + switch (fid) { + case RADEON_FID_HYPERZ_RAM_ACCESS: + if (debug_get_bool_option("RADEON_HYPERZ", FALSE)) { + return radeon_set_fd_access(cs, &cs->ws->hyperz_owner, + &cs->ws->hyperz_owner_mutex, + RADEON_INFO_WANT_HYPERZ, enable); + } else { + return FALSE; + } + + case RADEON_FID_CMASK_RAM_ACCESS: + if (debug_get_bool_option("RADEON_CMASK", FALSE)) { + return radeon_set_fd_access(cs, &cs->ws->cmask_owner, + &cs->ws->cmask_owner_mutex, + RADEON_INFO_WANT_CMASK, enable); + } else { + return FALSE; + } + } + return FALSE; +} + struct radeon_winsys *radeon_drm_winsys_create(int fd) { struct radeon_drm_winsys *ws = CALLOC_STRUCT(radeon_drm_winsys); @@ -231,10 +285,14 @@ struct radeon_winsys *radeon_drm_winsys_create(int fd) /* Set functions. */ ws->base.destroy = radeon_winsys_destroy; ws->base.get_value = radeon_get_value; + ws->base.cs_request_feature = radeon_cs_request_feature; radeon_bomgr_init_functions(ws); radeon_drm_cs_init_functions(ws); + pipe_mutex_init(ws->hyperz_owner_mutex); + pipe_mutex_init(ws->cmask_owner_mutex); + return &ws->base; fail: diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h index e1b9493fc10..d5186bc4d17 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h @@ -32,6 +32,8 @@ #include "radeon_winsys.h" +#include "os/os_thread.h" + struct radeon_drm_winsys { struct radeon_winsys base; @@ -52,10 +54,10 @@ struct radeon_drm_winsys { unsigned drm_minor; unsigned drm_patchlevel; - /* Hyper-Z user */ - boolean hyperz; - /* AA compression (CMask) */ - boolean aacompress; + struct radeon_drm_cs *hyperz_owner; + pipe_mutex hyperz_owner_mutex; + struct radeon_drm_cs *cmask_owner; + pipe_mutex cmask_owner_mutex; }; static INLINE struct radeon_drm_winsys * diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h index ca0e6624138..3a64e4abc35 100644 --- a/src/gallium/winsys/radeon/drm/radeon_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h @@ -87,9 +87,11 @@ enum radeon_value_id { * - TBD */ RADEON_VID_DRM_2_8_0, +}; - RADEON_VID_CAN_HYPERZ, /* ZMask + HiZ */ - RADEON_VID_CAN_AACOMPRESS, /* CMask */ +enum radeon_feature_id { + RADEON_FID_HYPERZ_RAM_ACCESS, /* ZMask + HiZ */ + RADEON_FID_CMASK_RAM_ACCESS, }; struct radeon_winsys { @@ -314,6 +316,16 @@ struct radeon_winsys { */ boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs, struct radeon_winsys_cs_handle *buf); + + /** + * Request access to a feature for a command stream. + * + * \param cs A command stream. + * \param fid A winsys buffer. + */ + boolean (*cs_request_feature)(struct radeon_winsys_cs *cs, + enum radeon_feature_id fid, + boolean enable); }; #endif diff --git a/src/gallium/winsys/svga/drm/vmw_screen_svga.c b/src/gallium/winsys/svga/drm/vmw_screen_svga.c index d96b2b97427..c362aa39938 100644 --- a/src/gallium/winsys/svga/drm/vmw_screen_svga.c +++ b/src/gallium/winsys/svga/drm/vmw_screen_svga.c @@ -201,6 +201,19 @@ vmw_svga_winsys_destroy(struct svga_winsys_screen *sws) } +static SVGA3dHardwareVersion +vmw_svga_winsys_get_hw_version(struct svga_winsys_screen *sws) +{ + struct vmw_winsys_screen *vws = vmw_winsys_screen(sws); + + if (!vws->ioctl.fifo_map) { + return 0; + } + + return vws->ioctl.fifo_map[SVGA_FIFO_3D_HWVERSION]; +} + + static boolean vmw_svga_winsys_get_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex index, @@ -276,6 +289,7 @@ boolean vmw_winsys_screen_init_svga(struct vmw_winsys_screen *vws) { vws->base.destroy = vmw_svga_winsys_destroy; + vws->base.get_hw_version = vmw_svga_winsys_get_hw_version; vws->base.get_cap = vmw_svga_winsys_get_cap; vws->base.context_create = vmw_svga_winsys_context_create; vws->base.surface_create = vmw_svga_winsys_surface_create; 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