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authorMarek Olšák <[email protected]>2019-07-02 21:40:49 -0400
committerMarek Olšák <[email protected]>2019-07-09 17:24:16 -0400
commit9d1483de3b89c4b05adb326c6b444ef9ed169243 (patch)
tree75b5a38d2002ebfa4de8de36b3267e524be4d781 /src/gallium/winsys
parent1d3bffaf9cb7ade0676bab969b5d33d6bdabcec8 (diff)
radeonsi/gfx10: enable 1D textures
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Acked-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/winsys')
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_surface.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 1dff1b3447e..4f410d5c88e 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -88,8 +88,10 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
config.info.storage_samples = tex->nr_storage_samples;
config.info.levels = tex->last_level + 1;
config.info.num_channels = util_format_get_nr_components(tex->format);
- config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
- config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
+ config.is_1d = tex->target == PIPE_TEXTURE_1D ||
+ tex->target == PIPE_TEXTURE_1D_ARRAY;
+ config.is_3d = tex->target == PIPE_TEXTURE_3D;
+ config.is_cube = tex->target == PIPE_TEXTURE_CUBE;
/* Use different surface counters for color and FMASK, so that MSAA MRTs
* always use consecutive surface indices when FMASK is allocated between