diff options
| author | James Zhu <[email protected]> | 2018-02-06 12:39:03 -0500 |
|---|---|---|
| committer | Leo Liu <[email protected]> | 2018-02-21 13:53:38 -0500 |
| commit | c6acae22c898687627e6871c337f1d48f90f1568 (patch) | |
| tree | 3b023e4455dbce68d9010a06b8d7d279fbde4999 /src/gallium/winsys | |
| parent | f0ad908e79c76c380102960a0d7727f55d1abce4 (diff) | |
winsys/amdgpu:add uvd hevc enc support in amdgpu cs
Support UVD HEVC encode in amdgpu cs
Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Boyuan Zhang <[email protected]>
Diffstat (limited to 'src/gallium/winsys')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 1927a3ad275..92d5394b121 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -376,6 +376,7 @@ static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs) { return cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD && cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCE && + cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD_ENC && cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_DEC && cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC; } @@ -818,6 +819,10 @@ static bool amdgpu_init_cs_context(struct amdgpu_cs_context *cs, cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD; break; + case RING_UVD_ENC: + cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD_ENC; + break; + case RING_VCE: cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCE; break; @@ -1533,6 +1538,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs, ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4; break; case RING_UVD: + case RING_UVD_ENC: while (rcs->current.cdw & 15) radeon_emit(rcs, 0x80000000); /* type2 nop packet */ break; |