diff options
| author | Keith Whitwell <[email protected]> | 2010-10-17 11:45:49 -0700 |
|---|---|---|
| committer | Keith Whitwell <[email protected]> | 2010-11-03 09:36:01 +0000 |
| commit | c3974dc837b4a11a30603bb00fa1d346e721af59 (patch) | |
| tree | fac5924eb1b1d003f6405f090bb6225b92f1cc8c /src/gallium/winsys | |
| parent | 7b120ceac8738b73dcffe4d39e3e32b473dea3cf (diff) | |
r600g: set hardware pixel centers according to gl_rasterization_rules
These were previously being left in the default (D3D) mode. This mean
that triangles were drawn slightly incorrectly, but also because this
state is relied on by the u_blitter code, all blits were half a pixel
off.
Diffstat (limited to 'src/gallium/winsys')
| -rw-r--r-- | src/gallium/winsys/r600/drm/r600_hw_context.c | 1 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/r600d.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c index 8b4521b86cd..bcbe71e1267 100644 --- a/src/gallium/winsys/r600/drm/r600_hw_context.c +++ b/src/gallium/winsys/r600/drm/r600_hw_context.c @@ -384,6 +384,7 @@ static const struct r600_reg r600_context_reg_list[] = { {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0}, {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0}, {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h index d91f7737af3..5ca7456e906 100644 --- a/src/gallium/winsys/r600/drm/r600d.h +++ b/src/gallium/winsys/r600/drm/r600d.h @@ -795,6 +795,7 @@ #define R_028A48_PA_SC_MPASS_PS_CNTL 0x028A48 #define R_028C00_PA_SC_LINE_CNTL 0x028C00 #define R_028C04_PA_SC_AA_CONFIG 0x028C04 +#define R_028C08_PA_SU_VTX_CNTL 0x028C08 #define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX 0x028C1C #define R_028C48_PA_SC_AA_MASK 0x028C48 #define R_028810_PA_CL_CLIP_CNTL 0x028810 |