diff options
| author | Christian König <[email protected]> | 2010-10-12 23:05:25 +0200 |
|---|---|---|
| committer | Christian König <[email protected]> | 2010-10-12 23:07:29 +0200 |
| commit | 695cc370a280a637f411f5ff3877b3fd1c05e424 (patch) | |
| tree | 69ae2a8fbecfa553faba59274688ffe11ee1a612 /src/gallium/winsys | |
| parent | f3e34ba6fba76870b1c91a27adb706d1b87aeec8 (diff) | |
| parent | 48156b87bc9d3e09ec34372d69504a787332ea0b (diff) | |
Merge branch 'master' of ssh://git.freedesktop.org/git/mesa/mesa into pipe-video
Conflicts:
configure.ac
src/gallium/drivers/nvfx/Makefile
src/gallium/include/pipe/p_defines.h
src/gallium/include/pipe/p_screen.h
src/gallium/include/state_tracker/dri1_api.h
src/gallium/include/state_tracker/drm_api.h
src/gallium/winsys/nouveau/drm/nouveau_drm_api.c
Diffstat (limited to 'src/gallium/winsys')
67 files changed, 7949 insertions, 905 deletions
diff --git a/src/gallium/winsys/SConscript b/src/gallium/winsys/SConscript index 2013ee97c1c..65b12287df7 100644 --- a/src/gallium/winsys/SConscript +++ b/src/gallium/winsys/SConscript @@ -1,5 +1,10 @@ Import('*') + +SConscript([ + 'sw/wrapper/SConscript', +]) + if 'xlib' in env['winsys']: SConscript([ 'sw/xlib/SConscript', @@ -34,3 +39,8 @@ if env['dri']: SConscript([ 'radeon/drm/SConscript', ]) + + if 'r600' in env['winsys']: + SConscript([ + 'r600/drm/SConscript', + ]) diff --git a/src/gallium/winsys/g3dvl/dri/XF86dri.c b/src/gallium/winsys/g3dvl/dri/XF86dri.c index 9e359a92384..831a7603396 100644 --- a/src/gallium/winsys/g3dvl/dri/XF86dri.c +++ b/src/gallium/winsys/g3dvl/dri/XF86dri.c @@ -36,7 +36,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* THIS IS NOT AN X CONSORTIUM STANDARD */ -#define NEED_REPLIES #include <X11/Xlibint.h> #include <X11/extensions/Xext.h> #include <X11/extensions/extutil.h> diff --git a/src/gallium/winsys/i915/drm/Makefile b/src/gallium/winsys/i915/drm/Makefile index a67b9e8a528..1977de1fb09 100644 --- a/src/gallium/winsys/i915/drm/Makefile +++ b/src/gallium/winsys/i915/drm/Makefile @@ -7,7 +7,7 @@ C_SOURCES = \ i915_drm_batchbuffer.c \ i915_drm_buffer.c \ i915_drm_fence.c \ - i915_drm_api.c + i915_drm_winsys.c LIBRARY_INCLUDES = $(shell pkg-config libdrm --cflags-only-I) diff --git a/src/gallium/winsys/i915/drm/SConscript b/src/gallium/winsys/i915/drm/SConscript index 96ca707e35f..d8f5885b62c 100644 --- a/src/gallium/winsys/i915/drm/SConscript +++ b/src/gallium/winsys/i915/drm/SConscript @@ -5,10 +5,10 @@ env = env.Clone() env.ParseConfig('pkg-config --cflags libdrm') i915drm_sources = [ - 'i915_drm_api.c', 'i915_drm_batchbuffer.c', 'i915_drm_buffer.c', 'i915_drm_fence.c', + 'i915_drm_winsys.c', ] i915drm = env.ConvenienceLibrary( diff --git a/src/gallium/winsys/i915/drm/i915_drm_batchbuffer.c b/src/gallium/winsys/i915/drm/i915_drm_batchbuffer.c index 102f59dc541..e50e7801c0a 100644 --- a/src/gallium/winsys/i915/drm/i915_drm_batchbuffer.c +++ b/src/gallium/winsys/i915/drm/i915_drm_batchbuffer.c @@ -3,6 +3,7 @@ #include "util/u_memory.h" #include "i915_drm.h" +#include "i915/i915_debug.h" #define BATCH_RESERVED 16 @@ -151,7 +152,6 @@ i915_drm_batchbuffer_flush(struct i915_winsys_batchbuffer *ibatch, struct i915_drm_batchbuffer *batch = i915_drm_batchbuffer(ibatch); unsigned used = 0; int ret = 0; - int i; assert(i915_winsys_batchbuffer_space(ibatch) >= 0); @@ -186,20 +186,28 @@ i915_drm_batchbuffer_flush(struct i915_winsys_batchbuffer *ibatch, #endif /* Do the sending to HW */ - ret = drm_intel_bo_exec(batch->bo, used, NULL, 0, 0); - assert(ret == 0); - - if (i915_drm_winsys(ibatch->iws)->dump_cmd) { - unsigned *ptr; - drm_intel_bo_map(batch->bo, FALSE); - ptr = (unsigned*)batch->bo->virtual; + if (i915_drm_winsys(ibatch->iws)->send_cmd) + ret = drm_intel_bo_exec(batch->bo, used, NULL, 0, 0); + else + ret = 0; - debug_printf("%s:\n", __func__); - for (i = 0; i < used / 4; i++, ptr++) { - debug_printf("\t%08x: %08x\n", i*4, *ptr); - } - - drm_intel_bo_unmap(batch->bo); + if (ret != 0 || i915_drm_winsys(ibatch->iws)->dump_cmd) { +#ifdef INTEL_MAP_BATCHBUFFER +#ifdef INTEL_MAP_GTT + drm_intel_gem_bo_map_gtt(batch->bo); +#else + drm_intel_bo_map(batch->bo, 0); +#endif +#endif + i915_dump_batchbuffer(ibatch); + assert(ret == 0); +#ifdef INTEL_MAP_BATCHBUFFER +#ifdef INTEL_MAP_GTT + drm_intel_gem_bo_unmap_gtt(batch->bo); +#else + drm_intel_bo_unmap(batch->bo); +#endif +#endif } else { #ifdef INTEL_RUN_SYNC drm_intel_bo_map(batch->bo, FALSE); diff --git a/src/gallium/winsys/i915/drm/i915_drm_buffer.c b/src/gallium/winsys/i915/drm/i915_drm_buffer.c index 3bd85026b21..6b06e7ae995 100644 --- a/src/gallium/winsys/i915/drm/i915_drm_buffer.c +++ b/src/gallium/winsys/i915/drm/i915_drm_buffer.c @@ -1,5 +1,5 @@ -#include "state_tracker/drm_api.h" +#include "state_tracker/drm_driver.h" #include "i915_drm_winsys.h" #include "util/u_memory.h" diff --git a/src/gallium/winsys/i915/drm/i915_drm_public.h b/src/gallium/winsys/i915/drm/i915_drm_public.h new file mode 100644 index 00000000000..b828d8d670c --- /dev/null +++ b/src/gallium/winsys/i915/drm/i915_drm_public.h @@ -0,0 +1,9 @@ + +#ifndef I915_DRM_PUBLIC_H +#define I915_DRM_PUBLIC_H + +struct i915_winsys; + +struct i915_winsys * i915_drm_winsys_create(int drmFD); + +#endif diff --git a/src/gallium/winsys/i915/drm/i915_drm_api.c b/src/gallium/winsys/i915/drm/i915_drm_winsys.c index 5dfd5a78798..179a84a704b 100644 --- a/src/gallium/winsys/i915/drm/i915_drm_api.c +++ b/src/gallium/winsys/i915/drm/i915_drm_winsys.c @@ -1,14 +1,11 @@ #include <stdio.h> -#include "state_tracker/drm_api.h" +#include "state_tracker/drm_driver.h" #include "i915_drm_winsys.h" +#include "i915_drm_public.h" #include "util/u_memory.h" -#include "i915/i915_context.h" -#include "i915/i915_screen.h" - -#include "trace/tr_drm.h" /* * Helper functions @@ -48,22 +45,12 @@ i915_drm_winsys_destroy(struct i915_winsys *iws) FREE(idws); } -static struct pipe_screen * -i915_drm_create_screen(struct drm_api *api, int drmFD, - struct drm_create_screen_arg *arg) +struct i915_winsys * +i915_drm_winsys_create(int drmFD) { struct i915_drm_winsys *idws; unsigned int deviceID; - if (arg != NULL) { - switch(arg->mode) { - case DRM_CREATE_NORMAL: - break; - default: - return NULL; - } - } - idws = CALLOC_STRUCT(i915_drm_winsys); if (!idws) return NULL; @@ -75,7 +62,7 @@ i915_drm_create_screen(struct drm_api *api, int drmFD, i915_drm_winsys_init_fence_functions(idws); idws->fd = drmFD; - idws->id = deviceID; + idws->base.pci_id = deviceID; idws->max_batch_size = 16 * 4096; idws->base.destroy = i915_drm_winsys_destroy; @@ -83,21 +70,8 @@ i915_drm_create_screen(struct drm_api *api, int drmFD, idws->pools.gem = drm_intel_bufmgr_gem_init(idws->fd, idws->max_batch_size); drm_intel_bufmgr_gem_enable_reuse(idws->pools.gem); - idws->dump_cmd = debug_get_bool_option("INTEL_DUMP_CMD", FALSE); + idws->dump_cmd = debug_get_bool_option("I915_DUMP_CMD", FALSE); + idws->send_cmd = !debug_get_bool_option("I915_NO_HW", FALSE); - return i915_create_screen(&idws->base, deviceID); -} - -static struct drm_api i915_drm_api = -{ - .name = "i915", - .driver_name = "i915", - .create_screen = i915_drm_create_screen, - .destroy = NULL, -}; - -struct drm_api * -drm_api_create() -{ - return trace_drm_create(&i915_drm_api); + return &idws->base; } diff --git a/src/gallium/winsys/i915/drm/i915_drm_winsys.h b/src/gallium/winsys/i915/drm/i915_drm_winsys.h index 217c4a7eafb..88a71f2424d 100644 --- a/src/gallium/winsys/i915/drm/i915_drm_winsys.h +++ b/src/gallium/winsys/i915/drm/i915_drm_winsys.h @@ -18,11 +18,10 @@ struct i915_drm_winsys struct i915_winsys base; boolean dump_cmd; + boolean send_cmd; int fd; /**< Drm file discriptor */ - unsigned id; - size_t max_batch_size; struct { @@ -36,7 +35,6 @@ i915_drm_winsys(struct i915_winsys *iws) return (struct i915_drm_winsys *)iws; } -struct i915_drm_winsys * i915_drm_winsys_create(int fd, unsigned pci_id); struct pipe_fence_handle * i915_drm_fence_create(drm_intel_bo *bo); void i915_drm_winsys_init_batchbuffer_functions(struct i915_drm_winsys *idws); diff --git a/src/gallium/winsys/i915/sw/i915_sw_public.h b/src/gallium/winsys/i915/sw/i915_sw_public.h new file mode 100644 index 00000000000..e951a32917f --- /dev/null +++ b/src/gallium/winsys/i915/sw/i915_sw_public.h @@ -0,0 +1,9 @@ + +#ifndef I915_SW_PUBLIC_H +#define I915_SW_PUBLIC_H + +struct i915_winsys; + +struct i915_winsys * i915_sw_winsys_create(void); + +#endif diff --git a/src/gallium/winsys/i915/sw/i915_sw_winsys.c b/src/gallium/winsys/i915/sw/i915_sw_winsys.c index a03875be5b3..058ddc44aaf 100644 --- a/src/gallium/winsys/i915/sw/i915_sw_winsys.c +++ b/src/gallium/winsys/i915/sw/i915_sw_winsys.c @@ -1,5 +1,6 @@ #include "i915_sw_winsys.h" +#include "i915_sw_public.h" #include "util/u_memory.h" @@ -28,8 +29,8 @@ i915_sw_destroy(struct i915_winsys *iws) */ -struct pipe_screen * -i915_sw_create_screen() +struct i915_winsys * +i915_sw_winsys_create() { struct i915_sw_winsys *isws; unsigned int deviceID; @@ -46,11 +47,10 @@ i915_sw_create_screen() isws->base.destroy = i915_sw_destroy; - isws->id = deviceID; + isws->base.pci_id = deviceID; isws->max_batch_size = 16 * 4096; isws->dump_cmd = debug_get_bool_option("INTEL_DUMP_CMD", FALSE); - /* XXX so this will leak winsys:es */ - return i915_create_screen(&isws->base, deviceID); + return &isws->base; } diff --git a/src/gallium/winsys/i915/sw/i915_sw_winsys.h b/src/gallium/winsys/i915/sw/i915_sw_winsys.h index 92e7c36fd8c..b7b43669f30 100644 --- a/src/gallium/winsys/i915/sw/i915_sw_winsys.h +++ b/src/gallium/winsys/i915/sw/i915_sw_winsys.h @@ -16,8 +16,6 @@ struct i915_sw_winsys boolean dump_cmd; - unsigned id; - size_t max_batch_size; }; @@ -27,7 +25,6 @@ i915_sw_winsys(struct i915_winsys *iws) return (struct i915_sw_winsys *)iws; } -struct pipe_screen* i915_sw_create_screen(void); struct pipe_fence_handle * i915_sw_fence_create(void); void i915_sw_winsys_init_batchbuffer_functions(struct i915_sw_winsys *idws); diff --git a/src/gallium/winsys/i965/drm/Makefile b/src/gallium/winsys/i965/drm/Makefile index bbb71e25d84..46f98d7a24a 100644 --- a/src/gallium/winsys/i965/drm/Makefile +++ b/src/gallium/winsys/i965/drm/Makefile @@ -5,7 +5,7 @@ LIBNAME = i965drm C_SOURCES = \ i965_drm_buffer.c \ - i965_drm_api.c + i965_drm_winsys.c LIBRARY_INCLUDES = $(shell pkg-config libdrm --cflags-only-I) diff --git a/src/gallium/winsys/i965/drm/SConscript b/src/gallium/winsys/i965/drm/SConscript index abf9aac5c01..785be449f70 100644 --- a/src/gallium/winsys/i965/drm/SConscript +++ b/src/gallium/winsys/i965/drm/SConscript @@ -5,8 +5,8 @@ env = env.Clone() env.ParseConfig('pkg-config --cflags libdrm') i965drm_sources = [ - 'i965_drm_api.c', 'i965_drm_buffer.c', + 'i965_drm_winsys.c', ] i965drm = env.ConvenienceLibrary( diff --git a/src/gallium/winsys/i965/drm/i965_drm_buffer.c b/src/gallium/winsys/i965/drm/i965_drm_buffer.c index 33a17496b2b..ed62db60bbb 100644 --- a/src/gallium/winsys/i965/drm/i965_drm_buffer.c +++ b/src/gallium/winsys/i965/drm/i965_drm_buffer.c @@ -1,5 +1,5 @@ -#include "state_tracker/drm_api.h" +#include "state_tracker/drm_driver.h" #include "i965_drm_winsys.h" #include "util/u_memory.h" #include "util/u_inlines.h" @@ -322,7 +322,7 @@ i965_libdrm_bo_subdata(struct brw_winsys_buffer *buffer, nr_reloc); if (BRW_DUMP) - brw_dump_data( idws->id, + brw_dump_data( idws->base.pci_id, data_type, buf->bo->offset + offset, data, size ); @@ -460,10 +460,10 @@ i965_libdrm_bo_flush_range(struct brw_winsys_buffer *buffer, offset, length); if (BRW_DUMP) - brw_dump_data( idws->id, + brw_dump_data( idws->base.pci_id, buf->data_type, buf->bo->offset + offset, - buf->bo->virtual + offset, + (char*)buf->bo->virtual + offset, length ); } diff --git a/src/gallium/winsys/i965/drm/i965_drm_public.h b/src/gallium/winsys/i965/drm/i965_drm_public.h new file mode 100644 index 00000000000..2913b079747 --- /dev/null +++ b/src/gallium/winsys/i965/drm/i965_drm_public.h @@ -0,0 +1,9 @@ + +#ifndef I965_DRM_PUBLIC_H +#define I965_DRM_PUBLIC_H + +struct brw_winsys_screen; + +struct brw_winsys_screen * i965_drm_winsys_screen_create(int drmFD); + +#endif diff --git a/src/gallium/winsys/i965/drm/i965_drm_api.c b/src/gallium/winsys/i965/drm/i965_drm_winsys.c index bd4dcfc9be7..b08e622db94 100644 --- a/src/gallium/winsys/i965/drm/i965_drm_api.c +++ b/src/gallium/winsys/i965/drm/i965_drm_winsys.c @@ -1,17 +1,11 @@ #include <stdio.h> -#include "state_tracker/drm_api.h" +#include "state_tracker/drm_driver.h" #include "i965_drm_winsys.h" +#include "i965_drm_public.h" #include "util/u_memory.h" -#include "i965/brw_context.h" /* XXX: shouldn't be doing this */ -#include "i965/brw_screen.h" /* XXX: shouldn't be doing this */ - -#include "trace/tr_drm.h" - -#include "../../sw/drm/sw_drm_api.h" - /* * Helper functions */ @@ -52,34 +46,22 @@ i965_libdrm_winsys_destroy(struct brw_winsys_screen *iws) FREE(idws); } -static struct pipe_screen * -i965_libdrm_create_screen(struct drm_api *api, int drmFD, - struct drm_create_screen_arg *arg) +struct brw_winsys_screen * +i965_drm_winsys_screen_create(int drmFD) { struct i965_libdrm_winsys *idws; - unsigned int deviceID; debug_printf("%s\n", __FUNCTION__); - if (arg != NULL) { - switch(arg->mode) { - case DRM_CREATE_NORMAL: - break; - default: - return NULL; - } - } - idws = CALLOC_STRUCT(i965_libdrm_winsys); if (!idws) return NULL; - i965_libdrm_get_device_id(&deviceID); + i965_libdrm_get_device_id(&idws->base.pci_id); i965_libdrm_winsys_init_buffer_functions(idws); idws->fd = drmFD; - idws->id = deviceID; idws->base.destroy = i965_libdrm_winsys_destroy; @@ -88,27 +70,5 @@ i965_libdrm_create_screen(struct drm_api *api, int drmFD, idws->send_cmd = !debug_get_bool_option("BRW_NO_HW", FALSE); - return brw_create_screen(&idws->base, deviceID); -} - -struct drm_api i965_libdrm_api = -{ - .name = "i965", - .driver_name = "i915", - .create_screen = i965_libdrm_create_screen, - .destroy = NULL, -}; - -struct drm_api * -drm_api_create() -{ - struct drm_api *api = NULL; - - if (api == NULL && debug_get_bool_option("BRW_SOFTPIPE", FALSE)) - api = sw_drm_api_create(&i965_libdrm_api); - - if (api == NULL) - api = &i965_libdrm_api; - - return trace_drm_create(api); + return &idws->base; } diff --git a/src/gallium/winsys/i965/drm/i965_drm_winsys.h b/src/gallium/winsys/i965/drm/i965_drm_winsys.h index c6a7d4a8c51..82dbe61cc51 100644 --- a/src/gallium/winsys/i965/drm/i965_drm_winsys.h +++ b/src/gallium/winsys/i965/drm/i965_drm_winsys.h @@ -22,8 +22,6 @@ struct i965_libdrm_winsys boolean send_cmd; int fd; /**< Drm file discriptor */ - - unsigned id; }; static INLINE struct i965_libdrm_winsys * @@ -32,8 +30,6 @@ i965_libdrm_winsys(struct brw_winsys_screen *iws) return (struct i965_libdrm_winsys *)iws; } -struct i965_libdrm_winsys *i965_libdrm_winsys_create(int fd, unsigned pci_id); - void i965_libdrm_winsys_init_buffer_functions(struct i965_libdrm_winsys *idws); diff --git a/src/gallium/winsys/i965/xlib/Makefile b/src/gallium/winsys/i965/xlib/Makefile index 3730db6997e..cc8249395c5 100644 --- a/src/gallium/winsys/i965/xlib/Makefile +++ b/src/gallium/winsys/i965/xlib/Makefile @@ -38,7 +38,7 @@ LIBS = \ $(TOP)/src/gallium/drivers/i965/libi965.a \ $(TOP)/src/gallium/drivers/trace/libtrace.a \ $(TOP)/src/gallium/state_trackers/glx/xlib/libxlib.a \ - $(TOP)/src/mesa/libglapi.a \ + $(TOP)/src/mapi/glapi/libglapi.a \ $(TOP)/src/mesa/libmesagallium.a \ $(GALLIUM_AUXILIARIES) diff --git a/src/gallium/winsys/i965/xlib/xlib_i965.c b/src/gallium/winsys/i965/xlib/xlib_i965.c index 063e9f600b9..baadd6e89ca 100644 --- a/src/gallium/winsys/i965/xlib/xlib_i965.c +++ b/src/gallium/winsys/i965/xlib/xlib_i965.c @@ -395,6 +395,7 @@ xlib_create_brw_winsys_screen( void ) return NULL; ws->used = 0; + ws->base.pci_id = PCI_CHIP_GM45_GM; ws->base.destroy = xlib_brw_winsys_destroy; ws->base.bo_alloc = xlib_brw_bo_alloc; @@ -452,7 +453,7 @@ xlib_create_i965_screen( void ) if (winsys == NULL) return NULL; - screen = brw_create_screen(winsys, PCI_CHIP_GM45_GM); + screen = brw_create_screen(winsys); if (screen == NULL) goto fail; diff --git a/src/gallium/winsys/nouveau/drm/Makefile b/src/gallium/winsys/nouveau/drm/Makefile index 71029858f75..74a3c6a0d70 100644 --- a/src/gallium/winsys/nouveau/drm/Makefile +++ b/src/gallium/winsys/nouveau/drm/Makefile @@ -3,7 +3,7 @@ include $(TOP)/configs/current LIBNAME = nouveaudrm -C_SOURCES = nouveau_drm_api.c +C_SOURCES = nouveau_drm_winsys.c LIBRARY_INCLUDES = $(shell pkg-config libdrm libdrm_nouveau --cflags-only-I) LIBRARY_DEFINES = $(shell pkg-config libdrm libdrm_nouveau --cflags-only-other) diff --git a/src/gallium/winsys/nouveau/drm/nouveau_drm_api.c b/src/gallium/winsys/nouveau/drm/nouveau_drm_api.c deleted file mode 100644 index 37f33875a5b..00000000000 --- a/src/gallium/winsys/nouveau/drm/nouveau_drm_api.c +++ /dev/null @@ -1,160 +0,0 @@ -#include "pipe/p_context.h" -#include "pipe/p_state.h" -#include "util/u_format.h" -#include "util/u_memory.h" -#include "util/u_inlines.h" - -#include "nouveau_drm_api.h" - -#include "nouveau_drmif.h" -#include "nouveau_channel.h" -#include "nouveau_bo.h" - -#include "nouveau/nouveau_winsys.h" -#include "nouveau/nouveau_screen.h" - -static struct pipe_surface * -dri_surface_from_handle(struct drm_api *api, struct pipe_screen *pscreen, - unsigned handle, enum pipe_format format, - unsigned width, unsigned height, unsigned pitch) -{ - struct pipe_surface *ps = NULL; - struct pipe_resource *pt = NULL; - struct pipe_resource tmpl; - struct winsys_handle whandle; - unsigned bind = (PIPE_BIND_SCANOUT | - PIPE_BIND_RENDER_TARGET | - PIPE_BIND_BLIT_DESTINATION | - PIPE_BIND_BLIT_SOURCE); - - memset(&tmpl, 0, sizeof(tmpl)); - tmpl.bind = bind; - tmpl.target = PIPE_TEXTURE_2D; - tmpl.last_level = 0; - tmpl.depth0 = 1; - tmpl.format = format; - tmpl.width0 = width; - tmpl.height0 = height; - - memset(&whandle, 0, sizeof(whandle)); - whandle.stride = pitch; - whandle.handle = handle; - - pt = pscreen->resource_from_handle(pscreen, &tmpl, &whandle); - if (!pt) - return NULL; - - ps = pscreen->get_tex_surface(pscreen, pt, 0, 0, 0, bind); - - /* we don't need the texture from this point on */ - pipe_resource_reference(&pt, NULL); - return ps; -} - -static struct pipe_surface * -nouveau_dri1_front_surface(struct pipe_screen *screen) -{ - return nouveau_winsys_screen(screen)->front; -} - -static struct dri1_api nouveau_dri1_api = { - nouveau_dri1_front_surface, -}; - -static void -nouveau_drm_destroy_winsys(struct pipe_winsys *s) -{ - struct nouveau_winsys *nv_winsys = nouveau_winsys(s); - struct nouveau_screen *nv_screen= nouveau_screen(nv_winsys->pscreen); - nouveau_device_close(&nv_screen->device); - FREE(nv_winsys); -} - -static struct pipe_screen * -nouveau_drm_create_screen(struct drm_api *api, int fd, - struct drm_create_screen_arg *arg) -{ - struct dri1_create_screen_arg *dri1 = (void *)arg; - struct nouveau_winsys *nvws; - struct pipe_winsys *ws; - struct nouveau_device *dev = NULL; - struct pipe_screen *(*init)(struct pipe_winsys *, - struct nouveau_device *); - int ret; - - ret = nouveau_device_open_existing(&dev, 0, fd, 0); - if (ret) - return NULL; - - switch (dev->chipset & 0xf0) { - case 0x30: - case 0x40: - case 0x60: - init = nvfx_screen_create; - break; - case 0x50: - case 0x80: - case 0x90: - case 0xa0: - init = nv50_screen_create; - break; - default: - debug_printf("%s: unknown chipset nv%02x\n", __func__, - dev->chipset); - return NULL; - } - - nvws = CALLOC_STRUCT(nouveau_winsys); - if (!nvws) { - nouveau_device_close(&dev); - return NULL; - } - ws = &nvws->base; - ws->destroy = nouveau_drm_destroy_winsys; - - nvws->pscreen = init(ws, dev); - if (!nvws->pscreen) { - ws->destroy(ws); - return NULL; - } - - if (arg && arg->mode == DRM_CREATE_DRI1) { - struct nouveau_dri *nvdri = dri1->ddx_info; - enum pipe_format format; - - if (nvdri->bpp == 16) - format = PIPE_FORMAT_B5G6R5_UNORM; - else - format = PIPE_FORMAT_B8G8R8A8_UNORM; - - nvws->front = dri_surface_from_handle(api, nvws->pscreen, - nvdri->front_offset, - format, nvdri->width, - nvdri->height, - nvdri->front_pitch * - (nvdri->bpp / 8)); - if (!nvws->front) { - debug_printf("%s: error referencing front buffer\n", - __func__); - ws->destroy(ws); - return NULL; - } - - dri1->api = &nouveau_dri1_api; - } - - return nvws->pscreen; -} - -static struct drm_api nouveau_drm_api_hooks = { - .name = "nouveau", - .driver_name = "nouveau", - .create_screen = nouveau_drm_create_screen, - .destroy = NULL, -}; - -struct drm_api * -drm_api_create() { - return &nouveau_drm_api_hooks; -} - diff --git a/src/gallium/winsys/nouveau/drm/nouveau_drm_public.h b/src/gallium/winsys/nouveau/drm/nouveau_drm_public.h new file mode 100644 index 00000000000..67b7c4429df --- /dev/null +++ b/src/gallium/winsys/nouveau/drm/nouveau_drm_public.h @@ -0,0 +1,9 @@ + +#ifndef __NOUVEAU_DRM_PUBLIC_H__ +#define __NOUVEAU_DRM_PUBLIC_H__ + +struct pipe_screen; + +struct pipe_screen *nouveau_drm_screen_create(int drmFD); + +#endif diff --git a/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c new file mode 100644 index 00000000000..d4bf124ce6f --- /dev/null +++ b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c @@ -0,0 +1,74 @@ +#include "pipe/p_context.h" +#include "pipe/p_state.h" +#include "util/u_format.h" +#include "util/u_memory.h" +#include "util/u_inlines.h" + +#include "nouveau_drm_winsys.h" +#include "nouveau_drm_public.h" + +#include "nouveau_drmif.h" +#include "nouveau_channel.h" +#include "nouveau_bo.h" + +#include "nouveau/nouveau_winsys.h" +#include "nouveau/nouveau_screen.h" + +static void +nouveau_drm_destroy_winsys(struct pipe_winsys *s) +{ + struct nouveau_winsys *nv_winsys = nouveau_winsys(s); + struct nouveau_screen *nv_screen= nouveau_screen(nv_winsys->pscreen); + if (nv_screen) + nouveau_device_close(&nv_screen->device); + FREE(nv_winsys); +} + +struct pipe_screen * +nouveau_drm_screen_create(int fd) +{ + struct nouveau_winsys *nvws; + struct pipe_winsys *ws; + struct nouveau_device *dev = NULL; + struct pipe_screen *(*init)(struct pipe_winsys *, + struct nouveau_device *); + int ret; + + ret = nouveau_device_open_existing(&dev, 0, fd, 0); + if (ret) + return NULL; + + switch (dev->chipset & 0xf0) { + case 0x30: + case 0x40: + case 0x60: + init = nvfx_screen_create; + break; + case 0x50: + case 0x80: + case 0x90: + case 0xa0: + init = nv50_screen_create; + break; + default: + debug_printf("%s: unknown chipset nv%02x\n", __func__, + dev->chipset); + return NULL; + } + + nvws = CALLOC_STRUCT(nouveau_winsys); + if (!nvws) { + nouveau_device_close(&dev); + return NULL; + } + ws = &nvws->base; + ws->destroy = nouveau_drm_destroy_winsys; + + nvws->pscreen = init(ws, dev); + if (!nvws->pscreen) { + ws->destroy(ws); + return NULL; + } + + return nvws->pscreen; +} diff --git a/src/gallium/winsys/nouveau/drm/nouveau_drm_api.h b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.h index a91aad7df8e..9e529ecad3d 100644 --- a/src/gallium/winsys/nouveau/drm/nouveau_drm_api.h +++ b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.h @@ -1,8 +1,5 @@ -#ifndef __NOUVEAU_DRM_API_H__ -#define __NOUVEAU_DRM_API_H__ - -#include "state_tracker/drm_api.h" -#include "state_tracker/dri1_api.h" +#ifndef __NOUVEAU_DRM_WINSYS_H__ +#define __NOUVEAU_DRM_WINSYS_H__ #include "util/u_simple_screen.h" diff --git a/src/gallium/winsys/r600/drm/Makefile b/src/gallium/winsys/r600/drm/Makefile new file mode 100644 index 00000000000..a396205f897 --- /dev/null +++ b/src/gallium/winsys/r600/drm/Makefile @@ -0,0 +1,23 @@ + +TOP = ../../../../.. +include $(TOP)/configs/current + +LIBNAME = r600winsys + +C_SOURCES = \ + bof.c \ + evergreen_hw_context.c \ + radeon_bo.c \ + radeon_bo_pb.c \ + radeon_pciid.c \ + r600.c \ + r600_bo.c \ + r600_drm.c \ + r600_hw_context.c + +LIBRARY_INCLUDES = -I$(TOP)/src/gallium/drivers/r600 \ + $(shell pkg-config libdrm --cflags-only-I) + +include ../../../Makefile.template + +symlinks: diff --git a/src/gallium/winsys/r600/drm/SConscript b/src/gallium/winsys/r600/drm/SConscript new file mode 100644 index 00000000000..cc053c06dd0 --- /dev/null +++ b/src/gallium/winsys/r600/drm/SConscript @@ -0,0 +1,25 @@ +Import('*') + +env = env.Clone() + +r600_sources = [ + 'bof.c', + 'evergreen_hw_context.c', + 'radeon_bo.c', + 'radeon_bo_pb.c', + 'radeon_pciid.c', + 'r600.c', + 'r600_bo.c', + 'r600_drm.c', + 'r600_hw_context.c', +] + +env.ParseConfig('pkg-config --cflags libdrm_radeon') +env.Append(CPPPATH = '#/src/gallium/drivers/r600') + +r600winsys = env.ConvenienceLibrary( + target ='r600winsys', + source = r600_sources, +) + +Export('r600winsys') diff --git a/src/gallium/winsys/r600/drm/bof.c b/src/gallium/winsys/r600/drm/bof.c new file mode 100644 index 00000000000..0598cc6bc0f --- /dev/null +++ b/src/gallium/winsys/r600/drm/bof.c @@ -0,0 +1,477 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <errno.h> +#include <stdlib.h> +#include <string.h> +#include "bof.h" + +/* + * helpers + */ +static int bof_entry_grow(bof_t *bof) +{ + bof_t **array; + + if (bof->array_size < bof->nentry) + return 0; + array = realloc(bof->array, (bof->nentry + 16) * sizeof(void*)); + if (array == NULL) + return -ENOMEM; + bof->array = array; + bof->nentry += 16; + return 0; +} + +/* + * object + */ +bof_t *bof_object(void) +{ + bof_t *object; + + object = calloc(1, sizeof(bof_t)); + if (object == NULL) + return NULL; + object->refcount = 1; + object->type = BOF_TYPE_OBJECT; + object->size = 12; + return object; +} + +bof_t *bof_object_get(bof_t *object, const char *keyname) +{ + unsigned i; + + for (i = 0; i < object->array_size; i += 2) { + if (!strcmp(object->array[i]->value, keyname)) { + return object->array[i + 1]; + } + } + return NULL; +} + +int bof_object_set(bof_t *object, const char *keyname, bof_t *value) +{ + bof_t *key; + int r; + + if (object->type != BOF_TYPE_OBJECT) + return -EINVAL; + r = bof_entry_grow(object); + if (r) + return r; + key = bof_string(keyname); + if (key == NULL) + return -ENOMEM; + object->array[object->array_size++] = key; + object->array[object->array_size++] = value; + object->size += value->size; + object->size += key->size; + bof_incref(value); + return 0; +} + +/* + * array + */ +bof_t *bof_array(void) +{ + bof_t *array = bof_object(); + + if (array == NULL) + return NULL; + array->type = BOF_TYPE_ARRAY; + array->size = 12; + return array; +} + +int bof_array_append(bof_t *array, bof_t *value) +{ + int r; + if (array->type != BOF_TYPE_ARRAY) + return -EINVAL; + r = bof_entry_grow(array); + if (r) + return r; + array->array[array->array_size++] = value; + array->size += value->size; + bof_incref(value); + return 0; +} + +bof_t *bof_array_get(bof_t *bof, unsigned i) +{ + if (!bof_is_array(bof) || i >= bof->array_size) + return NULL; + return bof->array[i]; +} + +unsigned bof_array_size(bof_t *bof) +{ + if (!bof_is_array(bof)) + return 0; + return bof->array_size; +} + +/* + * blob + */ +bof_t *bof_blob(unsigned size, void *value) +{ + bof_t *blob = bof_object(); + + if (blob == NULL) + return NULL; + blob->type = BOF_TYPE_BLOB; + blob->value = calloc(1, size); + if (blob->value == NULL) { + bof_decref(blob); + return NULL; + } + blob->size = size; + memcpy(blob->value, value, size); + blob->size += 12; + return blob; +} + +unsigned bof_blob_size(bof_t *bof) +{ + if (!bof_is_blob(bof)) + return 0; + return bof->size - 12; +} + +void *bof_blob_value(bof_t *bof) +{ + if (!bof_is_blob(bof)) + return NULL; + return bof->value; +} + +/* + * string + */ +bof_t *bof_string(const char *value) +{ + bof_t *string = bof_object(); + + if (string == NULL) + return NULL; + string->type = BOF_TYPE_STRING; + string->size = strlen(value) + 1; + string->value = calloc(1, string->size); + if (string->value == NULL) { + bof_decref(string); + return NULL; + } + strcpy(string->value, value); + string->size += 12; + return string; +} + +/* + * int32 + */ +bof_t *bof_int32(int32_t value) +{ + bof_t *int32 = bof_object(); + + if (int32 == NULL) + return NULL; + int32->type = BOF_TYPE_INT32; + int32->size = 4; + int32->value = calloc(1, int32->size); + if (int32->value == NULL) { + bof_decref(int32); + return NULL; + } + memcpy(int32->value, &value, 4); + int32->size += 12; + return int32; +} + +int32_t bof_int32_value(bof_t *bof) +{ + return *((uint32_t*)bof->value); +} + +/* + * common + */ +static void bof_indent(int level) +{ + int i; + + for (i = 0; i < level; i++) + fprintf(stderr, " "); +} + +static void bof_print_bof(bof_t *bof, int level, int entry) +{ + bof_indent(level); + if (bof == NULL) { + fprintf(stderr, "--NULL-- for entry %d\n", entry); + return; + } + switch (bof->type) { + case BOF_TYPE_STRING: + fprintf(stderr, "%p string [%s %d]\n", bof, (char*)bof->value, bof->size); + break; + case BOF_TYPE_INT32: + fprintf(stderr, "%p int32 [%d %d]\n", bof, *(int*)bof->value, bof->size); + break; + case BOF_TYPE_BLOB: + fprintf(stderr, "%p blob [%d]\n", bof, bof->size); + break; + case BOF_TYPE_NULL: + fprintf(stderr, "%p null [%d]\n", bof, bof->size); + break; + case BOF_TYPE_OBJECT: + fprintf(stderr, "%p object [%d %d]\n", bof, bof->array_size / 2, bof->size); + break; + case BOF_TYPE_ARRAY: + fprintf(stderr, "%p array [%d %d]\n", bof, bof->array_size, bof->size); + break; + default: + fprintf(stderr, "%p unknown [%d]\n", bof, bof->type); + return; + } +} + +static void bof_print_rec(bof_t *bof, int level, int entry) +{ + unsigned i; + + bof_print_bof(bof, level, entry); + for (i = 0; i < bof->array_size; i++) { + bof_print_rec(bof->array[i], level + 2, i); + } +} + +void bof_print(bof_t *bof) +{ + bof_print_rec(bof, 0, 0); +} + +static int bof_read(bof_t *root, FILE *file, long end, int level) +{ + bof_t *bof = NULL; + int r; + + if (ftell(file) >= end) { + return 0; + } + r = bof_entry_grow(root); + if (r) + return r; + bof = bof_object(); + if (bof == NULL) + return -ENOMEM; + bof->offset = ftell(file); + r = fread(&bof->type, 4, 1, file); + if (r != 1) + goto out_err; + r = fread(&bof->size, 4, 1, file); + if (r != 1) + goto out_err; + r = fread(&bof->array_size, 4, 1, file); + if (r != 1) + goto out_err; + switch (bof->type) { + case BOF_TYPE_STRING: + case BOF_TYPE_INT32: + case BOF_TYPE_BLOB: + bof->value = calloc(1, bof->size - 12); + if (bof->value == NULL) { + goto out_err; + } + r = fread(bof->value, bof->size - 12, 1, file); + if (r != 1) { + fprintf(stderr, "error reading %d\n", bof->size - 12); + goto out_err; + } + break; + case BOF_TYPE_NULL: + return 0; + case BOF_TYPE_OBJECT: + case BOF_TYPE_ARRAY: + r = bof_read(bof, file, bof->offset + bof->size, level + 2); + if (r) + goto out_err; + break; + default: + fprintf(stderr, "invalid type %d\n", bof->type); + goto out_err; + } + root->array[root->centry++] = bof; + return bof_read(root, file, end, level); +out_err: + bof_decref(bof); + return -EINVAL; +} + +bof_t *bof_load_file(const char *filename) +{ + bof_t *root = bof_object(); + int r; + + if (root == NULL) { + fprintf(stderr, "%s failed to create root object\n", __func__); + return NULL; + } + root->file = fopen(filename, "r"); + if (root->file == NULL) + goto out_err; + r = fseek(root->file, 0L, SEEK_SET); + if (r) { + fprintf(stderr, "%s failed to seek into file %s\n", __func__, filename); + goto out_err; + } + root->offset = ftell(root->file); + r = fread(&root->type, 4, 1, root->file); + if (r != 1) + goto out_err; + r = fread(&root->size, 4, 1, root->file); + if (r != 1) + goto out_err; + r = fread(&root->array_size, 4, 1, root->file); + if (r != 1) + goto out_err; + r = bof_read(root, root->file, root->offset + root->size, 2); + if (r) + goto out_err; + return root; +out_err: + bof_decref(root); + return NULL; +} + +void bof_incref(bof_t *bof) +{ + bof->refcount++; +} + +void bof_decref(bof_t *bof) +{ + unsigned i; + + if (bof == NULL) + return; + if (--bof->refcount > 0) + return; + for (i = 0; i < bof->array_size; i++) { + bof_decref(bof->array[i]); + bof->array[i] = NULL; + } + bof->array_size = 0; + if (bof->file) { + fclose(bof->file); + bof->file = NULL; + } + free(bof->array); + free(bof->value); + free(bof); +} + +static int bof_file_write(bof_t *bof, FILE *file) +{ + unsigned i; + int r; + + r = fwrite(&bof->type, 4, 1, file); + if (r != 1) + return -EINVAL; + r = fwrite(&bof->size, 4, 1, file); + if (r != 1) + return -EINVAL; + r = fwrite(&bof->array_size, 4, 1, file); + if (r != 1) + return -EINVAL; + switch (bof->type) { + case BOF_TYPE_NULL: + if (bof->size) + return -EINVAL; + break; + case BOF_TYPE_STRING: + case BOF_TYPE_INT32: + case BOF_TYPE_BLOB: + r = fwrite(bof->value, bof->size - 12, 1, file); + if (r != 1) + return -EINVAL; + break; + case BOF_TYPE_OBJECT: + case BOF_TYPE_ARRAY: + for (i = 0; i < bof->array_size; i++) { + r = bof_file_write(bof->array[i], file); + if (r) + return r; + } + break; + default: + return -EINVAL; + } + return 0; +} + +int bof_dump_file(bof_t *bof, const char *filename) +{ + unsigned i; + int r = 0; + + if (bof->file) { + fclose(bof->file); + bof->file = NULL; + } + bof->file = fopen(filename, "w"); + if (bof->file == NULL) { + fprintf(stderr, "%s failed to open file %s\n", __func__, filename); + r = -EINVAL; + goto out_err; + } + r = fseek(bof->file, 0L, SEEK_SET); + if (r) { + fprintf(stderr, "%s failed to seek into file %s\n", __func__, filename); + goto out_err; + } + r = fwrite(&bof->type, 4, 1, bof->file); + if (r != 1) + goto out_err; + r = fwrite(&bof->size, 4, 1, bof->file); + if (r != 1) + goto out_err; + r = fwrite(&bof->array_size, 4, 1, bof->file); + if (r != 1) + goto out_err; + for (i = 0; i < bof->array_size; i++) { + r = bof_file_write(bof->array[i], bof->file); + if (r) + return r; + } +out_err: + fclose(bof->file); + bof->file = NULL; + return r; +} diff --git a/src/gallium/winsys/r600/drm/bof.h b/src/gallium/winsys/r600/drm/bof.h new file mode 100644 index 00000000000..014affb74f1 --- /dev/null +++ b/src/gallium/winsys/r600/drm/bof.h @@ -0,0 +1,90 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef BOF_H +#define BOF_H + +#include <stdio.h> +#include <stdint.h> + +#define BOF_TYPE_STRING 0 +#define BOF_TYPE_NULL 1 +#define BOF_TYPE_BLOB 2 +#define BOF_TYPE_OBJECT 3 +#define BOF_TYPE_ARRAY 4 +#define BOF_TYPE_INT32 5 + +struct bof; + +typedef struct bof { + struct bof **array; + unsigned centry; + unsigned nentry; + unsigned refcount; + FILE *file; + uint32_t type; + uint32_t size; + uint32_t array_size; + void *value; + long offset; +} bof_t; + +extern int bof_file_flush(bof_t *root); +extern bof_t *bof_file_new(const char *filename); +extern int bof_object_dump(bof_t *object, const char *filename); + +/* object */ +extern bof_t *bof_object(void); +extern bof_t *bof_object_get(bof_t *object, const char *keyname); +extern int bof_object_set(bof_t *object, const char *keyname, bof_t *value); +/* array */ +extern bof_t *bof_array(void); +extern int bof_array_append(bof_t *array, bof_t *value); +extern bof_t *bof_array_get(bof_t *bof, unsigned i); +extern unsigned bof_array_size(bof_t *bof); +/* blob */ +extern bof_t *bof_blob(unsigned size, void *value); +extern unsigned bof_blob_size(bof_t *bof); +extern void *bof_blob_value(bof_t *bof); +/* string */ +extern bof_t *bof_string(const char *value); +/* int32 */ +extern bof_t *bof_int32(int32_t value); +extern int32_t bof_int32_value(bof_t *bof); +/* common functions */ +extern void bof_decref(bof_t *bof); +extern void bof_incref(bof_t *bof); +extern bof_t *bof_load_file(const char *filename); +extern int bof_dump_file(bof_t *bof, const char *filename); +extern void bof_print(bof_t *bof); + +static inline int bof_is_object(bof_t *bof){return (bof->type == BOF_TYPE_OBJECT);} +static inline int bof_is_blob(bof_t *bof){return (bof->type == BOF_TYPE_BLOB);} +static inline int bof_is_null(bof_t *bof){return (bof->type == BOF_TYPE_NULL);} +static inline int bof_is_int32(bof_t *bof){return (bof->type == BOF_TYPE_INT32);} +static inline int bof_is_array(bof_t *bof){return (bof->type == BOF_TYPE_ARRAY);} +static inline int bof_is_string(bof_t *bof){return (bof->type == BOF_TYPE_STRING);} + +#endif diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c new file mode 100644 index 00000000000..7f21b53ace0 --- /dev/null +++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c @@ -0,0 +1,919 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <errno.h> +#include <stdint.h> +#include <string.h> +#include <stdlib.h> +#include <assert.h> +#include "xf86drm.h" +#include "r600.h" +#include "evergreend.h" +#include "radeon_drm.h" +#include "bof.h" +#include "pipe/p_compiler.h" +#include "util/u_inlines.h" +#include "util/u_memory.h" +#include <pipebuffer/pb_bufmgr.h> +#include "r600_priv.h" + +#define GROUP_FORCE_NEW_BLOCK 0 + +static const struct r600_reg evergreen_config_reg_list[] = { + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008A14_PA_CL_ENHANCE, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C20_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C24_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C28_SQ_STACK_RESOURCE_MGMT_3, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_009100_SPI_CONFIG_CNTL, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_00913C_SPI_CONFIG_CNTL_1, 0, 0, 0}, +}; + +static const struct r600_reg evergreen_ctl_const_list[] = { + {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, + {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, +}; + +static const struct r600_reg evergreen_context_reg_list[] = { + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028000_DB_RENDER_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028004_DB_COUNT_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028008_DB_DEPTH_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028014_DB_HTILE_DATA_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028040_DB_Z_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028044_DB_STENCIL_INFO, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028048_DB_Z_READ_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02804C_DB_STENCIL_READ_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028050_DB_Z_WRITE_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028054_DB_STENCIL_WRITE_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028058_DB_DEPTH_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02805C_DB_DEPTH_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285BC_PA_CL_UCP0_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C0_PA_CL_UCP0_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C4_PA_CL_UCP0_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C8_PA_CL_UCP0_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285CC_PA_CL_UCP1_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D0_PA_CL_UCP1_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D4_PA_CL_UCP1_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D8_PA_CL_UCP1_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285DC_PA_CL_UCP2_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E0_PA_CL_UCP2_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E4_PA_CL_UCP2_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E8_PA_CL_UCP2_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285EC_PA_CL_UCP3_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F0_PA_CL_UCP3_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F4_PA_CL_UCP3_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F8_PA_CL_UCP3_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285FC_PA_CL_UCP4_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028600_PA_CL_UCP4_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028604_PA_CL_UCP4_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028608_PA_CL_UCP4_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02860C_PA_CL_UCP5_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028610_PA_CL_UCP5_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028614_PA_CL_UCP5_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028618_PA_CL_UCP5_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_5, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_6, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_7, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028640_SPI_VS_OUT_ID_9, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E0_SPI_BARYC_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02885C_SQ_PGM_START_VS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_START_FS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028ABC_DB_HTILE_SURFACE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C3C_PA_SC_AA_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C60_CB_COLOR0_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C64_CB_COLOR0_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C68_CB_COLOR0_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C6C_CB_COLOR0_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C70_CB_COLOR0_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C74_CB_COLOR0_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C78_CB_COLOR0_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C9C_CB_COLOR1_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA0_CB_COLOR1_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA4_CB_COLOR1_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA8_CB_COLOR1_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CAC_CB_COLOR1_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CB0_CB_COLOR1_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CB4_CB_COLOR1_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CD8_CB_COLOR2_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CDC_CB_COLOR2_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE0_CB_COLOR2_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE4_CB_COLOR2_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE8_CB_COLOR2_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CEC_CB_COLOR2_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CF0_CB_COLOR2_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D14_CB_COLOR3_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D18_CB_COLOR3_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D1C_CB_COLOR3_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D20_CB_COLOR3_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D24_CB_COLOR3_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D28_CB_COLOR3_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D2C_CB_COLOR3_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D50_CB_COLOR4_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D54_CB_COLOR4_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D58_CB_COLOR4_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D5C_CB_COLOR4_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D60_CB_COLOR4_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D64_CB_COLOR4_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D68_CB_COLOR4_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D8C_CB_COLOR5_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D90_CB_COLOR5_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D94_CB_COLOR5_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D98_CB_COLOR5_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D9C_CB_COLOR5_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DA0_CB_COLOR5_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DA4_CB_COLOR5_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DC8_CB_COLOR6_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DCC_CB_COLOR6_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD0_CB_COLOR6_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD4_CB_COLOR6_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD8_CB_COLOR6_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DDC_CB_COLOR6_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DE0_CB_COLOR6_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E04_CB_COLOR7_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E08_CB_COLOR7_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E0C_CB_COLOR7_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E10_CB_COLOR7_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E14_CB_COLOR7_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E18_CB_COLOR7_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E1C_CB_COLOR7_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E40_CB_COLOR8_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E44_CB_COLOR8_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E48_CB_COLOR8_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E4C_CB_COLOR8_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E50_CB_COLOR8_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E54_CB_COLOR8_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E58_CB_COLOR8_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E5C_CB_COLOR9_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E60_CB_COLOR9_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E64_CB_COLOR9_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E68_CB_COLOR9_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E6C_CB_COLOR9_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E70_CB_COLOR9_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E74_CB_COLOR9_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E78_CB_COLOR10_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E7C_CB_COLOR10_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E80_CB_COLOR10_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E84_CB_COLOR10_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E88_CB_COLOR10_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E8C_CB_COLOR10_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E90_CB_COLOR10_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E94_CB_COLOR11_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E98_CB_COLOR11_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E9C_CB_COLOR11_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA0_CB_COLOR11_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA4_CB_COLOR11_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA8_CB_COLOR11_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EAC_CB_COLOR11_DIM, 0, 0, 0}, +}; + +/* SHADER RESOURCE R600/R700 */ +static int evergreen_state_resource_init(struct r600_context *ctx, u32 offset) +{ + struct r600_reg r600_shader_resource[] = { + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030000_RESOURCE0_WORD0, 0, 0, 0}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030004_RESOURCE0_WORD1, 0, 0, 0}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030008_RESOURCE0_WORD2, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_03000C_RESOURCE0_WORD3, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030010_RESOURCE0_WORD4, 0, 0, 0}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030014_RESOURCE0_WORD5, 0, 0, 0}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030018_RESOURCE0_WORD6, 0, 0, 0}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_03001C_RESOURCE0_WORD7, 0, 0, 0}, + }; + unsigned nreg = Elements(r600_shader_resource); + + for (int i = 0; i < nreg; i++) { + r600_shader_resource[i].offset += offset; + } + return r600_context_add_block(ctx, r600_shader_resource, nreg); +} + +/* SHADER SAMPLER R600/R700 */ +static int r600_state_sampler_init(struct r600_context *ctx, u32 offset) +{ + struct r600_reg r600_shader_sampler[] = { + {PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, + {PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, + {PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, + }; + unsigned nreg = Elements(r600_shader_sampler); + + for (int i = 0; i < nreg; i++) { + r600_shader_sampler[i].offset += offset; + } + return r600_context_add_block(ctx, r600_shader_sampler, nreg); +} + +/* SHADER SAMPLER BORDER R600/R700 */ +static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 offset, unsigned id) +{ + struct r600_reg r600_shader_sampler_border[] = { + {PKT3_SET_CONFIG_REG, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, 0, R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, 0, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, 0, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, 0, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, + }; + unsigned nreg = Elements(r600_shader_sampler_border); + unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C; + struct r600_range *range; + struct r600_block *block; + int r; + + for (int i = 0; i < nreg; i++) { + r600_shader_sampler_border[i].offset -= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX; + r600_shader_sampler_border[i].offset += fake_offset; + } + r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg); + if (r) { + return r; + } + /* set proper offset */ + range = &ctx->range[CTX_RANGE_ID(ctx, r600_shader_sampler_border[0].offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, r600_shader_sampler_border[0].offset)]; + block->pm4[1] = (offset - EVERGREEN_CONFIG_REG_OFFSET) >> 2; + return 0; +} + +static int evergreen_loop_const_init(struct r600_context *ctx, u32 offset) +{ + unsigned nreg = 32; + struct r600_reg r600_loop_consts[32]; + int i; + + for (i = 0; i < nreg; i++) { + r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST; + r600_loop_consts[i].offset_base = EVERGREEN_LOOP_CONST_OFFSET; + r600_loop_consts[i].offset = EVERGREEN_LOOP_CONST_OFFSET + ((offset + i) * 4); + r600_loop_consts[i].need_bo = 0; + r600_loop_consts[i].flush_flags = 0; + } + return r600_context_add_block(ctx, r600_loop_consts, nreg); +} + +int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon) +{ + int r; + + memset(ctx, 0, sizeof(struct r600_context)); + ctx->radeon = radeon; + LIST_INITHEAD(&ctx->query_list); + + /* initialize hash */ + ctx->hash_size = 19; + ctx->hash_shift = 11; + for (int i = 0; i < 256; i++) { + ctx->range[i].start_offset = i << ctx->hash_shift; + ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1; + ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*)); + if (ctx->range[i].blocks == NULL) { + return -ENOMEM; + } + } + + /* add blocks */ + r = r600_context_add_block(ctx, evergreen_config_reg_list, + Elements(evergreen_config_reg_list)); + if (r) + goto out_err; + r = r600_context_add_block(ctx, evergreen_context_reg_list, + Elements(evergreen_context_reg_list)); + if (r) + goto out_err; + r = r600_context_add_block(ctx, evergreen_ctl_const_list, + Elements(evergreen_ctl_const_list)); + if (r) + goto out_err; + + + /* PS SAMPLER */ + for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) { + r = r600_state_sampler_init(ctx, offset); + if (r) + goto out_err; + } + /* VS SAMPLER */ + for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) { + r = r600_state_sampler_init(ctx, offset); + if (r) + goto out_err; + } + /* PS SAMPLER BORDER */ + for (int j = 0; j < 18; j++) { + r = evergreen_state_sampler_border_init(ctx, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, j); + if (r) + goto out_err; + } + /* VS SAMPLER BORDER */ + for (int j = 0; j < 18; j++) { + r = evergreen_state_sampler_border_init(ctx, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, j); + if (r) + goto out_err; + } + /* PS RESOURCE */ + for (int j = 0, offset = 0; j < 176; j++, offset += 0x20) { + r = evergreen_state_resource_init(ctx, offset); + if (r) + goto out_err; + } + /* VS RESOURCE */ + for (int j = 0, offset = 0x1600; j < 160; j++, offset += 0x20) { + r = evergreen_state_resource_init(ctx, offset); + if (r) + goto out_err; + } + + /* PS loop const */ + evergreen_loop_const_init(ctx, 0); + /* VS loop const */ + evergreen_loop_const_init(ctx, 32); + + /* setup block table */ + ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); + for (int i = 0, c = 0; i < 256; i++) { + for (int j = 0; j < (1 << ctx->hash_shift); j++) { + if (ctx->range[i].blocks[j]) { + assert(c < ctx->nblocks); + ctx->blocks[c++] = ctx->range[i].blocks[j]; + j += (ctx->range[i].blocks[j]->nreg << 2) - 1; + } + } + } + + /* allocate cs variables */ + ctx->nreloc = RADEON_CTX_MAX_PM4; + ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc)); + if (ctx->reloc == NULL) { + r = -ENOMEM; + goto out_err; + } + ctx->bo = calloc(ctx->nreloc, sizeof(void *)); + if (ctx->bo == NULL) { + r = -ENOMEM; + goto out_err; + } + ctx->pm4_ndwords = RADEON_CTX_MAX_PM4; + ctx->pm4 = calloc(ctx->pm4_ndwords, 4); + if (ctx->pm4 == NULL) { + r = -ENOMEM; + goto out_err; + } + /* save 16dwords space for fence mecanism */ + ctx->pm4_ndwords -= 16; + + r = r600_context_init_fence(ctx); + if (r) { + goto out_err; + } + + /* init dirty list */ + LIST_INITHEAD(&ctx->dirty); + return 0; +out_err: + r600_context_fini(ctx); + return r; +} + +static inline void evergreen_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + if (state == NULL) { + block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); + r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); + LIST_DELINIT(&block->list); + return; + } + block->reg[0] = state->regs[0].value; + block->reg[1] = state->regs[1].value; + block->reg[2] = state->regs[2].value; + block->reg[3] = state->regs[3].value; + block->reg[4] = state->regs[4].value; + block->reg[5] = state->regs[5].value; + block->reg[6] = state->regs[6].value; + block->reg[7] = state->regs[7].value; + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); + r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); + if (state->regs[0].bo) { + /* VERTEX RESOURCE, we preted there is 2 bo to relocate so + * we have single case btw VERTEX & TEXTURE resource + */ + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo); + r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo); + } else { + /* TEXTURE RESOURCE */ + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo); + r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo); + } + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x20 * rid; + + evergreen_context_pipe_state_set_resource(ctx, state, offset); +} + +void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x1600 + 0x20 * rid; + + evergreen_context_pipe_state_set_resource(ctx, state, offset); +} + +static inline void evergreen_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + if (state == NULL) { + block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + LIST_DELINIT(&block->list); + return; + } + block->reg[0] = state->regs[0].value; + block->reg[1] = state->regs[1].value; + block->reg[2] = state->regs[2].value; + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset, unsigned id) +{ + unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C; + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, fake_offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, fake_offset)]; + if (state == NULL) { + block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + LIST_DELINIT(&block->list); + return; + } + if (state->nregs <= 3) { + return; + } + block->reg[0] = id; + block->reg[1] = state->regs[3].value; + block->reg[2] = state->regs[4].value; + block->reg[3] = state->regs[5].value; + block->reg[4] = state->regs[6].value; + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) +{ + unsigned offset; + + offset = 0x0003C000 + id * 0xc; + evergreen_context_pipe_state_set_sampler(ctx, state, offset); + evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, id); +} + +void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) +{ + unsigned offset; + + offset = 0x0003C0D8 + id * 0xc; + evergreen_context_pipe_state_set_sampler(ctx, state, offset); + evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, id); +} + + +void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw) +{ + struct r600_bo *cb[12]; + struct r600_bo *db; + unsigned ndwords = 9, flush; + struct r600_block *dirty_block = NULL; + struct r600_block *next_block; + + if (draw->indices) { + ndwords = 13; + /* make sure there is enough relocation space before scheduling draw */ + if (ctx->creloc >= (ctx->nreloc - 1)) { + r600_context_flush(ctx); + } + } + + /* find number of color buffer */ + db = r600_context_reg_bo(ctx, R_028048_DB_Z_READ_BASE); + cb[0] = r600_context_reg_bo(ctx, R_028C60_CB_COLOR0_BASE); + cb[1] = r600_context_reg_bo(ctx, R_028C9C_CB_COLOR1_BASE); + cb[2] = r600_context_reg_bo(ctx, R_028CD8_CB_COLOR2_BASE); + cb[3] = r600_context_reg_bo(ctx, R_028D14_CB_COLOR3_BASE); + cb[4] = r600_context_reg_bo(ctx, R_028D50_CB_COLOR4_BASE); + cb[5] = r600_context_reg_bo(ctx, R_028D8C_CB_COLOR5_BASE); + cb[6] = r600_context_reg_bo(ctx, R_028DC8_CB_COLOR6_BASE); + cb[7] = r600_context_reg_bo(ctx, R_028E04_CB_COLOR7_BASE); + cb[8] = r600_context_reg_bo(ctx, R_028E40_CB_COLOR8_BASE); + cb[9] = r600_context_reg_bo(ctx, R_028E5C_CB_COLOR9_BASE); + cb[10] = r600_context_reg_bo(ctx, R_028E78_CB_COLOR10_BASE); + cb[11] = r600_context_reg_bo(ctx, R_028E94_CB_COLOR11_BASE); + for (int i = 0; i < 12; i++) { + if (cb[i]) { + ndwords += 7; + } + } + if (db) + ndwords += 7; + + /* queries need some special values */ + if (ctx->num_query_running) { + r600_context_reg(ctx, + R_028004_DB_COUNT_CONTROL, + S_028004_PERFECT_ZPASS_COUNTS(1), + S_028004_PERFECT_ZPASS_COUNTS(1)); + r600_context_reg(ctx, + R_02800C_DB_RENDER_OVERRIDE, + S_02800C_NOOP_CULL_DISABLE(1), + S_02800C_NOOP_CULL_DISABLE(1)); + } + + if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) { + /* need to flush */ + r600_context_flush(ctx); + } + /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */ + if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) { + R600_ERR("context is too big to be scheduled\n"); + return; + } + + /* enough room to copy packet */ + LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty,list) { + r600_context_block_emit_dirty(ctx, dirty_block); + } + + /* draw packet */ + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0); + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0); + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances; + if (draw->indices) { + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3); + ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices); + ctx->pm4[ctx->pm4_cdwords++] = 0; + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices; + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = 0; + r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices); + } else { + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1); + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices; + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; + } + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0); + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; + + /* flush color buffer */ + for (int i = 0; i < 12; i++) { + if (cb[i]) { + if (i > 7) { + flush = (S_0085F0_CB8_DEST_BASE_ENA(1) << (i - 8)) | + S_0085F0_CB_ACTION_ENA(1); + } else { + flush = (S_0085F0_CB0_DEST_BASE_ENA(1) << i) | + S_0085F0_CB_ACTION_ENA(1); + } + r600_context_bo_flush(ctx, flush, 0, cb[i]); + } + } + if (db) { + r600_context_bo_flush(ctx, + S_0085F0_DB_ACTION_ENA(1) | + S_0085F0_DB_DEST_BASE_ENA(1), + 0, db); + } + + /* all dirty state have been scheduled in current cs */ + ctx->pm4_dirty_cdwords = 0; +} + +static inline void evergreen_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + block->reg[0] = state->regs[0].value; + block->reg[1] = state->regs[1].value; + block->reg[2] = state->regs[2].value; + block->reg[3] = state->regs[3].value; + block->reg[4] = state->regs[4].value; + block->reg[5] = state->regs[5].value; + block->reg[6] = state->regs[6].value; + block->reg[7] = state->regs[7].value; + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); + r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); + if (state->regs[0].bo) { + /* VERTEX RESOURCE, we preted there is 2 bo to relocate so + * we have single case btw VERTEX & TEXTURE resource + */ + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo); + r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo); + } else { + /* TEXTURE RESOURCE */ + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo); + r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo); + } + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_030000_RESOURCE0_WORD0 + 0x20 * rid; + + evergreen_resource_set(ctx, state, offset); +} + +void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_030000_RESOURCE0_WORD0 + 0x1600 + 0x20 * rid; + + evergreen_resource_set(ctx, state, offset); +} diff --git a/src/gallium/winsys/r600/drm/r600.c b/src/gallium/winsys/r600/drm/r600.c new file mode 100644 index 00000000000..496547ca994 --- /dev/null +++ b/src/gallium/winsys/r600/drm/r600.c @@ -0,0 +1,168 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include "xf86drm.h" +#include "radeon_drm.h" +#include "pipe/p_compiler.h" +#include "util/u_inlines.h" +#include <pipebuffer/pb_bufmgr.h> +#include "r600_priv.h" + +enum radeon_family r600_get_family(struct radeon *r600) +{ + return r600->family; +} + +enum chip_class r600_get_family_class(struct radeon *radeon) +{ + return radeon->chip_class; +} + +static int r600_get_device(struct radeon *r600) +{ + struct drm_radeon_info info; + + r600->device = 0; + info.request = RADEON_INFO_DEVICE_ID; + info.value = (uintptr_t)&r600->device; + return drmCommandWriteRead(r600->fd, DRM_RADEON_INFO, &info, sizeof(struct drm_radeon_info)); +} + +struct radeon *r600_new(int fd, unsigned device) +{ + struct radeon *r600; + int r; + + r600 = calloc(1, sizeof(*r600)); + if (r600 == NULL) { + return NULL; + } + r600->fd = fd; + r600->device = device; + if (fd >= 0) { + r = r600_get_device(r600); + if (r) { + R600_ERR("Failed to get device id\n"); + r600_delete(r600); + return NULL; + } + } + r600->family = radeon_family_from_device(r600->device); + if (r600->family == CHIP_UNKNOWN) { + R600_ERR("Unknown chipset 0x%04X\n", r600->device); + r600_delete(r600); + return NULL; + } + switch (r600->family) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + break; + case CHIP_R100: + case CHIP_RV100: + case CHIP_RS100: + case CHIP_RV200: + case CHIP_RS200: + case CHIP_R200: + case CHIP_RV250: + case CHIP_RS300: + case CHIP_RV280: + case CHIP_R300: + case CHIP_R350: + case CHIP_RV350: + case CHIP_RV380: + case CHIP_R420: + case CHIP_R423: + case CHIP_RV410: + case CHIP_RS400: + case CHIP_RS480: + case CHIP_RS600: + case CHIP_RS690: + case CHIP_RS740: + case CHIP_RV515: + case CHIP_R520: + case CHIP_RV530: + case CHIP_RV560: + case CHIP_RV570: + case CHIP_R580: + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + default: + R600_ERR("unknown or unsupported chipset 0x%04X\n", r600->device); + break; + } + + /* setup class */ + switch (r600->family) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + r600->chip_class = R600; + break; + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + r600->chip_class = R700; + break; + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + r600->chip_class = EVERGREEN; + break; + default: + R600_ERR("unknown or unsupported chipset 0x%04X\n", r600->device); + break; + } + + return r600; +} + +void r600_delete(struct radeon *r600) +{ + if (r600 == NULL) + return; + drmClose(r600->fd); + free(r600); +} diff --git a/src/gallium/winsys/r600/drm/r600_bo.c b/src/gallium/winsys/r600/drm/r600_bo.c new file mode 100644 index 00000000000..9498f3a82ea --- /dev/null +++ b/src/gallium/winsys/r600/drm/r600_bo.c @@ -0,0 +1,122 @@ +/* + * Copyright 2010 Dave Airlie + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Dave Airlie + */ +#include <pipe/p_compiler.h> +#include <pipe/p_screen.h> +#include <pipebuffer/pb_bufmgr.h> +#include "r600_priv.h" + +struct r600_bo *r600_bo(struct radeon *radeon, + unsigned size, unsigned alignment, unsigned usage) +{ + struct r600_bo *ws_bo = calloc(1, sizeof(struct r600_bo)); + struct pb_desc desc; + struct pb_manager *man; + + desc.alignment = alignment; + desc.usage = usage; + ws_bo->size = size; + + if (usage & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) + man = radeon->cman; + else + man = radeon->kman; + + ws_bo->pb = man->create_buffer(man, size, &desc); + if (ws_bo->pb == NULL) { + free(ws_bo); + return NULL; + } + + pipe_reference_init(&ws_bo->reference, 1); + return ws_bo; +} + +struct r600_bo *r600_bo_handle(struct radeon *radeon, + unsigned handle) +{ + struct r600_bo *ws_bo = calloc(1, sizeof(struct r600_bo)); + struct radeon_bo *bo; + + ws_bo->pb = radeon_bo_pb_create_buffer_from_handle(radeon->kman, handle); + if (!ws_bo->pb) { + free(ws_bo); + return NULL; + } + bo = radeon_bo_pb_get_bo(ws_bo->pb); + ws_bo->size = bo->size; + pipe_reference_init(&ws_bo->reference, 1); + return ws_bo; +} + +void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx) +{ + return pb_map(bo->pb, usage, ctx); +} + +void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo) +{ + pb_unmap(bo->pb); +} + +static void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo) +{ + if (bo->pb) + pb_reference(&bo->pb, NULL); + free(bo); +} + +void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, + struct r600_bo *src) +{ + struct r600_bo *old = *dst; + + if (pipe_reference(&(*dst)->reference, &src->reference)) { + r600_bo_destroy(radeon, old); + } + *dst = src; +} + +unsigned r600_bo_get_handle(struct r600_bo *pb_bo) +{ + struct radeon_bo *bo; + + bo = radeon_bo_pb_get_bo(pb_bo->pb); + if (!bo) + return 0; + + return bo->handle; +} + +unsigned r600_bo_get_size(struct r600_bo *pb_bo) +{ + struct radeon_bo *bo; + + bo = radeon_bo_pb_get_bo(pb_bo->pb); + if (!bo) + return 0; + + return bo->size; +} diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c new file mode 100644 index 00000000000..5f175a4df98 --- /dev/null +++ b/src/gallium/winsys/r600/drm/r600_drm.c @@ -0,0 +1,187 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + * Corbin Simpson <[email protected]> + * Joakim Sindholt <[email protected]> + */ +#include <stdio.h> +#include <errno.h> +#include <sys/ioctl.h> +#include "util/u_inlines.h" +#include "util/u_debug.h" +#include <pipebuffer/pb_bufmgr.h> +#include "r600.h" +#include "r600_priv.h" +#include "r600_drm_public.h" +#include "xf86drm.h" +#include "radeon_drm.h" + +static int radeon_get_device(struct radeon *radeon) +{ + struct drm_radeon_info info; + int r; + + radeon->device = 0; + info.request = RADEON_INFO_DEVICE_ID; + info.value = (uintptr_t)&radeon->device; + r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info, + sizeof(struct drm_radeon_info)); + return r; +} + +struct radeon *radeon_new(int fd, unsigned device) +{ + struct radeon *radeon; + int r; + + radeon = calloc(1, sizeof(*radeon)); + if (radeon == NULL) { + return NULL; + } + radeon->fd = fd; + radeon->device = device; + radeon->refcount = 1; + if (fd >= 0) { + r = radeon_get_device(radeon); + if (r) { + fprintf(stderr, "Failed to get device id\n"); + return radeon_decref(radeon); + } + } + radeon->family = radeon_family_from_device(radeon->device); + if (radeon->family == CHIP_UNKNOWN) { + fprintf(stderr, "Unknown chipset 0x%04X\n", radeon->device); + return radeon_decref(radeon); + } + switch (radeon->family) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + break; + case CHIP_R100: + case CHIP_RV100: + case CHIP_RS100: + case CHIP_RV200: + case CHIP_RS200: + case CHIP_R200: + case CHIP_RV250: + case CHIP_RS300: + case CHIP_RV280: + case CHIP_R300: + case CHIP_R350: + case CHIP_RV350: + case CHIP_RV380: + case CHIP_R420: + case CHIP_R423: + case CHIP_RV410: + case CHIP_RS400: + case CHIP_RS480: + case CHIP_RS600: + case CHIP_RS690: + case CHIP_RS740: + case CHIP_RV515: + case CHIP_R520: + case CHIP_RV530: + case CHIP_RV560: + case CHIP_RV570: + case CHIP_R580: + default: + fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n", + __func__, radeon->device); + break; + } + + /* setup class */ + switch (radeon->family) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + radeon->chip_class = R600; + break; + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + radeon->chip_class = R700; + break; + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + radeon->chip_class = EVERGREEN; + break; + default: + fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n", + __func__, radeon->device); + break; + } + + radeon->kman = radeon_bo_pbmgr_create(radeon); + if (!radeon->kman) + return NULL; + radeon->cman = pb_cache_manager_create(radeon->kman, 100000); + if (!radeon->cman) + return NULL; + return radeon; +} + +struct radeon *r600_drm_winsys_create(int drmfd) +{ + return radeon_new(drmfd, 0); +} + +struct radeon *radeon_decref(struct radeon *radeon) +{ + if (radeon == NULL) + return NULL; + if (--radeon->refcount > 0) { + return NULL; + } + + radeon->cman->destroy(radeon->cman); + radeon->kman->destroy(radeon->kman); + drmClose(radeon->fd); + free(radeon); + return NULL; +} diff --git a/src/gallium/winsys/r600/drm/r600_drm_public.h b/src/gallium/winsys/r600/drm/r600_drm_public.h new file mode 100644 index 00000000000..cfce8df9c2c --- /dev/null +++ b/src/gallium/winsys/r600/drm/r600_drm_public.h @@ -0,0 +1,33 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef R600_DRM_PUBLIC_H +#define R600_DRM_PUBLIC_H + +struct radeon; + +struct radeon *r600_drm_winsys_create(int drmFD); + +#endif diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c new file mode 100644 index 00000000000..2521ff96473 --- /dev/null +++ b/src/gallium/winsys/r600/drm/r600_hw_context.c @@ -0,0 +1,1362 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <errno.h> +#include <stdint.h> +#include <string.h> +#include <stdlib.h> +#include <assert.h> +#include "xf86drm.h" +#include "r600.h" +#include "r600d.h" +#include "radeon_drm.h" +#include "bof.h" +#include "pipe/p_compiler.h" +#include "util/u_inlines.h" +#include "util/u_memory.h" +#include <pipebuffer/pb_bufmgr.h> +#include "r600_priv.h" + +#define GROUP_FORCE_NEW_BLOCK 0 + +int r600_context_init_fence(struct r600_context *ctx) +{ + ctx->fence = 1; + ctx->fence_bo = r600_bo(ctx->radeon, 4096, 0, 0); + if (ctx->fence_bo == NULL) { + return -ENOMEM; + } + ctx->cfence = r600_bo_map(ctx->radeon, ctx->fence_bo, PB_USAGE_UNSYNCHRONIZED, NULL); + *ctx->cfence = 0; + LIST_INITHEAD(&ctx->fenced_bo); + return 0; +} + +static void INLINE r600_context_update_fenced_list(struct r600_context *ctx) +{ + for (int i = 0; i < ctx->creloc; i++) { + if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist)) + LIST_DELINIT(&ctx->bo[i]->fencedlist); + LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo); + ctx->bo[i]->fence = ctx->fence; + ctx->bo[i]->ctx = ctx; + } +} + +static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsigned fence) +{ + struct radeon_bo *bo = NULL; + struct radeon_bo *tmp; + + LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) { + if (bo->fence <= *ctx->cfence) { + LIST_DELINIT(&bo->fencedlist); + bo->fence = 0; + } else { + bo->fence = fence; + } + } +} + +int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg) +{ + struct r600_block *block; + struct r600_range *range; + int offset; + + for (unsigned i = 0, n = 0; i < nreg; i += n) { + u32 j; + + /* ignore new block balise */ + if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) { + n = 1; + continue; + } + + /* register that need relocation are in their own group */ + /* find number of consecutive registers */ + n = 0; + offset = reg[i].offset; + while (reg[i + n].offset == offset) { + n++; + offset += 4; + if ((n + i) >= nreg) + break; + if (n >= (R600_BLOCK_MAX_REG - 2)) + break; + } + + /* allocate new block */ + block = calloc(1, sizeof(struct r600_block)); + if (block == NULL) { + return -ENOMEM; + } + ctx->nblocks++; + for (int j = 0; j < n; j++) { + range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)]; + range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block; + } + + /* initialize block */ + block->start_offset = reg[i].offset; + block->pm4[block->pm4_ndwords++] = PKT3(reg[i].opcode, n); + block->pm4[block->pm4_ndwords++] = (block->start_offset - reg[i].offset_base) >> 2; + block->reg = &block->pm4[block->pm4_ndwords]; + block->pm4_ndwords += n; + block->nreg = n; + LIST_INITHEAD(&block->list); + + for (j = 0; j < n; j++) { + if (reg[i+j].need_bo) { + block->nbo++; + assert(block->nbo < R600_BLOCK_MAX_BO); + block->pm4_bo_index[j] = block->nbo; + block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0); + block->pm4[block->pm4_ndwords++] = 0x00000000; + block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags; + block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask; + block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1; + } + } + for (j = 0; j < n; j++) { + if (reg[i+j].flush_flags) { + block->pm4_flush_ndwords += 7; + } + } + /* check that we stay in limit */ + assert(block->pm4_ndwords < R600_BLOCK_MAX_REG); + } + return 0; +} + +/* R600/R700 configuration */ +static const struct r600_reg r600_config_reg_list[] = { + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009508_TA_CNTL_AUX, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009714_VC_ENHANCE, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009830_DB_DEBUG, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0, 0}, +}; + +static const struct r600_reg r600_ctl_const_list[] = { + {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, + {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, +}; + +static const struct r600_reg r600_context_reg_list[] = { + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB0_VGT_STRMOUT_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028040_CB_COLOR0_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028060_CB_COLOR0_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028080_CB_COLOR0_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E0_CB_COLOR0_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C0_CB_COLOR0_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028100_CB_COLOR0_MASK, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028044_CB_COLOR1_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028064_CB_COLOR1_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028084_CB_COLOR1_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E4_CB_COLOR1_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C4_CB_COLOR1_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028104_CB_COLOR1_MASK, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028048_CB_COLOR2_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028068_CB_COLOR2_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028088_CB_COLOR2_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E8_CB_COLOR2_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C8_CB_COLOR2_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028108_CB_COLOR2_MASK, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02804C_CB_COLOR3_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02806C_CB_COLOR3_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02808C_CB_COLOR3_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280EC_CB_COLOR3_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280CC_CB_COLOR3_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02810C_CB_COLOR3_MASK, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028050_CB_COLOR4_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028070_CB_COLOR4_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028090_CB_COLOR4_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F0_CB_COLOR4_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D0_CB_COLOR4_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028110_CB_COLOR4_MASK, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028054_CB_COLOR5_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028074_CB_COLOR5_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028094_CB_COLOR5_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F4_CB_COLOR5_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D4_CB_COLOR5_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028114_CB_COLOR5_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028058_CB_COLOR6_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028078_CB_COLOR6_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028098_CB_COLOR6_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F8_CB_COLOR6_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D8_CB_COLOR6_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028118_CB_COLOR6_MASK, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02805C_CB_COLOR7_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02807C_CB_COLOR7_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02809C_CB_COLOR7_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280FC_CB_COLOR7_FRAG, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280DC_CB_COLOR7_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02811C_CB_COLOR7_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028120_CB_CLEAR_RED, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028124_CB_CLEAR_GREEN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028128_CB_CLEAR_BLUE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02812C_CB_CLEAR_ALPHA, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028424_CB_FOG_RED, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028428_CB_FOG_GREEN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02842C_CB_FOG_BLUE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0287A0_CB_SHADER_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028804_CB_BLEND_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C34_CB_CLRCMP_SRC, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C38_CB_CLRCMP_DST, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C3C_CB_CLRCMP_MSK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C48_PA_SC_AA_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02800C_DB_DEPTH_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028000_DB_DEPTH_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028004_DB_DEPTH_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028010_DB_DEPTH_INFO, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D0C_DB_RENDER_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D24_DB_HTILE_SURFACE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E20_PA_CL_UCP0_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E24_PA_CL_UCP0_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E28_PA_CL_UCP0_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E2C_PA_CL_UCP0_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E30_PA_CL_UCP1_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E34_PA_CL_UCP1_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E38_PA_CL_UCP1_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E3C_PA_CL_UCP1_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E40_PA_CL_UCP2_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E44_PA_CL_UCP2_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E48_PA_CL_UCP2_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E4C_PA_CL_UCP2_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E50_PA_CL_UCP3_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E54_PA_CL_UCP3_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E58_PA_CL_UCP3_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E5C_PA_CL_UCP3_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E60_PA_CL_UCP4_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E64_PA_CL_UCP4_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E68_PA_CL_UCP4_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E6C_PA_CL_UCP4_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E70_PA_CL_UCP5_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E74_PA_CL_UCP5_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E78_PA_CL_UCP5_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E7C_PA_CL_UCP5_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028614_SPI_VS_OUT_ID_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028618_SPI_VS_OUT_ID_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_4, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_5, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_7, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_8, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_9, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028858_SQ_PGM_START_VS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028894_SQ_PGM_START_FS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0}, +}; + +/* SHADER RESOURCE R600/R700 */ +static int r600_state_resource_init(struct r600_context *ctx, u32 offset) +{ + struct r600_reg r600_shader_resource[] = { + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038000_RESOURCE0_WORD0, 0, 0, 0}, + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038004_RESOURCE0_WORD1, 0, 0, 0}, + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038008_RESOURCE0_WORD2, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_03800C_RESOURCE0_WORD3, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038010_RESOURCE0_WORD4, 0, 0, 0}, + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038014_RESOURCE0_WORD5, 0, 0, 0}, + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038018_RESOURCE0_WORD6, 0, 0, 0}, + }; + unsigned nreg = Elements(r600_shader_resource); + + for (int i = 0; i < nreg; i++) { + r600_shader_resource[i].offset += offset; + } + return r600_context_add_block(ctx, r600_shader_resource, nreg); +} + +/* SHADER SAMPLER R600/R700 */ +static int r600_state_sampler_init(struct r600_context *ctx, u32 offset) +{ + struct r600_reg r600_shader_sampler[] = { + {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, + {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, + {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, + }; + unsigned nreg = Elements(r600_shader_sampler); + + for (int i = 0; i < nreg; i++) { + r600_shader_sampler[i].offset += offset; + } + return r600_context_add_block(ctx, r600_shader_sampler, nreg); +} + +/* SHADER SAMPLER BORDER R600/R700 */ +static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset) +{ + struct r600_reg r600_shader_sampler_border[] = { + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, + }; + unsigned nreg = Elements(r600_shader_sampler_border); + + for (int i = 0; i < nreg; i++) { + r600_shader_sampler_border[i].offset += offset; + } + return r600_context_add_block(ctx, r600_shader_sampler_border, nreg); +} + +static int r600_loop_const_init(struct r600_context *ctx, u32 offset) +{ + unsigned nreg = 32; + struct r600_reg r600_loop_consts[32]; + int i; + + for (i = 0; i < nreg; i++) { + r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST; + r600_loop_consts[i].offset_base = R600_LOOP_CONST_OFFSET; + r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4); + r600_loop_consts[i].need_bo = 0; + r600_loop_consts[i].flush_flags = 0; + r600_loop_consts[i].flush_mask = 0; + } + return r600_context_add_block(ctx, r600_loop_consts, nreg); +} + +/* initialize */ +void r600_context_fini(struct r600_context *ctx) +{ + struct r600_block *block; + struct r600_range *range; + + for (int i = 0; i < 256; i++) { + for (int j = 0; j < (1 << ctx->hash_shift); j++) { + block = ctx->range[i].blocks[j]; + if (block) { + for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) { + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + range->blocks[CTX_BLOCK_ID(ctx, offset)] = NULL; + } + free(block); + } + } + free(ctx->range[i].blocks); + } + free(ctx->reloc); + free(ctx->pm4); + if (ctx->fence_bo) { + r600_bo_reference(ctx->radeon, &ctx->fence_bo, NULL); + } + memset(ctx, 0, sizeof(struct r600_context)); +} + +int r600_context_init(struct r600_context *ctx, struct radeon *radeon) +{ + int r; + + memset(ctx, 0, sizeof(struct r600_context)); + ctx->radeon = radeon; + LIST_INITHEAD(&ctx->query_list); + + /* initialize hash */ + ctx->hash_size = 19; + ctx->hash_shift = 11; + for (int i = 0; i < 256; i++) { + ctx->range[i].start_offset = i << ctx->hash_shift; + ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1; + ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*)); + if (ctx->range[i].blocks == NULL) { + return -ENOMEM; + } + } + + /* add blocks */ + r = r600_context_add_block(ctx, r600_config_reg_list, + Elements(r600_config_reg_list)); + if (r) + goto out_err; + r = r600_context_add_block(ctx, r600_context_reg_list, + Elements(r600_context_reg_list)); + if (r) + goto out_err; + r = r600_context_add_block(ctx, r600_ctl_const_list, + Elements(r600_ctl_const_list)); + if (r) + goto out_err; + + /* PS SAMPLER BORDER */ + for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) { + r = r600_state_sampler_border_init(ctx, offset); + if (r) + goto out_err; + } + + /* VS SAMPLER BORDER */ + for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) { + r = r600_state_sampler_border_init(ctx, offset); + if (r) + goto out_err; + } + /* PS SAMPLER */ + for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) { + r = r600_state_sampler_init(ctx, offset); + if (r) + goto out_err; + } + /* VS SAMPLER */ + for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) { + r = r600_state_sampler_init(ctx, offset); + if (r) + goto out_err; + } + /* PS RESOURCE */ + for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) { + r = r600_state_resource_init(ctx, offset); + if (r) + goto out_err; + } + /* VS RESOURCE */ + for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) { + r = r600_state_resource_init(ctx, offset); + if (r) + goto out_err; + } + + /* PS loop const */ + r600_loop_const_init(ctx, 0); + /* VS loop const */ + r600_loop_const_init(ctx, 32); + + /* setup block table */ + ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); + for (int i = 0, c = 0; i < 256; i++) { + for (int j = 0, add; j < (1 << ctx->hash_shift); j++) { + if (ctx->range[i].blocks[j]) { + add = 1; + for (int k = 0; k < c; k++) { + if (ctx->blocks[k] == ctx->range[i].blocks[j]) { + add = 0; + break; + } + } + if (add) { + assert(c < ctx->nblocks); + ctx->blocks[c++] = ctx->range[i].blocks[j]; + j += (ctx->range[i].blocks[j]->nreg << 2) - 1; + } + } + } + } + + /* allocate cs variables */ + ctx->nreloc = RADEON_CTX_MAX_PM4; + ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc)); + if (ctx->reloc == NULL) { + r = -ENOMEM; + goto out_err; + } + ctx->bo = calloc(ctx->nreloc, sizeof(void *)); + if (ctx->bo == NULL) { + r = -ENOMEM; + goto out_err; + } + ctx->pm4_ndwords = RADEON_CTX_MAX_PM4; + ctx->pm4 = calloc(ctx->pm4_ndwords, 4); + if (ctx->pm4 == NULL) { + r = -ENOMEM; + goto out_err; + } + /* save 16dwords space for fence mecanism */ + ctx->pm4_ndwords -= 16; + + r = r600_context_init_fence(ctx); + if (r) { + goto out_err; + } + + /* init dirty list */ + LIST_INITHEAD(&ctx->dirty); + return 0; +out_err: + r600_context_fini(ctx); + return r; +} + +void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags, + unsigned flush_mask, struct r600_bo *rbo) +{ + struct radeon_bo *bo; + + bo = r600_bo_get_bo(rbo); + /* if bo has already been flush */ + if (!(bo->last_flush ^ flush_flags)) { + bo->last_flush &= flush_mask; + return; + } + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3); + ctx->pm4[ctx->pm4_cdwords++] = flush_flags; + ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8; + ctx->pm4[ctx->pm4_cdwords++] = 0x00000000; + ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = bo->reloc_id; + bo->last_flush = (bo->last_flush | flush_flags) & flush_mask; +} + +void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo) +{ + struct radeon_bo *bo; + + bo = r600_bo_get_bo(rbo); + assert(bo != NULL); + if (bo->reloc) { + *pm4 = bo->reloc_id; + return; + } + bo->reloc = &ctx->reloc[ctx->creloc]; + bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4; + ctx->reloc[ctx->creloc].handle = bo->handle; + ctx->reloc[ctx->creloc].read_domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; + ctx->reloc[ctx->creloc].write_domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; + ctx->reloc[ctx->creloc].flags = 0; + radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo); + ctx->creloc++; + /* set PKT3 to point to proper reloc */ + *pm4 = bo->reloc_id; +} + +void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state) +{ + struct r600_range *range; + struct r600_block *block; + + for (int i = 0; i < state->nregs; i++) { + unsigned id; + + range = &ctx->range[CTX_RANGE_ID(ctx, state->regs[i].offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, state->regs[i].offset)]; + id = (state->regs[i].offset - block->start_offset) >> 2; + block->reg[id] &= ~state->regs[i].mask; + block->reg[id] |= state->regs[i].value; + if (block->pm4_bo_index[id]) { + /* find relocation */ + id = block->pm4_bo_index[id]; + r600_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo); + } + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } + } +} + +static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + if (state == NULL) { + block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); + r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); + LIST_DELINIT(&block->list); + return; + } + block->reg[0] = state->regs[0].value; + block->reg[1] = state->regs[1].value; + block->reg[2] = state->regs[2].value; + block->reg[3] = state->regs[3].value; + block->reg[4] = state->regs[4].value; + block->reg[5] = state->regs[5].value; + block->reg[6] = state->regs[6].value; + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); + r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); + if (state->regs[0].bo) { + /* VERTEX RESOURCE, we preted there is 2 bo to relocate so + * we have single case btw VERTEX & TEXTURE resource + */ + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo); + r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo); + } else { + /* TEXTURE RESOURCE */ + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo); + r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo); + } + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid; + + r600_context_pipe_state_set_resource(ctx, state, offset); +} + +void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid; + + r600_context_pipe_state_set_resource(ctx, state, offset); +} + +static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + if (state == NULL) { + block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + LIST_DELINIT(&block->list); + return; + } + block->reg[0] = state->regs[0].value; + block->reg[1] = state->regs[1].value; + block->reg[2] = state->regs[2].value; + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + if (state == NULL) { + block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + LIST_DELINIT(&block->list); + return; + } + if (state->nregs <= 3) { + return; + } + block->reg[0] = state->regs[3].value; + block->reg[1] = state->regs[4].value; + block->reg[2] = state->regs[5].value; + block->reg[3] = state->regs[6].value; + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) +{ + unsigned offset; + + offset = 0x0003C000 + id * 0xc; + r600_context_pipe_state_set_sampler(ctx, state, offset); + offset = 0x0000A400 + id * 0x10; + r600_context_pipe_state_set_sampler_border(ctx, state, offset); +} + +void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) +{ + unsigned offset; + + offset = 0x0003C0D8 + id * 0xc; + r600_context_pipe_state_set_sampler(ctx, state, offset); + offset = 0x0000A600 + id * 0x10; + r600_context_pipe_state_set_sampler_border(ctx, state, offset); +} + +struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + unsigned id; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + offset -= block->start_offset; + id = block->pm4_bo_index[offset >> 2]; + if (block->reloc[id].bo) { + return block->reloc[id].bo; + } + return NULL; +} + +void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw) +{ + struct r600_bo *cb[8]; + struct r600_bo *db; + unsigned ndwords = 9; + struct r600_block *dirty_block = NULL; + struct r600_block *next_block; + + if (draw->indices) { + ndwords = 13; + /* make sure there is enough relocation space before scheduling draw */ + if (ctx->creloc >= (ctx->nreloc - 1)) { + r600_context_flush(ctx); + } + } + + /* find number of color buffer */ + db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE); + cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE); + cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE); + cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE); + cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE); + cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE); + cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE); + cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE); + cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE); + for (int i = 0; i < 8; i++) { + if (cb[i]) { + ndwords += 7; + } + } + if (db) + ndwords += 7; + + /* queries need some special values */ + if (ctx->num_query_running) { + if (ctx->radeon->family >= CHIP_RV770) { + r600_context_reg(ctx, + R_028D0C_DB_RENDER_CONTROL, + S_028D0C_R700_PERFECT_ZPASS_COUNTS(1), + S_028D0C_R700_PERFECT_ZPASS_COUNTS(1)); + } + r600_context_reg(ctx, + R_028D10_DB_RENDER_OVERRIDE, + S_028D10_NOOP_CULL_DISABLE(1), + S_028D10_NOOP_CULL_DISABLE(1)); + } + + if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) { + /* need to flush */ + r600_context_flush(ctx); + } + /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */ + if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) { + R600_ERR("context is too big to be scheduled\n"); + return; + } + + /* enough room to copy packet */ + LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty,list) { + r600_context_block_emit_dirty(ctx, dirty_block); + } + + /* draw packet */ + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0); + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0); + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances; + if (draw->indices) { + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3); + ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices); + ctx->pm4[ctx->pm4_cdwords++] = 0; + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices; + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = 0; + r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices); + } else { + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1); + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices; + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; + } + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0); + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; + + /* flush color buffer */ + for (int i = 0; i < 8; i++) { + if (cb[i]) { + r600_context_bo_flush(ctx, + (S_0085F0_CB0_DEST_BASE_ENA(1) << i) | + S_0085F0_CB_ACTION_ENA(1), + 0, cb[i]); + } + } + if (db) { + r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1), 0, db); + } + + /* all dirty state have been scheduled in current cs */ + ctx->pm4_dirty_cdwords = 0; +} + +void r600_context_flush(struct r600_context *ctx) +{ + struct drm_radeon_cs drmib; + struct drm_radeon_cs_chunk chunks[2]; + uint64_t chunk_array[2]; + unsigned fence; + int r; + + if (!ctx->pm4_cdwords) + return; + + /* suspend queries */ + r600_context_queries_suspend(ctx); + + radeon_bo_pbmgr_flush_maps(ctx->radeon->kman); + + /* emit fence */ + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4); + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT | (5 << 8); + ctx->pm4[ctx->pm4_cdwords++] = 0; + ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24); + ctx->pm4[ctx->pm4_cdwords++] = ctx->fence; + ctx->pm4[ctx->pm4_cdwords++] = 0; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = 0; + r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->fence_bo); + +#if 1 + /* emit cs */ + drmib.num_chunks = 2; + drmib.chunks = (uint64_t)(uintptr_t)chunk_array; + chunks[0].chunk_id = RADEON_CHUNK_ID_IB; + chunks[0].length_dw = ctx->pm4_cdwords; + chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4; + chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS; + chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4; + chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc; + chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0]; + chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1]; + r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib, + sizeof(struct drm_radeon_cs)); +#endif + + r600_context_update_fenced_list(ctx); + + fence = ctx->fence + 1; + if (fence < ctx->fence) { + /* wrap around */ + fence = 1; + r600_context_fence_wraparound(ctx, fence); + } + ctx->fence = fence; + + /* restart */ + for (int i = 0; i < ctx->creloc; i++) { + ctx->bo[i]->reloc = NULL; + ctx->bo[i]->last_flush = 0; + radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL); + } + ctx->creloc = 0; + ctx->pm4_dirty_cdwords = 0; + ctx->pm4_cdwords = 0; + + /* resume queries */ + r600_context_queries_resume(ctx); + + /* set all valid group as dirty so they get reemited on + * next draw command + */ + for (int i = 0; i < ctx->nblocks; i++) { + if (ctx->blocks[i]->status & R600_BLOCK_STATUS_ENABLED) { + if(!(ctx->blocks[i]->status & R600_BLOCK_STATUS_DIRTY)) { + LIST_ADDTAIL(&ctx->blocks[i]->list,&ctx->dirty); + } + ctx->pm4_dirty_cdwords += ctx->blocks[i]->pm4_ndwords + ctx->blocks[i]->pm4_flush_ndwords; + ctx->blocks[i]->status |= R600_BLOCK_STATUS_DIRTY; + } + } +} + +void r600_context_dump_bof(struct r600_context *ctx, const char *file) +{ + bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root; + unsigned i; + + root = device_id = bcs = blob = array = bo = size = handle = NULL; + root = bof_object(); + if (root == NULL) + goto out_err; + device_id = bof_int32(ctx->radeon->device); + if (device_id == NULL) + goto out_err; + if (bof_object_set(root, "device_id", device_id)) + goto out_err; + bof_decref(device_id); + device_id = NULL; + /* dump relocs */ + blob = bof_blob(ctx->creloc * 16, ctx->reloc); + if (blob == NULL) + goto out_err; + if (bof_object_set(root, "reloc", blob)) + goto out_err; + bof_decref(blob); + blob = NULL; + /* dump cs */ + blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4); + if (blob == NULL) + goto out_err; + if (bof_object_set(root, "pm4", blob)) + goto out_err; + bof_decref(blob); + blob = NULL; + /* dump bo */ + array = bof_array(); + if (array == NULL) + goto out_err; + for (i = 0; i < ctx->creloc; i++) { + struct radeon_bo *rbo = ctx->bo[i]; + bo = bof_object(); + if (bo == NULL) + goto out_err; + size = bof_int32(rbo->size); + if (size == NULL) + goto out_err; + if (bof_object_set(bo, "size", size)) + goto out_err; + bof_decref(size); + size = NULL; + handle = bof_int32(rbo->handle); + if (handle == NULL) + goto out_err; + if (bof_object_set(bo, "handle", handle)) + goto out_err; + bof_decref(handle); + handle = NULL; + radeon_bo_map(ctx->radeon, rbo); + blob = bof_blob(rbo->size, rbo->data); + radeon_bo_unmap(ctx->radeon, rbo); + if (blob == NULL) + goto out_err; + if (bof_object_set(bo, "data", blob)) + goto out_err; + bof_decref(blob); + blob = NULL; + if (bof_array_append(array, bo)) + goto out_err; + bof_decref(bo); + bo = NULL; + } + if (bof_object_set(root, "bo", array)) + goto out_err; + bof_dump_file(root, file); +out_err: + bof_decref(blob); + bof_decref(array); + bof_decref(bo); + bof_decref(size); + bof_decref(handle); + bof_decref(device_id); + bof_decref(root); +} + +static void r600_query_result(struct r600_context *ctx, struct r600_query *query) +{ + u64 start, end; + u32 *results; + int i; + + results = r600_bo_map(ctx->radeon, query->buffer, 0, NULL); + for (i = 0; i < query->num_results; i += 4) { + start = (u64)results[i] | (u64)results[i + 1] << 32; + end = (u64)results[i + 2] | (u64)results[i + 3] << 32; + if ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL)) { + query->result += end - start; + } + } + r600_bo_unmap(ctx->radeon, query->buffer); + query->num_results = 0; +} + +void r600_query_begin(struct r600_context *ctx, struct r600_query *query) +{ + /* query request needs 6 dwords for begin + 6 dwords for end */ + if ((12 + ctx->pm4_cdwords) > ctx->pm4_ndwords) { + /* need to flush */ + r600_context_flush(ctx); + } + + /* if query buffer is full force a flush */ + if (query->num_results >= ((query->buffer_size >> 2) - 2)) { + r600_context_flush(ctx); + r600_query_result(ctx, query); + } + + /* emit begin query */ + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2); + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE; + ctx->pm4[ctx->pm4_cdwords++] = query->num_results + r600_bo_offset(query->buffer); + ctx->pm4[ctx->pm4_cdwords++] = 0; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = 0; + r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer); + + query->state |= R600_QUERY_STATE_STARTED; + query->state ^= R600_QUERY_STATE_ENDED; + ctx->num_query_running++; +} + +void r600_query_end(struct r600_context *ctx, struct r600_query *query) +{ + /* emit begin query */ + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2); + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE; + ctx->pm4[ctx->pm4_cdwords++] = query->num_results + 8 + r600_bo_offset(query->buffer); + ctx->pm4[ctx->pm4_cdwords++] = 0; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = 0; + r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer); + + query->num_results += 16; + query->state ^= R600_QUERY_STATE_STARTED; + query->state |= R600_QUERY_STATE_ENDED; + ctx->num_query_running--; +} + +struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type) +{ + struct r600_query *query; + + if (query_type != PIPE_QUERY_OCCLUSION_COUNTER) + return NULL; + + query = calloc(1, sizeof(struct r600_query)); + if (query == NULL) + return NULL; + + query->type = query_type; + query->buffer_size = 4096; + + query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0); + if (!query->buffer) { + free(query); + return NULL; + } + + LIST_ADDTAIL(&query->list, &ctx->query_list); + + return query; +} + +void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query) +{ + r600_bo_reference(ctx->radeon, &query->buffer, NULL); + LIST_DELINIT(&query->list); + free(query); +} + +boolean r600_context_query_result(struct r600_context *ctx, + struct r600_query *query, + boolean wait, void *vresult) +{ + uint64_t *result = (uint64_t*)vresult; + + if (query->num_results) { + r600_context_flush(ctx); + } + r600_query_result(ctx, query); + *result = query->result; + query->result = 0; + return TRUE; +} + +void r600_context_queries_suspend(struct r600_context *ctx) +{ + struct r600_query *query; + + LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) { + if (query->state & R600_QUERY_STATE_STARTED) { + r600_query_end(ctx, query); + query->state |= R600_QUERY_STATE_SUSPENDED; + } + } +} + +void r600_context_queries_resume(struct r600_context *ctx) +{ + struct r600_query *query; + + LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) { + if (query->state & R600_QUERY_STATE_SUSPENDED) { + r600_query_begin(ctx, query); + query->state ^= R600_QUERY_STATE_SUSPENDED; + } + } +} diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h new file mode 100644 index 00000000000..e3868d3cb9a --- /dev/null +++ b/src/gallium/winsys/r600/drm/r600_priv.h @@ -0,0 +1,180 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef R600_PRIV_H +#define R600_PRIV_H + +#include <errno.h> +#include <stdint.h> +#include <stdlib.h> +#include <assert.h> +#include <pipebuffer/pb_bufmgr.h> +#include "util/u_double_list.h" +#include "r600.h" + +struct radeon { + int fd; + int refcount; + unsigned device; + unsigned family; + enum chip_class chip_class; + struct pb_manager *kman; /* kernel bo manager */ + struct pb_manager *cman; /* cached bo manager */ +}; + +struct radeon *r600_new(int fd, unsigned device); +void r600_delete(struct radeon *r600); + +struct r600_reg { + unsigned opcode; + unsigned offset_base; + unsigned offset; + unsigned need_bo; + unsigned flush_flags; + unsigned flush_mask; +}; + +struct radeon_bo { + struct pipe_reference reference; + unsigned handle; + unsigned size; + unsigned alignment; + unsigned map_count; + void *data; + struct list_head fencedlist; + unsigned fence; + struct r600_context *ctx; + boolean shared; + struct r600_reloc *reloc; + unsigned reloc_id; + unsigned last_flush; +}; + +struct r600_bo { + struct pipe_reference reference; + struct pb_buffer *pb; + unsigned size; +}; + + +/* radeon_pciid.c */ +unsigned radeon_family_from_device(unsigned device); + +/* r600_drm.c */ +struct radeon *radeon_decref(struct radeon *radeon); + +/* radeon_bo.c */ +struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, + unsigned size, unsigned alignment, void *ptr); +void radeon_bo_reference(struct radeon *radeon, struct radeon_bo **dst, + struct radeon_bo *src); +int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo); +int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain); +void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr); +int radeon_bo_fencelist(struct radeon *radeon, struct radeon_bo **bolist, uint32_t num_bo); + + +/* radeon_bo_pb.c */ +struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf); +struct pb_manager *radeon_bo_pbmgr_create(struct radeon *radeon); +struct pb_buffer *radeon_bo_pb_create_buffer_from_handle(struct pb_manager *_mgr, + uint32_t handle); + +/* r600_hw_context.c */ +int r600_context_init_fence(struct r600_context *ctx); +void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo); +void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags, + unsigned flush_mask, struct r600_bo *rbo); +struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset); +int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg); + +/* r600_bo.c */ +unsigned r600_bo_get_handle(struct r600_bo *bo); +unsigned r600_bo_get_size(struct r600_bo *bo); +static INLINE struct radeon_bo *r600_bo_get_bo(struct r600_bo *bo) +{ + return radeon_bo_pb_get_bo(bo->pb); +} + +#define CTX_RANGE_ID(ctx, offset) (((offset) >> (ctx)->hash_shift) & 255) +#define CTX_BLOCK_ID(ctx, offset) ((offset) & ((1 << (ctx)->hash_shift) - 1)) + +static void inline r600_context_reg(struct r600_context *ctx, + unsigned offset, unsigned value, + unsigned mask) +{ + struct r600_range *range; + struct r600_block *block; + unsigned id; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + id = (offset - block->start_offset) >> 2; + block->reg[id] &= ~mask; + block->reg[id] |= value; + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + ctx->pm4_dirty_cdwords += block->pm4_ndwords; + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +static inline void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block) +{ + int id; + + for (int j = 0; j < block->nreg; j++) { + if (block->pm4_bo_index[j]) { + /* find relocation */ + id = block->pm4_bo_index[j]; + r600_context_bo_reloc(ctx, + &block->pm4[block->reloc[id].bo_pm4_index], + block->reloc[id].bo); + r600_context_bo_flush(ctx, + block->reloc[id].flush_flags, + block->reloc[id].flush_mask, + block->reloc[id].bo); + } + } + memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, block->pm4_ndwords * 4); + ctx->pm4_cdwords += block->pm4_ndwords; + block->status ^= R600_BLOCK_STATUS_DIRTY; + LIST_DELINIT(&block->list); +} + +static inline int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo) +{ + bo->map_count++; + return 0; +} + +static inline void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo) +{ + bo->map_count--; + assert(bo->map_count >= 0); +} + +#endif diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h new file mode 100644 index 00000000000..d91f7737af3 --- /dev/null +++ b/src/gallium/winsys/r600/drm/r600d.h @@ -0,0 +1,2212 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef R600D_H +#define R600D_H + +/* evergreen values */ +#define EG_RESOURCE_OFFSET 0x00030000 +#define EG_RESOURCE_END 0x00034000 +#define EG_LOOP_CONST_OFFSET 0x0003A200 +#define EG_LOOP_CONST_END 0x0003A26C +#define EG_BOOL_CONST_OFFSET 0x0003A500 +#define EG_BOOL_CONST_END 0x0003A506 + + +#define R600_CONFIG_REG_OFFSET 0X00008000 +#define R600_CONFIG_REG_END 0X0000AC00 +#define R600_CONTEXT_REG_OFFSET 0X00028000 +#define R600_CONTEXT_REG_END 0X00029000 +#define R600_ALU_CONST_OFFSET 0X00030000 +#define R600_ALU_CONST_END 0X00032000 +#define R600_RESOURCE_OFFSET 0X00038000 +#define R600_RESOURCE_END 0X0003C000 +#define R600_SAMPLER_OFFSET 0X0003C000 +#define R600_SAMPLER_END 0X0003CFF0 +#define R600_CTL_CONST_OFFSET 0X0003CFF0 +#define R600_CTL_CONST_END 0X0003E200 +#define R600_LOOP_CONST_OFFSET 0X0003E200 +#define R600_LOOP_CONST_END 0X0003E380 +#define R600_BOOL_CONST_OFFSET 0X0003E380 +#define R600_BOOL_CONST_END 0X00040000 + +#define PKT3_NOP 0x10 +#define PKT3_INDIRECT_BUFFER_END 0x17 +#define PKT3_SET_PREDICATION 0x20 +#define PKT3_REG_RMW 0x21 +#define PKT3_COND_EXEC 0x22 +#define PKT3_PRED_EXEC 0x23 +#define PKT3_START_3D_CMDBUF 0x24 +#define PKT3_DRAW_INDEX_2 0x27 +#define PKT3_CONTEXT_CONTROL 0x28 +#define PKT3_DRAW_INDEX_IMMD_BE 0x29 +#define PKT3_INDEX_TYPE 0x2A +#define PKT3_DRAW_INDEX 0x2B +#define PKT3_DRAW_INDEX_AUTO 0x2D +#define PKT3_DRAW_INDEX_IMMD 0x2E +#define PKT3_NUM_INSTANCES 0x2F +#define PKT3_STRMOUT_BUFFER_UPDATE 0x34 +#define PKT3_INDIRECT_BUFFER_MP 0x38 +#define PKT3_MEM_SEMAPHORE 0x39 +#define PKT3_MPEG_INDEX 0x3A +#define PKT3_WAIT_REG_MEM 0x3C +#define PKT3_MEM_WRITE 0x3D +#define PKT3_INDIRECT_BUFFER 0x32 +#define PKT3_CP_INTERRUPT 0x40 +#define PKT3_SURFACE_SYNC 0x43 +#define PKT3_ME_INITIALIZE 0x44 +#define PKT3_COND_WRITE 0x45 +#define PKT3_EVENT_WRITE 0x46 +#define PKT3_EVENT_WRITE_EOP 0x47 +#define PKT3_ONE_REG_WRITE 0x57 +#define PKT3_SET_CONFIG_REG 0x68 +#define PKT3_SET_CONTEXT_REG 0x69 +#define PKT3_SET_ALU_CONST 0x6A +#define PKT3_SET_BOOL_CONST 0x6B +#define PKT3_SET_LOOP_CONST 0x6C +#define PKT3_SET_RESOURCE 0x6D +#define PKT3_SET_SAMPLER 0x6E +#define PKT3_SET_CTL_CONST 0x6F +#define PKT3_SURFACE_BASE_UPDATE 0x73 + +#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 +#define EVENT_TYPE_ZPASS_DONE 0x15 +#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 + +#define PKT_TYPE_S(x) (((x) & 0x3) << 30) +#define PKT_TYPE_G(x) (((x) >> 30) & 0x3) +#define PKT_TYPE_C 0x3FFFFFFF +#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) +#define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) +#define PKT_COUNT_C 0xC000FFFF +#define PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0) +#define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) +#define PKT0_BASE_INDEX_C 0xFFFF0000 +#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) +#define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF) +#define PKT3_IT_OPCODE_C 0xFFFF00FF +#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count)) +#define PKT3(op, count) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count)) + +/* Registers */ +#define R_0280A0_CB_COLOR0_INFO 0x0280A0 +#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) +#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) +#define C_0280A0_ENDIAN 0xFFFFFFFC +#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) +#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) +#define C_0280A0_FORMAT 0xFFFFFF03 +#define V_0280A0_COLOR_INVALID 0x00000000 +#define V_0280A0_COLOR_8 0x00000001 +#define V_0280A0_COLOR_4_4 0x00000002 +#define V_0280A0_COLOR_3_3_2 0x00000003 +#define V_0280A0_COLOR_16 0x00000005 +#define V_0280A0_COLOR_16_FLOAT 0x00000006 +#define V_0280A0_COLOR_8_8 0x00000007 +#define V_0280A0_COLOR_5_6_5 0x00000008 +#define V_0280A0_COLOR_6_5_5 0x00000009 +#define V_0280A0_COLOR_1_5_5_5 0x0000000A +#define V_0280A0_COLOR_4_4_4_4 0x0000000B +#define V_0280A0_COLOR_5_5_5_1 0x0000000C +#define V_0280A0_COLOR_32 0x0000000D +#define V_0280A0_COLOR_32_FLOAT 0x0000000E +#define V_0280A0_COLOR_16_16 0x0000000F +#define V_0280A0_COLOR_16_16_FLOAT 0x00000010 +#define V_0280A0_COLOR_8_24 0x00000011 +#define V_0280A0_COLOR_8_24_FLOAT 0x00000012 +#define V_0280A0_COLOR_24_8 0x00000013 +#define V_0280A0_COLOR_24_8_FLOAT 0x00000014 +#define V_0280A0_COLOR_10_11_11 0x00000015 +#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 +#define V_0280A0_COLOR_11_11_10 0x00000017 +#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 +#define V_0280A0_COLOR_2_10_10_10 0x00000019 +#define V_0280A0_COLOR_8_8_8_8 0x0000001A +#define V_0280A0_COLOR_10_10_10_2 0x0000001B +#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C +#define V_0280A0_COLOR_32_32 0x0000001D +#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E +#define V_0280A0_COLOR_16_16_16_16 0x0000001F +#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 +#define V_0280A0_COLOR_32_32_32_32 0x00000022 +#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 +#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) +#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) +#define C_0280A0_ARRAY_MODE 0xFFFFF0FF +#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 +#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 +#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 +#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 +#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) +#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) +#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF +#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) +#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) +#define C_0280A0_READ_SIZE 0xFFFF7FFF +#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) +#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) +#define C_0280A0_COMP_SWAP 0xFFFCFFFF +#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) +#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) +#define C_0280A0_TILE_MODE 0xFFF3FFFF +#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) +#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) +#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF +#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) +#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) +#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF +#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) +#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) +#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF +#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) +#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) +#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF +#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) +#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) +#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF +#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) +#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) +#define C_0280A0_ROUND_MODE 0xFDFFFFFF +#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) +#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) +#define C_0280A0_TILE_COMPACT 0xFBFFFFFF +#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) +#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) +#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF +#define R_028060_CB_COLOR0_SIZE 0x028060 +#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028060_PITCH_TILE_MAX 0xFFFFFC00 +#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) +#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) +#define C_028060_SLICE_TILE_MAX 0xC00003FF +#define R_028800_DB_DEPTH_CONTROL 0x028800 +#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) +#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028800_STENCIL_ENABLE 0xFFFFFFFE +#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) +#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028800_Z_ENABLE 0xFFFFFFFD +#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) +#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) +#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB +#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) +#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) +#define C_028800_ZFUNC 0xFFFFFF8F +#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) +#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) +#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F +#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) +#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) +#define C_028800_STENCILFUNC 0xFFFFF8FF +#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) +#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) +#define C_028800_STENCILFAIL 0xFFFFC7FF +#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) +#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) +#define C_028800_STENCILZPASS 0xFFFE3FFF +#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) +#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) +#define C_028800_STENCILZFAIL 0xFFF1FFFF +#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) +#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) +#define C_028800_STENCILFUNC_BF 0xFF8FFFFF +#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) +#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) +#define C_028800_STENCILFAIL_BF 0xFC7FFFFF +#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) +#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) +#define C_028800_STENCILZPASS_BF 0xE3FFFFFF +#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) +#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) +#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF +#define R_028010_DB_DEPTH_INFO 0x028010 +#define S_028010_FORMAT(x) (((x) & 0x7) << 0) +#define G_028010_FORMAT(x) (((x) >> 0) & 0x7) +#define C_028010_FORMAT 0xFFFFFFF8 +#define V_028010_DEPTH_INVALID 0x00000000 +#define V_028010_DEPTH_16 0x00000001 +#define V_028010_DEPTH_X8_24 0x00000002 +#define V_028010_DEPTH_8_24 0x00000003 +#define V_028010_DEPTH_X8_24_FLOAT 0x00000004 +#define V_028010_DEPTH_8_24_FLOAT 0x00000005 +#define V_028010_DEPTH_32_FLOAT 0x00000006 +#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 +#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) +#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) +#define C_028010_READ_SIZE 0xFFFFFFF7 +#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) +#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) +#define C_028010_ARRAY_MODE 0xFFF87FFF +#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) +#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) +#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF +#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) +#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) +#define C_028010_TILE_COMPACT 0xFBFFFFFF +#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) +#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) +#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF +#define R_028000_DB_DEPTH_SIZE 0x028000 +#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028000_PITCH_TILE_MAX 0xFFFFFC00 +#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) +#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) +#define C_028000_SLICE_TILE_MAX 0xC00003FF +#define R_028004_DB_DEPTH_VIEW 0x028004 +#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) +#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) +#define C_028004_SLICE_START 0xFFFFF800 +#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) +#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) +#define C_028004_SLICE_MAX 0xFF001FFF +#define R_028D24_DB_HTILE_SURFACE 0x028D24 +#define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) +#define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) +#define C_028D24_HTILE_WIDTH 0xFFFFFFFE +#define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) +#define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) +#define C_028D24_HTILE_HEIGHT 0xFFFFFFFD +#define S_028D24_LINEAR(x) (((x) & 0x1) << 2) +#define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) +#define C_028D24_LINEAR 0xFFFFFFFB +#define S_028D24_FULL_CACHE(x) (((x) & 0x1) << 3) +#define G_028D24_FULL_CACHE(x) (((x) >> 3) & 0x1) +#define C_028D24_FULL_CACHE 0xFFFFFFF7 +#define S_028D24_HTILE_USES_PRELOAD_WIN(x) (((x) & 0x1) << 4) +#define G_028D24_HTILE_USES_PRELOAD_WIN(x) (((x) >> 4) & 0x1) +#define C_028D24_HTILE_USES_PRELOAD_WIN 0xFFFFFFEF +#define S_028D24_PRELOAD(x) (((x) & 0x1) << 5) +#define G_028D24_PRELOAD(x) (((x) >> 5) & 0x1) +#define C_028D24_PRELOAD 0xFFFFFFDF +#define S_028D24_PREFETCH_WIDTH(x) (((x) & 0x3F) << 6) +#define G_028D24_PREFETCH_WIDTH(x) (((x) >> 6) & 0x3F) +#define C_028D24_PREFETCH_WIDTH 0xFFFFF03F +#define S_028D24_PREFETCH_HEIGHT(x) (((x) & 0x3F) << 12) +#define G_028D24_PREFETCH_HEIGHT(x) (((x) >> 12) & 0x3F) +#define C_028D24_PREFETCH_HEIGHT 0xFFFC0FFF +#define R_028D34_DB_PREFETCH_LIMIT 0x028D34 +#define S_028D34_DEPTH_HEIGHT_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028D34_DEPTH_HEIGHT_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028D34_DEPTH_HEIGHT_TILE_MAX 0xFFFFFC00 +#define R_028D10_DB_RENDER_OVERRIDE 0x028D10 +#define S_028D10_FORCE_HIZ_ENABLE(x) (((x) & 0x3) << 0) +#define G_028D10_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x3) +#define C_028D10_FORCE_HIZ_ENABLE 0xFFFFFFFC +#define S_028D10_FORCE_HIS_ENABLE0(x) (((x) & 0x3) << 2) +#define G_028D10_FORCE_HIS_ENABLE0(x) (((x) >> 2) & 0x3) +#define C_028D10_FORCE_HIS_ENABLE0 0xFFFFFFF3 +#define S_028D10_FORCE_HIS_ENABLE1(x) (((x) & 0x3) << 4) +#define G_028D10_FORCE_HIS_ENABLE1(x) (((x) >> 4) & 0x3) +#define C_028D10_FORCE_HIS_ENABLE1 0xFFFFFFCF +#define S_028D10_FORCE_SHADER_Z_ORDER(x) (((x) & 0x1) << 6) +#define G_028D10_FORCE_SHADER_Z_ORDER(x) (((x) >> 6) & 0x1) +#define C_028D10_FORCE_SHADER_Z_ORDER 0xFFFFFFBF +#define S_028D10_FAST_Z_DISABLE(x) (((x) & 0x1) << 7) +#define G_028D10_FAST_Z_DISABLE(x) (((x) >> 7) & 0x1) +#define C_028D10_FAST_Z_DISABLE 0xFFFFFF7F +#define S_028D10_FAST_STENCIL_DISABLE(x) (((x) & 0x1) << 8) +#define G_028D10_FAST_STENCIL_DISABLE(x) (((x) >> 8) & 0x1) +#define C_028D10_FAST_STENCIL_DISABLE 0xFFFFFEFF +#define S_028D10_NOOP_CULL_DISABLE(x) (((x) & 0x1) << 9) +#define G_028D10_NOOP_CULL_DISABLE(x) (((x) >> 9) & 0x1) +#define C_028D10_NOOP_CULL_DISABLE 0xFFFFFDFF +#define S_028D10_FORCE_COLOR_KILL(x) (((x) & 0x1) << 10) +#define G_028D10_FORCE_COLOR_KILL(x) (((x) >> 10) & 0x1) +#define C_028D10_FORCE_COLOR_KILL 0xFFFFFBFF +#define S_028D10_FORCE_Z_READ(x) (((x) & 0x1) << 11) +#define G_028D10_FORCE_Z_READ(x) (((x) >> 11) & 0x1) +#define C_028D10_FORCE_Z_READ 0xFFFFF7FF +#define S_028D10_FORCE_STENCIL_READ(x) (((x) & 0x1) << 12) +#define G_028D10_FORCE_STENCIL_READ(x) (((x) >> 12) & 0x1) +#define C_028D10_FORCE_STENCIL_READ 0xFFFFEFFF +#define S_028D10_FORCE_FULL_Z_RANGE(x) (((x) & 0x3) << 13) +#define G_028D10_FORCE_FULL_Z_RANGE(x) (((x) >> 13) & 0x3) +#define C_028D10_FORCE_FULL_Z_RANGE 0xFFFF9FFF +#define S_028D10_FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x1) << 15) +#define G_028D10_FORCE_QC_SMASK_CONFLICT(x) (((x) >> 15) & 0x1) +#define C_028D10_FORCE_QC_SMASK_CONFLICT 0xFFFF7FFF +#define S_028D10_DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x1) << 16) +#define G_028D10_DISABLE_VIEWPORT_CLAMP(x) (((x) >> 16) & 0x1) +#define C_028D10_DISABLE_VIEWPORT_CLAMP 0xFFFEFFFF +#define S_028D10_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17) +#define G_028D10_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1) +#define C_028D10_IGNORE_SC_ZRANGE 0xFFFDFFFF +#define R_028A40_VGT_GS_MODE 0x028A40 +#define S_028A40_MODE(x) (((x) & 0x3) << 0) +#define G_028A40_MODE(x) (((x) >> 0) & 0x3) +#define C_028A40_MODE 0xFFFFFFFC +#define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 2) +#define G_028A40_ES_PASSTHRU(x) (((x) >> 2) & 0x1) +#define C_028A40_ES_PASSTHRU 0xFFFFFFFB +#define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3) +#define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3) +#define C_028A40_CUT_MODE 0xFFFFFFE7 +#define R_008DFC_SQ_CF_WORD0 0x008DFC +#define S_008DFC_ADDR(x) (((x) & 0xFFFFFFFF) << 0) +#define G_008DFC_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_008DFC_ADDR 0x00000000 +#define R_008DFC_SQ_CF_WORD1 0x008DFC +#define S_008DFC_POP_COUNT(x) (((x) & 0x7) << 0) +#define G_008DFC_POP_COUNT(x) (((x) >> 0) & 0x7) +#define C_008DFC_POP_COUNT 0xFFFFFFF8 +#define S_008DFC_CF_CONST(x) (((x) & 0x1F) << 3) +#define G_008DFC_CF_CONST(x) (((x) >> 3) & 0x1F) +#define C_008DFC_CF_CONST 0xFFFFFF07 +#define S_008DFC_COND(x) (((x) & 0x3) << 8) +#define G_008DFC_COND(x) (((x) >> 8) & 0x3) +#define C_008DFC_COND 0xFFFFFCFF +#define S_008DFC_COUNT(x) (((x) & 0x7) << 10) +#define G_008DFC_COUNT(x) (((x) >> 10) & 0x7) +#define C_008DFC_COUNT 0xFFFFE3FF +#define S_008DFC_CALL_COUNT(x) (((x) & 0x3F) << 13) +#define G_008DFC_CALL_COUNT(x) (((x) >> 13) & 0x3F) +#define C_008DFC_CALL_COUNT 0xFFF81FFF +#define S_008DFC_END_OF_PROGRAM(x) (((x) & 0x1) << 21) +#define G_008DFC_END_OF_PROGRAM(x) (((x) >> 21) & 0x1) +#define C_008DFC_END_OF_PROGRAM 0xFFDFFFFF +#define S_008DFC_VALID_PIXEL_MODE(x) (((x) & 0x1) << 22) +#define G_008DFC_VALID_PIXEL_MODE(x) (((x) >> 22) & 0x1) +#define C_008DFC_VALID_PIXEL_MODE 0xFFBFFFFF +#define S_008DFC_CF_INST(x) (((x) & 0x7F) << 23) +#define G_008DFC_CF_INST(x) (((x) >> 23) & 0x7F) +#define C_008DFC_CF_INST 0xC07FFFFF +#define V_008DFC_SQ_CF_INST_NOP 0x00000000 +#define V_008DFC_SQ_CF_INST_TEX 0x00000001 +#define V_008DFC_SQ_CF_INST_VTX 0x00000002 +#define V_008DFC_SQ_CF_INST_VTX_TC 0x00000003 +#define V_008DFC_SQ_CF_INST_LOOP_START 0x00000004 +#define V_008DFC_SQ_CF_INST_LOOP_END 0x00000005 +#define V_008DFC_SQ_CF_INST_LOOP_START_DX10 0x00000006 +#define V_008DFC_SQ_CF_INST_LOOP_START_NO_AL 0x00000007 +#define V_008DFC_SQ_CF_INST_LOOP_CONTINUE 0x00000008 +#define V_008DFC_SQ_CF_INST_LOOP_BREAK 0x00000009 +#define V_008DFC_SQ_CF_INST_JUMP 0x0000000A +#define V_008DFC_SQ_CF_INST_PUSH 0x0000000B +#define V_008DFC_SQ_CF_INST_PUSH_ELSE 0x0000000C +#define V_008DFC_SQ_CF_INST_ELSE 0x0000000D +#define V_008DFC_SQ_CF_INST_POP 0x0000000E +#define V_008DFC_SQ_CF_INST_POP_JUMP 0x0000000F +#define V_008DFC_SQ_CF_INST_POP_PUSH 0x00000010 +#define V_008DFC_SQ_CF_INST_POP_PUSH_ELSE 0x00000011 +#define V_008DFC_SQ_CF_INST_CALL 0x00000012 +#define V_008DFC_SQ_CF_INST_CALL_FS 0x00000013 +#define V_008DFC_SQ_CF_INST_RETURN 0x00000014 +#define V_008DFC_SQ_CF_INST_EMIT_VERTEX 0x00000015 +#define V_008DFC_SQ_CF_INST_EMIT_CUT_VERTEX 0x00000016 +#define V_008DFC_SQ_CF_INST_CUT_VERTEX 0x00000017 +#define V_008DFC_SQ_CF_INST_KILL 0x00000018 +#define S_008DFC_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_008DFC_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_008DFC_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_008DFC_BARRIER(x) (((x) & 0x1) << 31) +#define G_008DFC_BARRIER(x) (((x) >> 31) & 0x1) +#define C_008DFC_BARRIER 0x7FFFFFFF +#define R_008DFC_SQ_CF_ALU_WORD0 0x008DFC +#define S_008DFC_ALU_ADDR(x) (((x) & 0x3FFFFF) << 0) +#define G_008DFC_ALU_ADDR(x) (((x) >> 0) & 0x3FFFFF) +#define C_008DFC_ALU_ADDR 0xFFC00000 +#define S_008DFC_KCACHE_BANK0(x) (((x) & 0xF) << 22) +#define G_008DFC_KCACHE_BANK0(x) (((x) >> 22) & 0xF) +#define C_008DFC_KCACHE_BANK0 0xFC3FFFFF +#define S_008DFC_KCACHE_BANK1(x) (((x) & 0xF) << 26) +#define G_008DFC_KCACHE_BANK1(x) (((x) >> 26) & 0xF) +#define C_008DFC_KCACHE_BANK1 0xC3FFFFFF +#define S_008DFC_KCACHE_MODE0(x) (((x) & 0x3) << 30) +#define G_008DFC_KCACHE_MODE0(x) (((x) >> 30) & 0x3) +#define C_008DFC_KCACHE_MODE0 0x3FFFFFFF +#define R_008DFC_SQ_CF_ALU_WORD1 0x008DFC +#define S_008DFC_KCACHE_MODE1(x) (((x) & 0x3) << 0) +#define G_008DFC_KCACHE_MODE1(x) (((x) >> 0) & 0x3) +#define C_008DFC_KCACHE_MODE1 0xFFFFFFFC +#define S_008DFC_KCACHE_ADDR0(x) (((x) & 0xFF) << 2) +#define G_008DFC_KCACHE_ADDR0(x) (((x) >> 2) & 0xFF) +#define C_008DFC_KCACHE_ADDR0 0xFFFFFC03 +#define S_008DFC_KCACHE_ADDR1(x) (((x) & 0xFF) << 10) +#define G_008DFC_KCACHE_ADDR1(x) (((x) >> 10) & 0xFF) +#define C_008DFC_KCACHE_ADDR1 0xFFFC03FF +#define S_008DFC_ALU_COUNT(x) (((x) & 0x7F) << 18) +#define G_008DFC_ALU_COUNT(x) (((x) >> 18) & 0x7F) +#define C_008DFC_ALU_COUNT 0xFE03FFFF +#define S_008DFC_USES_WATERFALL(x) (((x) & 0x1) << 25) +#define G_008DFC_USES_WATERFALL(x) (((x) >> 25) & 0x1) +#define C_008DFC_USES_WATERFALL 0xFDFFFFFF +#define S_008DFC_CF_ALU_INST(x) (((x) & 0xF) << 26) +#define G_008DFC_CF_ALU_INST(x) (((x) >> 26) & 0xF) +#define C_008DFC_CF_ALU_INST 0xC3FFFFFF +#define V_008DFC_SQ_CF_INST_ALU 0x00000008 +#define V_008DFC_SQ_CF_INST_ALU_PUSH_BEFORE 0x00000009 +#define V_008DFC_SQ_CF_INST_ALU_POP_AFTER 0x0000000A +#define V_008DFC_SQ_CF_INST_ALU_POP2_AFTER 0x0000000B +#define V_008DFC_SQ_CF_INST_ALU_CONTINUE 0x0000000D +#define V_008DFC_SQ_CF_INST_ALU_BREAK 0x0000000E +#define V_008DFC_SQ_CF_INST_ALU_ELSE_AFTER 0x0000000F +#define S_008DFC_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_008DFC_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_008DFC_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_008DFC_BARRIER(x) (((x) & 0x1) << 31) +#define G_008DFC_BARRIER(x) (((x) >> 31) & 0x1) +#define C_008DFC_BARRIER 0x7FFFFFFF +#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD0 0x008DFC +#define S_008DFC_ARRAY_BASE(x) (((x) & 0x1FFF) << 0) +#define G_008DFC_ARRAY_BASE(x) (((x) >> 0) & 0x1FFF) +#define C_008DFC_ARRAY_BASE 0xFFFFE000 +#define S_008DFC_TYPE(x) (((x) & 0x3) << 13) +#define G_008DFC_TYPE(x) (((x) >> 13) & 0x3) +#define C_008DFC_TYPE 0xFFFF9FFF +#define S_008DFC_RW_GPR(x) (((x) & 0x7F) << 15) +#define G_008DFC_RW_GPR(x) (((x) >> 15) & 0x7F) +#define C_008DFC_RW_GPR 0xFFC07FFF +#define S_008DFC_RW_REL(x) (((x) & 0x1) << 22) +#define G_008DFC_RW_REL(x) (((x) >> 22) & 0x1) +#define C_008DFC_RW_REL 0xFFBFFFFF +#define S_008DFC_INDEX_GPR(x) (((x) & 0x7F) << 23) +#define G_008DFC_INDEX_GPR(x) (((x) >> 23) & 0x7F) +#define C_008DFC_INDEX_GPR 0xC07FFFFF +#define S_008DFC_ELEM_SIZE(x) (((x) & 0x3) << 30) +#define G_008DFC_ELEM_SIZE(x) (((x) >> 30) & 0x3) +#define C_008DFC_ELEM_SIZE 0x3FFFFFFF +#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1 0x008DFC +#define S_008DFC_BURST_COUNT(x) (((x) & 0xF) << 17) +#define G_008DFC_BURST_COUNT(x) (((x) >> 17) & 0xF) +#define C_008DFC_BURST_COUNT 0xFFE1FFFF +#define S_008DFC_END_OF_PROGRAM(x) (((x) & 0x1) << 21) +#define G_008DFC_END_OF_PROGRAM(x) (((x) >> 21) & 0x1) +#define C_008DFC_END_OF_PROGRAM 0xFFDFFFFF +#define S_008DFC_VALID_PIXEL_MODE(x) (((x) & 0x1) << 22) +#define G_008DFC_VALID_PIXEL_MODE(x) (((x) >> 22) & 0x1) +#define C_008DFC_VALID_PIXEL_MODE 0xFFBFFFFF +#define S_008DFC_CF_INST(x) (((x) & 0x7F) << 23) +#define G_008DFC_CF_INST(x) (((x) >> 23) & 0x7F) +#define C_008DFC_CF_INST 0xC07FFFFF +#define V_008DFC_SQ_CF_INST_MEM_STREAM0 0x00000020 +#define V_008DFC_SQ_CF_INST_MEM_STREAM1 0x00000021 +#define V_008DFC_SQ_CF_INST_MEM_STREAM2 0x00000022 +#define V_008DFC_SQ_CF_INST_MEM_STREAM3 0x00000023 +#define V_008DFC_SQ_CF_INST_MEM_SCRATCH 0x00000024 +#define V_008DFC_SQ_CF_INST_MEM_REDUCTION 0x00000025 +#define V_008DFC_SQ_CF_INST_MEM_RING 0x00000026 +#define V_008DFC_SQ_CF_INST_EXPORT 0x00000027 +#define V_008DFC_SQ_CF_INST_EXPORT_DONE 0x00000028 +#define S_008DFC_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30) +#define G_008DFC_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1) +#define C_008DFC_WHOLE_QUAD_MODE 0xBFFFFFFF +#define S_008DFC_BARRIER(x) (((x) & 0x1) << 31) +#define G_008DFC_BARRIER(x) (((x) >> 31) & 0x1) +#define C_008DFC_BARRIER 0x7FFFFFFF +#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_BUF 0x008DFC +#define S_008DFC_ARRAY_SIZE(x) (((x) & 0xFFF) << 0) +#define G_008DFC_ARRAY_SIZE(x) (((x) >> 0) & 0xFFF) +#define C_008DFC_ARRAY_SIZE 0xFFFFF000 +#define S_008DFC_COMP_MASK(x) (((x) & 0xF) << 12) +#define G_008DFC_COMP_MASK(x) (((x) >> 12) & 0xF) +#define C_008DFC_COMP_MASK 0xFFFF0FFF +#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ 0x008DFC +#define S_008DFC_SEL_X(x) (((x) & 0x7) << 0) +#define G_008DFC_SEL_X(x) (((x) >> 0) & 0x7) +#define C_008DFC_SEL_X 0xFFFFFFF8 +#define S_008DFC_SEL_Y(x) (((x) & 0x7) << 3) +#define G_008DFC_SEL_Y(x) (((x) >> 3) & 0x7) +#define C_008DFC_SEL_Y 0xFFFFFFC7 +#define S_008DFC_SEL_Z(x) (((x) & 0x7) << 6) +#define G_008DFC_SEL_Z(x) (((x) >> 6) & 0x7) +#define C_008DFC_SEL_Z 0xFFFFFE3F +#define S_008DFC_SEL_W(x) (((x) & 0x7) << 9) +#define G_008DFC_SEL_W(x) (((x) >> 9) & 0x7) +#define C_008DFC_SEL_W 0xFFFFF1FF +#define R_008DFC_SQ_VTX_WORD0 0x008DFC +#define S_008DFC_VTX_INST(x) (((x) & 0x1F) << 0) +#define G_008DFC_VTX_INST(x) (((x) >> 0) & 0x1F) +#define C_008DFC_VTX_INST 0xFFFFFFE0 +#define S_008DFC_FETCH_TYPE(x) (((x) & 0x3) << 5) +#define G_008DFC_FETCH_TYPE(x) (((x) >> 5) & 0x3) +#define C_008DFC_FETCH_TYPE 0xFFFFFF9F +#define S_008DFC_FETCH_WHOLE_QUAD(x) (((x) & 0x1) << 7) +#define G_008DFC_FETCH_WHOLE_QUAD(x) (((x) >> 7) & 0x1) +#define C_008DFC_FETCH_WHOLE_QUAD 0xFFFFFF7F +#define S_008DFC_BUFFER_ID(x) (((x) & 0xFF) << 8) +#define G_008DFC_BUFFER_ID(x) (((x) >> 8) & 0xFF) +#define C_008DFC_BUFFER_ID 0xFFFF00FF +#define S_008DFC_SRC_GPR(x) (((x) & 0x7F) << 16) +#define G_008DFC_SRC_GPR(x) (((x) >> 16) & 0x7F) +#define C_008DFC_SRC_GPR 0xFF80FFFF +#define S_008DFC_SRC_REL(x) (((x) & 0x1) << 23) +#define G_008DFC_SRC_REL(x) (((x) >> 23) & 0x1) +#define C_008DFC_SRC_REL 0xFF7FFFFF +#define S_008DFC_SRC_SEL_X(x) (((x) & 0x3) << 24) +#define G_008DFC_SRC_SEL_X(x) (((x) >> 24) & 0x3) +#define C_008DFC_SRC_SEL_X 0xFCFFFFFF +#define S_008DFC_MEGA_FETCH_COUNT(x) (((x) & 0x3F) << 26) +#define G_008DFC_MEGA_FETCH_COUNT(x) (((x) >> 26) & 0x3F) +#define C_008DFC_MEGA_FETCH_COUNT 0x03FFFFFF +#define R_008DFC_SQ_VTX_WORD1 0x008DFC +#define S_008DFC_DST_SEL_X(x) (((x) & 0x7) << 9) +#define G_008DFC_DST_SEL_X(x) (((x) >> 9) & 0x7) +#define C_008DFC_DST_SEL_X 0xFFFFF1FF +#define S_008DFC_DST_SEL_Y(x) (((x) & 0x7) << 12) +#define G_008DFC_DST_SEL_Y(x) (((x) >> 12) & 0x7) +#define C_008DFC_DST_SEL_Y 0xFFFF8FFF +#define S_008DFC_DST_SEL_Z(x) (((x) & 0x7) << 15) +#define G_008DFC_DST_SEL_Z(x) (((x) >> 15) & 0x7) +#define C_008DFC_DST_SEL_Z 0xFFFC7FFF +#define S_008DFC_DST_SEL_W(x) (((x) & 0x7) << 18) +#define G_008DFC_DST_SEL_W(x) (((x) >> 18) & 0x7) +#define C_008DFC_DST_SEL_W 0xFFE3FFFF +#define S_008DFC_USE_CONST_FIELDS(x) (((x) & 0x1) << 21) +#define G_008DFC_USE_CONST_FIELDS(x) (((x) >> 21) & 0x1) +#define C_008DFC_USE_CONST_FIELDS 0xFFDFFFFF +#define S_008DFC_DATA_FORMAT(x) (((x) & 0x3F) << 22) +#define G_008DFC_DATA_FORMAT(x) (((x) >> 22) & 0x3F) +#define C_008DFC_DATA_FORMAT 0xF03FFFFF +#define S_008DFC_NUM_FORMAT_ALL(x) (((x) & 0x3) << 28) +#define G_008DFC_NUM_FORMAT_ALL(x) (((x) >> 28) & 0x3) +#define C_008DFC_NUM_FORMAT_ALL 0xCFFFFFFF +#define S_008DFC_FORMAT_COMP_ALL(x) (((x) & 0x1) << 30) +#define G_008DFC_FORMAT_COMP_ALL(x) (((x) >> 30) & 0x1) +#define C_008DFC_FORMAT_COMP_ALL 0xBFFFFFFF +#define S_008DFC_SRF_MODE_ALL(x) (((x) & 0x1) << 31) +#define G_008DFC_SRF_MODE_ALL(x) (((x) >> 31) & 0x1) +#define C_008DFC_SRF_MODE_ALL 0x7FFFFFFF +#define R_008DFC_SQ_VTX_WORD1_GPR 0x008DFC +#define S_008DFC_DST_GPR(x) (((x) & 0x7F) << 0) +#define G_008DFC_DST_GPR(x) (((x) >> 0) & 0x7F) +#define C_008DFC_DST_GPR 0xFFFFFF80 +#define S_008DFC_DST_REL(x) (((x) & 0x1) << 7) +#define G_008DFC_DST_REL(x) (((x) >> 7) & 0x1) +#define C_008DFC_DST_REL 0xFFFFFF7F +#define R_008DFC_SQ_VTX_WORD2 0x008DFC +#define S_008DFC_OFFSET(x) (((x) & 0xFFFF) << 0) +#define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFFF) +#define C_008DFC_OFFSET 0xFFFF0000 +#define S_008DFC_ENDIAN_SWAP(x) (((x) & 0x3) << 16) +#define G_008DFC_ENDIAN_SWAP(x) (((x) >> 16) & 0x3) +#define C_008DFC_ENDIAN_SWAP 0xFFFCFFFF +#define S_008DFC_CONST_BUF_NO_STRIDE(x) (((x) & 0x1) << 18) +#define G_008DFC_CONST_BUF_NO_STRIDE(x) (((x) >> 18) & 0x1) +#define C_008DFC_CONST_BUF_NO_STRIDE 0xFFFBFFFF +#define S_008DFC_MEGA_FETCH(x) (((x) & 0x1) << 19) +#define G_008DFC_MEGA_FETCH(x) (((x) >> 19) & 0x1) +#define C_008DFC_MEGA_FETCH 0xFFF7FFFF +#define S_008DFC_ALT_CONST(x) (((x) & 0x1) << 20) +#define G_008DFC_ALT_CONST(x) (((x) >> 20) & 0x1) +#define C_008DFC_ALT_CONST 0xFFEFFFFF +#define R_008040_WAIT_UNTIL 0x008040 +#define S_008040_WAIT_CP_DMA_IDLE(x) (((x) & 0x1) << 8) +#define G_008040_WAIT_CP_DMA_IDLE(x) (((x) >> 8) & 0x1) +#define C_008040_WAIT_CP_DMA_IDLE 0xFFFFFEFF +#define S_008040_WAIT_CMDFIFO(x) (((x) & 0x1) << 10) +#define G_008040_WAIT_CMDFIFO(x) (((x) >> 10) & 0x1) +#define C_008040_WAIT_CMDFIFO 0xFFFFFBFF +#define S_008040_WAIT_2D_IDLE(x) (((x) & 0x1) << 14) +#define G_008040_WAIT_2D_IDLE(x) (((x) >> 14) & 0x1) +#define C_008040_WAIT_2D_IDLE 0xFFFFBFFF +#define S_008040_WAIT_3D_IDLE(x) (((x) & 0x1) << 15) +#define G_008040_WAIT_3D_IDLE(x) (((x) >> 15) & 0x1) +#define C_008040_WAIT_3D_IDLE 0xFFFF7FFF +#define S_008040_WAIT_2D_IDLECLEAN(x) (((x) & 0x1) << 16) +#define G_008040_WAIT_2D_IDLECLEAN(x) (((x) >> 16) & 0x1) +#define C_008040_WAIT_2D_IDLECLEAN 0xFFFEFFFF +#define S_008040_WAIT_3D_IDLECLEAN(x) (((x) & 0x1) << 17) +#define G_008040_WAIT_3D_IDLECLEAN(x) (((x) >> 17) & 0x1) +#define C_008040_WAIT_3D_IDLECLEAN 0xFFFDFFFF +#define S_008040_WAIT_EXTERN_SIG(x) (((x) & 0x1) << 19) +#define G_008040_WAIT_EXTERN_SIG(x) (((x) >> 19) & 0x1) +#define C_008040_WAIT_EXTERN_SIG 0xFFF7FFFF +#define S_008040_CMDFIFO_ENTRIES(x) (((x) & 0x1F) << 20) +#define G_008040_CMDFIFO_ENTRIES(x) (((x) >> 20) & 0x1F) +#define C_008040_CMDFIFO_ENTRIES 0xFE0FFFFF +#define R_0286CC_SPI_PS_IN_CONTROL_0 0x0286CC +#define S_0286CC_NUM_INTERP(x) (((x) & 0x3F) << 0) +#define G_0286CC_NUM_INTERP(x) (((x) >> 0) & 0x3F) +#define C_0286CC_NUM_INTERP 0xFFFFFFC0 +#define S_0286CC_POSITION_ENA(x) (((x) & 0x1) << 8) +#define G_0286CC_POSITION_ENA(x) (((x) >> 8) & 0x1) +#define C_0286CC_POSITION_ENA 0xFFFFFEFF +#define S_0286CC_POSITION_CENTROID(x) (((x) & 0x1) << 9) +#define G_0286CC_POSITION_CENTROID(x) (((x) >> 9) & 0x1) +#define C_0286CC_POSITION_CENTROID 0xFFFFFDFF +#define S_0286CC_POSITION_ADDR(x) (((x) & 0x1F) << 10) +#define G_0286CC_POSITION_ADDR(x) (((x) >> 10) & 0x1F) +#define C_0286CC_POSITION_ADDR 0xFFFF83FF +#define S_0286CC_PARAM_GEN(x) (((x) & 0xF) << 15) +#define G_0286CC_PARAM_GEN(x) (((x) >> 15) & 0xF) +#define C_0286CC_PARAM_GEN 0xFFF87FFF +#define S_0286CC_PARAM_GEN_ADDR(x) (((x) & 0x7F) << 19) +#define G_0286CC_PARAM_GEN_ADDR(x) (((x) >> 19) & 0x7F) +#define C_0286CC_PARAM_GEN_ADDR 0xFC07FFFF +#define S_0286CC_BARYC_SAMPLE_CNTL(x) (((x) & 0x3) << 26) +#define G_0286CC_BARYC_SAMPLE_CNTL(x) (((x) >> 26) & 0x3) +#define C_0286CC_BARYC_SAMPLE_CNTL 0xF3FFFFFF +#define S_0286CC_PERSP_GRADIENT_ENA(x) (((x) & 0x1) << 28) +#define G_0286CC_PERSP_GRADIENT_ENA(x) (((x) >> 28) & 0x1) +#define C_0286CC_PERSP_GRADIENT_ENA 0xEFFFFFFF +#define S_0286CC_LINEAR_GRADIENT_ENA(x) (((x) & 0x1) << 29) +#define G_0286CC_LINEAR_GRADIENT_ENA(x) (((x) >> 29) & 0x1) +#define C_0286CC_LINEAR_GRADIENT_ENA 0xDFFFFFFF +#define S_0286CC_POSITION_SAMPLE(x) (((x) & 0x1) << 30) +#define G_0286CC_POSITION_SAMPLE(x) (((x) >> 30) & 0x1) +#define C_0286CC_POSITION_SAMPLE 0xBFFFFFFF +#define S_0286CC_BARYC_AT_SAMPLE_ENA(x) (((x) & 0x1) << 31) +#define G_0286CC_BARYC_AT_SAMPLE_ENA(x) (((x) >> 31) & 0x1) +#define C_0286CC_BARYC_AT_SAMPLE_ENA 0x7FFFFFFF +#define R_0286D0_SPI_PS_IN_CONTROL_1 0x0286D0 +#define S_0286D0_GEN_INDEX_PIX(x) (((x) & 0x1) << 0) +#define G_0286D0_GEN_INDEX_PIX(x) (((x) >> 0) & 0x1) +#define C_0286D0_GEN_INDEX_PIX 0xFFFFFFFE +#define S_0286D0_GEN_INDEX_PIX_ADDR(x) (((x) & 0x7F) << 1) +#define G_0286D0_GEN_INDEX_PIX_ADDR(x) (((x) >> 1) & 0x7F) +#define C_0286D0_GEN_INDEX_PIX_ADDR 0xFFFFFF01 +#define S_0286D0_FRONT_FACE_ENA(x) (((x) & 0x1) << 8) +#define G_0286D0_FRONT_FACE_ENA(x) (((x) >> 8) & 0x1) +#define C_0286D0_FRONT_FACE_ENA 0xFFFFFEFF +#define S_0286D0_FRONT_FACE_CHAN(x) (((x) & 0x3) << 9) +#define G_0286D0_FRONT_FACE_CHAN(x) (((x) >> 9) & 0x3) +#define C_0286D0_FRONT_FACE_CHAN 0xFFFFF9FF +#define S_0286D0_FRONT_FACE_ALL_BITS(x) (((x) & 0x1) << 11) +#define G_0286D0_FRONT_FACE_ALL_BITS(x) (((x) >> 11) & 0x1) +#define C_0286D0_FRONT_FACE_ALL_BITS 0xFFFFF7FF +#define S_0286D0_FRONT_FACE_ADDR(x) (((x) & 0x1F) << 12) +#define G_0286D0_FRONT_FACE_ADDR(x) (((x) >> 12) & 0x1F) +#define C_0286D0_FRONT_FACE_ADDR 0xFFFE0FFF +#define S_0286D0_FOG_ADDR(x) (((x) & 0x7F) << 17) +#define G_0286D0_FOG_ADDR(x) (((x) >> 17) & 0x7F) +#define C_0286D0_FOG_ADDR 0xFF01FFFF +#define S_0286D0_FIXED_PT_POSITION_ENA(x) (((x) & 0x1) << 24) +#define G_0286D0_FIXED_PT_POSITION_ENA(x) (((x) >> 24) & 0x1) +#define C_0286D0_FIXED_PT_POSITION_ENA 0xFEFFFFFF +#define S_0286D0_FIXED_PT_POSITION_ADDR(x) (((x) & 0x1F) << 25) +#define G_0286D0_FIXED_PT_POSITION_ADDR(x) (((x) >> 25) & 0x1F) +#define C_0286D0_FIXED_PT_POSITION_ADDR 0xC1FFFFFF +#define R_0286C4_SPI_VS_OUT_CONFIG 0x0286C4 +#define S_0286C4_VS_PER_COMPONENT(x) (((x) & 0x1) << 0) +#define G_0286C4_VS_PER_COMPONENT(x) (((x) >> 0) & 0x1) +#define C_0286C4_VS_PER_COMPONENT 0xFFFFFFFE +#define S_0286C4_VS_EXPORT_COUNT(x) (((x) & 0x1F) << 1) +#define G_0286C4_VS_EXPORT_COUNT(x) (((x) >> 1) & 0x1F) +#define C_0286C4_VS_EXPORT_COUNT 0xFFFFFFC1 +#define S_0286C4_VS_EXPORTS_FOG(x) (((x) & 0x1) << 8) +#define G_0286C4_VS_EXPORTS_FOG(x) (((x) >> 8) & 0x1) +#define C_0286C4_VS_EXPORTS_FOG 0xFFFFFEFF +#define S_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x1F) << 9) +#define G_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) >> 9) & 0x1F) +#define C_0286C4_VS_OUT_FOG_VEC_ADDR 0xFFFFC1FF +#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240 +#define S_028240_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028240_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028240_TL_X 0xFFFFC000 +#define S_028240_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028240_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028240_TL_Y 0xC000FFFF +#define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244 +#define S_028244_BR_X(x) (((x) & 0x3FFF) << 0) +#define G_028244_BR_X(x) (((x) >> 0) & 0x3FFF) +#define C_028244_BR_X 0xFFFFC000 +#define S_028244_BR_Y(x) (((x) & 0x3FFF) << 16) +#define G_028244_BR_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028244_BR_Y 0xC000FFFF +#define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030 +#define S_028030_TL_X(x) (((x) & 0x7FFF) << 0) +#define G_028030_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028030_TL_X 0xFFFF8000 +#define S_028030_TL_Y(x) (((x) & 0x7FFF) << 16) +#define G_028030_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028030_TL_Y 0x8000FFFF +#define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034 +#define S_028034_BR_X(x) (((x) & 0x7FFF) << 0) +#define G_028034_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028034_BR_X 0xFFFF8000 +#define S_028034_BR_Y(x) (((x) & 0x7FFF) << 16) +#define G_028034_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028034_BR_Y 0x8000FFFF +#define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204 +#define S_028204_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028204_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028204_TL_X 0xFFFFC000 +#define S_028204_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028204_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028204_TL_Y 0xC000FFFF +#define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208 +#define S_028208_BR_X(x) (((x) & 0x3FFF) << 0) +#define G_028208_BR_X(x) (((x) >> 0) & 0x3FFF) +#define C_028208_BR_X 0xFFFFC000 +#define S_028208_BR_Y(x) (((x) & 0x3FFF) << 16) +#define G_028208_BR_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028208_BR_Y 0xC000FFFF +#define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0 +#define S_0287F0_SOURCE_SELECT(x) (((x) & 0x3) << 0) +#define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x3) +#define C_0287F0_SOURCE_SELECT 0xFFFFFFFC +#define S_0287F0_MAJOR_MODE(x) (((x) & 0x3) << 2) +#define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x3) +#define C_0287F0_MAJOR_MODE 0xFFFFFFF3 +#define S_0287F0_SPRITE_EN(x) (((x) & 0x1) << 4) +#define G_0287F0_SPRITE_EN(x) (((x) >> 4) & 0x1) +#define C_0287F0_SPRITE_EN 0xFFFFFFEF +#define S_0287F0_NOT_EOP(x) (((x) & 0x1) << 5) +#define G_0287F0_NOT_EOP(x) (((x) >> 5) & 0x1) +#define C_0287F0_NOT_EOP 0xFFFFFFDF +#define S_0287F0_USE_OPAQUE(x) (((x) & 0x1) << 6) +#define G_0287F0_USE_OPAQUE(x) (((x) >> 6) & 0x1) +#define C_0287F0_USE_OPAQUE 0xFFFFFFBF +#define R_0280A0_CB_COLOR0_INFO 0x0280A0 +#define R_0280A4_CB_COLOR1_INFO 0x0280A4 +#define R_0280A8_CB_COLOR2_INFO 0x0280A8 +#define R_0280AC_CB_COLOR3_INFO 0x0280AC +#define R_0280B0_CB_COLOR4_INFO 0x0280B0 +#define R_0280B4_CB_COLOR5_INFO 0x0280B4 +#define R_0280B8_CB_COLOR6_INFO 0x0280B8 +#define R_0280BC_CB_COLOR7_INFO 0x0280BC +#define R_02800C_DB_DEPTH_BASE 0x02800C +#define R_028000_DB_DEPTH_SIZE 0x028000 +#define R_028004_DB_DEPTH_VIEW 0x028004 +#define R_028010_DB_DEPTH_INFO 0x028010 +#define R_028D24_DB_HTILE_SURFACE 0x028D24 +#define R_028D34_DB_PREFETCH_LIMIT 0x028D34 +#define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4 +#define R_028A48_PA_SC_MPASS_PS_CNTL 0x028A48 +#define R_028C00_PA_SC_LINE_CNTL 0x028C00 +#define R_028C04_PA_SC_AA_CONFIG 0x028C04 +#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX 0x028C1C +#define R_028C48_PA_SC_AA_MASK 0x028C48 +#define R_028810_PA_CL_CLIP_CNTL 0x028810 +#define R_02881C_PA_CL_VS_OUT_CNTL 0x02881C +#define R_028820_PA_CL_NANINF_CNTL 0x028820 +#define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x028C0C +#define R_028C10_PA_CL_GB_VERT_DISC_ADJ 0x028C10 +#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ 0x028C14 +#define R_028C18_PA_CL_GB_HORZ_DISC_ADJ 0x028C18 +#define R_028814_PA_SU_SC_MODE_CNTL 0x028814 +#define R_028A00_PA_SU_POINT_SIZE 0x028A00 +#define R_028A04_PA_SU_POINT_MINMAX 0x028A04 +#define R_028A08_PA_SU_LINE_CNTL 0x028A08 +#define R_028A0C_PA_SC_LINE_STIPPLE 0x028A0C +#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x028DF8 +#define R_028DFC_PA_SU_POLY_OFFSET_CLAMP 0x028DFC +#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE 0x028E00 +#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x028E04 +#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE 0x028E08 +#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x028E0C +#define R_028818_PA_CL_VTE_CNTL 0x028818 +#define R_02843C_PA_CL_VPORT_XSCALE_0 0x02843C +#define R_028444_PA_CL_VPORT_YSCALE_0 0x028444 +#define R_02844C_PA_CL_VPORT_ZSCALE_0 0x02844C +#define R_028440_PA_CL_VPORT_XOFFSET_0 0x028440 +#define R_028448_PA_CL_VPORT_YOFFSET_0 0x028448 +#define R_028450_PA_CL_VPORT_ZOFFSET_0 0x028450 +#define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250 +#define R_028254_PA_SC_VPORT_SCISSOR_0_BR 0x028254 +#define R_028780_CB_BLEND0_CONTROL 0x028780 +#define R_028784_CB_BLEND1_CONTROL 0x028784 +#define R_028788_CB_BLEND2_CONTROL 0x028788 +#define R_02878C_CB_BLEND3_CONTROL 0x02878C +#define R_028790_CB_BLEND4_CONTROL 0x028790 +#define R_028794_CB_BLEND5_CONTROL 0x028794 +#define R_028798_CB_BLEND6_CONTROL 0x028798 +#define R_02879C_CB_BLEND7_CONTROL 0x02879C +#define R_028804_CB_BLEND_CONTROL 0x028804 +#define R_028028_DB_STENCIL_CLEAR 0x028028 +#define R_02802C_DB_DEPTH_CLEAR 0x02802C +#define R_028430_DB_STENCILREFMASK 0x028430 +#define R_028434_DB_STENCILREFMASK_BF 0x028434 +#define R_028800_DB_DEPTH_CONTROL 0x028800 +#define R_02880C_DB_SHADER_CONTROL 0x02880C +#define R_028D0C_DB_RENDER_CONTROL 0x028D0C +#define S_028D0C_DEPTH_CLEAR_ENABLE(x) (((x) & 0x1) << 0) +#define S_028D0C_STENCIL_CLEAR_ENABLE(x) (((x) & 0x1) << 1) +#define S_028D0C_DEPTH_COPY_ENABLE(x) (((x) & 0x1) << 2) +#define S_028D0C_STENCIL_COPY_ENABLE(x) (((x) & 0x1) << 3) +#define S_028D0C_RESUMMARIZE_ENABLE(x) (((x) & 0x1) << 4) +#define S_028D0C_STENCIL_COMPRESS_DISABLE(x) (((x) & 0x1) << 5) +#define S_028D0C_DEPTH_COMPRESS_DISABLE(x) (((x) & 0x1) << 6) +#define S_028D0C_COPY_CENTROID(x) (((x) & 0x1) << 7) +#define S_028D0C_COPY_SAMPLE(x) (((x) & 0x1) << 8) +#define S_028D0C_R700_PERFECT_ZPASS_COUNTS(x) (((x) & 0x1) << 15) +#define R_028D10_DB_RENDER_OVERRIDE 0x028D10 +#define R_028D2C_DB_SRESULTS_COMPARE_STATE1 0x028D2C +#define R_028D30_DB_PRELOAD_CONTROL 0x028D30 +#define R_028D44_DB_ALPHA_TO_MASK 0x028D44 +#define R_028868_SQ_PGM_RESOURCES_VS 0x028868 +#define R_0286CC_SPI_PS_IN_CONTROL_0 0x0286CC +#define R_0286D0_SPI_PS_IN_CONTROL_1 0x0286D0 +#define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 +#define R_028648_SPI_PS_INPUT_CNTL_1 0x028648 +#define R_02864C_SPI_PS_INPUT_CNTL_2 0x02864C +#define R_028650_SPI_PS_INPUT_CNTL_3 0x028650 +#define R_028654_SPI_PS_INPUT_CNTL_4 0x028654 +#define R_028658_SPI_PS_INPUT_CNTL_5 0x028658 +#define R_02865C_SPI_PS_INPUT_CNTL_6 0x02865C +#define R_028660_SPI_PS_INPUT_CNTL_7 0x028660 +#define R_028664_SPI_PS_INPUT_CNTL_8 0x028664 +#define R_028668_SPI_PS_INPUT_CNTL_9 0x028668 +#define R_02866C_SPI_PS_INPUT_CNTL_10 0x02866C +#define R_028670_SPI_PS_INPUT_CNTL_11 0x028670 +#define R_028674_SPI_PS_INPUT_CNTL_12 0x028674 +#define R_028678_SPI_PS_INPUT_CNTL_13 0x028678 +#define R_02867C_SPI_PS_INPUT_CNTL_14 0x02867C +#define R_028680_SPI_PS_INPUT_CNTL_15 0x028680 +#define R_028684_SPI_PS_INPUT_CNTL_16 0x028684 +#define R_028688_SPI_PS_INPUT_CNTL_17 0x028688 +#define R_02868C_SPI_PS_INPUT_CNTL_18 0x02868C +#define R_028690_SPI_PS_INPUT_CNTL_19 0x028690 +#define R_028694_SPI_PS_INPUT_CNTL_20 0x028694 +#define R_028698_SPI_PS_INPUT_CNTL_21 0x028698 +#define R_02869C_SPI_PS_INPUT_CNTL_22 0x02869C +#define R_0286A0_SPI_PS_INPUT_CNTL_23 0x0286A0 +#define R_0286A4_SPI_PS_INPUT_CNTL_24 0x0286A4 +#define R_0286A8_SPI_PS_INPUT_CNTL_25 0x0286A8 +#define R_0286AC_SPI_PS_INPUT_CNTL_26 0x0286AC +#define R_0286B0_SPI_PS_INPUT_CNTL_27 0x0286B0 +#define R_0286B4_SPI_PS_INPUT_CNTL_28 0x0286B4 +#define R_0286B8_SPI_PS_INPUT_CNTL_29 0x0286B8 +#define R_0286BC_SPI_PS_INPUT_CNTL_30 0x0286BC +#define R_0286C0_SPI_PS_INPUT_CNTL_31 0x0286C0 +#define R_028850_SQ_PGM_RESOURCES_PS 0x028850 +#define R_028854_SQ_PGM_EXPORTS_PS 0x028854 +#define R_008958_VGT_PRIMITIVE_TYPE 0x008958 +#define R_028A7C_VGT_DMA_INDEX_TYPE 0x028A7C +#define R_028A88_VGT_DMA_NUM_INSTANCES 0x028A88 +#define R_008970_VGT_NUM_INDICES 0x008970 +#define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0 +#define R_028238_CB_TARGET_MASK 0x028238 +#define R_02823C_CB_SHADER_MASK 0x02823C +#define R_028060_CB_COLOR0_SIZE 0x028060 +#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) +#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) +#define C_028060_PITCH_TILE_MAX 0xFFFFFC00 +#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) +#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) +#define C_028060_SLICE_TILE_MAX 0xC00003FF +#define R_028064_CB_COLOR1_SIZE 0x028064 +#define R_028068_CB_COLOR2_SIZE 0x028068 +#define R_02806C_CB_COLOR3_SIZE 0x02806C +#define R_028070_CB_COLOR4_SIZE 0x028070 +#define R_028074_CB_COLOR5_SIZE 0x028074 +#define R_028078_CB_COLOR6_SIZE 0x028078 +#define R_02807C_CB_COLOR7_SIZE 0x02807C +#define R_028040_CB_COLOR0_BASE 0x028040 +#define R_028044_CB_COLOR1_BASE 0x028044 +#define R_028048_CB_COLOR2_BASE 0x028048 +#define R_02804C_CB_COLOR3_BASE 0x02804C +#define R_028050_CB_COLOR4_BASE 0x028050 +#define R_028054_CB_COLOR5_BASE 0x028054 +#define R_028058_CB_COLOR6_BASE 0x028058 +#define R_02805C_CB_COLOR7_BASE 0x02805C +#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240 +#define S_028240_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028240_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028240_TL_X 0xFFFFC000 +#define S_028240_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028240_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028240_TL_Y 0xC000FFFF +#define R_028C04_PA_SC_AA_CONFIG 0x028C04 +#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) +#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) +#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC +#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) +#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) +#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF +#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) +#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) +#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF +#define R_0288CC_SQ_PGM_CF_OFFSET_PS 0x0288CC +#define R_0288DC_SQ_PGM_CF_OFFSET_FS 0x0288DC +#define R_0288D0_SQ_PGM_CF_OFFSET_VS 0x0288D0 +#define R_028840_SQ_PGM_START_PS 0x028840 +#define R_028894_SQ_PGM_START_FS 0x028894 +#define R_028858_SQ_PGM_START_VS 0x028858 +#define R_028080_CB_COLOR0_VIEW 0x028080 +#define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) +#define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) +#define C_028080_SLICE_START 0xFFFFF800 +#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) +#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) +#define C_028080_SLICE_MAX 0xFF001FFF +#define R_028084_CB_COLOR1_VIEW 0x028084 +#define R_028088_CB_COLOR2_VIEW 0x028088 +#define R_02808C_CB_COLOR3_VIEW 0x02808C +#define R_028090_CB_COLOR4_VIEW 0x028090 +#define R_028094_CB_COLOR5_VIEW 0x028094 +#define R_028098_CB_COLOR6_VIEW 0x028098 +#define R_02809C_CB_COLOR7_VIEW 0x02809C +#define R_028100_CB_COLOR0_MASK 0x028100 +#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) +#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) +#define C_028100_CMASK_BLOCK_MAX 0xFFFFF000 +#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) +#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF) +#define C_028100_FMASK_TILE_MAX 0x00000FFF +#define R_028104_CB_COLOR1_MASK 0x028104 +#define R_028108_CB_COLOR2_MASK 0x028108 +#define R_02810C_CB_COLOR3_MASK 0x02810C +#define R_028110_CB_COLOR4_MASK 0x028110 +#define R_028114_CB_COLOR5_MASK 0x028114 +#define R_028118_CB_COLOR6_MASK 0x028118 +#define R_02811C_CB_COLOR7_MASK 0x02811C +#define R_028040_CB_COLOR0_BASE 0x028040 +#define S_028040_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028040_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028040_BASE_256B 0x00000000 +#define R_0280E0_CB_COLOR0_FRAG 0x0280E0 +#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0280E0_BASE_256B 0x00000000 +#define R_0280E4_CB_COLOR1_FRAG 0x0280E4 +#define R_0280E8_CB_COLOR2_FRAG 0x0280E8 +#define R_0280EC_CB_COLOR3_FRAG 0x0280EC +#define R_0280F0_CB_COLOR4_FRAG 0x0280F0 +#define R_0280F4_CB_COLOR5_FRAG 0x0280F4 +#define R_0280F8_CB_COLOR6_FRAG 0x0280F8 +#define R_0280FC_CB_COLOR7_FRAG 0x0280FC +#define R_0280C0_CB_COLOR0_TILE 0x0280C0 +#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0280C0_BASE_256B 0x00000000 +#define R_0280C4_CB_COLOR1_TILE 0x0280C4 +#define R_0280C8_CB_COLOR2_TILE 0x0280C8 +#define R_0280CC_CB_COLOR3_TILE 0x0280CC +#define R_0280D0_CB_COLOR4_TILE 0x0280D0 +#define R_0280D4_CB_COLOR5_TILE 0x0280D4 +#define R_0280D8_CB_COLOR6_TILE 0x0280D8 +#define R_0280DC_CB_COLOR7_TILE 0x0280DC +#define R_028808_CB_COLOR_CONTROL 0x028808 +#define S_028808_FOG_ENABLE(x) (((x) & 0x1) << 0) +#define G_028808_FOG_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028808_FOG_ENABLE 0xFFFFFFFE +#define S_028808_MULTIWRITE_ENABLE(x) (((x) & 0x1) << 1) +#define G_028808_MULTIWRITE_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028808_MULTIWRITE_ENABLE 0xFFFFFFFD +#define S_028808_DITHER_ENABLE(x) (((x) & 0x1) << 2) +#define G_028808_DITHER_ENABLE(x) (((x) >> 2) & 0x1) +#define C_028808_DITHER_ENABLE 0xFFFFFFFB +#define S_028808_DEGAMMA_ENABLE(x) (((x) & 0x1) << 3) +#define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1) +#define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7 +#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) +#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) +#define C_028808_SPECIAL_OP 0xFFFFFF8F +#define S_028808_PER_MRT_BLEND(x) (((x) & 0x1) << 7) +#define G_028808_PER_MRT_BLEND(x) (((x) >> 7) & 0x1) +#define C_028808_PER_MRT_BLEND 0xFFFFFF7F +#define S_028808_TARGET_BLEND_ENABLE(x) (((x) & 0xFF) << 8) +#define G_028808_TARGET_BLEND_ENABLE(x) (((x) >> 8) & 0xFF) +#define C_028808_TARGET_BLEND_ENABLE 0xFFFF00FF +#define S_028808_ROP3(x) (((x) & 0xFF) << 16) +#define G_028808_ROP3(x) (((x) >> 16) & 0xFF) +#define C_028808_ROP3 0xFF00FFFF +#define R_028614_SPI_VS_OUT_ID_0 0x028614 +#define S_028614_SEMANTIC_0(x) (((x) & 0xFF) << 0) +#define G_028614_SEMANTIC_0(x) (((x) >> 0) & 0xFF) +#define C_028614_SEMANTIC_0 0xFFFFFF00 +#define S_028614_SEMANTIC_1(x) (((x) & 0xFF) << 8) +#define G_028614_SEMANTIC_1(x) (((x) >> 8) & 0xFF) +#define C_028614_SEMANTIC_1 0xFFFF00FF +#define S_028614_SEMANTIC_2(x) (((x) & 0xFF) << 16) +#define G_028614_SEMANTIC_2(x) (((x) >> 16) & 0xFF) +#define C_028614_SEMANTIC_2 0xFF00FFFF +#define S_028614_SEMANTIC_3(x) (((x) & 0xFF) << 24) +#define G_028614_SEMANTIC_3(x) (((x) >> 24) & 0xFF) +#define C_028614_SEMANTIC_3 0x00FFFFFF +#define R_028618_SPI_VS_OUT_ID_1 0x028618 +#define R_02861C_SPI_VS_OUT_ID_2 0x02861C +#define R_028620_SPI_VS_OUT_ID_3 0x028620 +#define R_028624_SPI_VS_OUT_ID_4 0x028624 +#define R_028628_SPI_VS_OUT_ID_5 0x028628 +#define R_02862C_SPI_VS_OUT_ID_6 0x02862C +#define R_028630_SPI_VS_OUT_ID_7 0x028630 +#define R_028634_SPI_VS_OUT_ID_8 0x028634 +#define R_028638_SPI_VS_OUT_ID_9 0x028638 +#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 +#define S_038000_DIM(x) (((x) & 0x7) << 0) +#define G_038000_DIM(x) (((x) >> 0) & 0x7) +#define C_038000_DIM 0xFFFFFFF8 +#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) +#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) +#define C_038000_TILE_MODE 0xFFFFFF87 +#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) +#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) +#define C_038000_TILE_TYPE 0xFFFFFF7F +#define S_038000_PITCH(x) (((x) & 0x7FF) << 8) +#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) +#define C_038000_PITCH 0xFFF800FF +#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) +#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) +#define C_038000_TEX_WIDTH 0x0007FFFF +#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 +#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) +#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) +#define C_038004_TEX_HEIGHT 0xFFFFE000 +#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) +#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) +#define C_038004_TEX_DEPTH 0xFC001FFF +#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) +#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) +#define C_038004_DATA_FORMAT 0x03FFFFFF +#define V_038004_COLOR_INVALID 0x00000000 +#define V_038004_COLOR_8 0x00000001 +#define V_038004_COLOR_4_4 0x00000002 +#define V_038004_COLOR_3_3_2 0x00000003 +#define V_038004_COLOR_16 0x00000005 +#define V_038004_COLOR_16_FLOAT 0x00000006 +#define V_038004_COLOR_8_8 0x00000007 +#define V_038004_COLOR_5_6_5 0x00000008 +#define V_038004_COLOR_6_5_5 0x00000009 +#define V_038004_COLOR_1_5_5_5 0x0000000A +#define V_038004_COLOR_4_4_4_4 0x0000000B +#define V_038004_COLOR_5_5_5_1 0x0000000C +#define V_038004_COLOR_32 0x0000000D +#define V_038004_COLOR_32_FLOAT 0x0000000E +#define V_038004_COLOR_16_16 0x0000000F +#define V_038004_COLOR_16_16_FLOAT 0x00000010 +#define V_038004_COLOR_8_24 0x00000011 +#define V_038004_COLOR_8_24_FLOAT 0x00000012 +#define V_038004_COLOR_24_8 0x00000013 +#define V_038004_COLOR_24_8_FLOAT 0x00000014 +#define V_038004_COLOR_10_11_11 0x00000015 +#define V_038004_COLOR_10_11_11_FLOAT 0x00000016 +#define V_038004_COLOR_11_11_10 0x00000017 +#define V_038004_COLOR_11_11_10_FLOAT 0x00000018 +#define V_038004_COLOR_2_10_10_10 0x00000019 +#define V_038004_COLOR_8_8_8_8 0x0000001A +#define V_038004_COLOR_10_10_10_2 0x0000001B +#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C +#define V_038004_COLOR_32_32 0x0000001D +#define V_038004_COLOR_32_32_FLOAT 0x0000001E +#define V_038004_COLOR_16_16_16_16 0x0000001F +#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 +#define V_038004_COLOR_32_32_32_32 0x00000022 +#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 +#define R_038008_SQ_TEX_RESOURCE_WORD2_0 0x038008 +#define S_038008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) +#define G_038008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_038008_BASE_ADDRESS 0x00000000 +#define R_03800C_SQ_TEX_RESOURCE_WORD3_0 0x03800C +#define S_03800C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) +#define G_03800C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_03800C_MIP_ADDRESS 0x00000000 +#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 +#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) +#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) +#define C_038010_FORMAT_COMP_X 0xFFFFFFFC +#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) +#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) +#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 +#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) +#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) +#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF +#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) +#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) +#define C_038010_FORMAT_COMP_W 0xFFFFFF3F +#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) +#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) +#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF +#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) +#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) +#define C_038010_SRF_MODE_ALL 0xFFFFFBFF +#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) +#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) +#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF +#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) +#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) +#define C_038010_ENDIAN_SWAP 0xFFFFCFFF +#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) +#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) +#define C_038010_REQUEST_SIZE 0xFFFF3FFF +#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) +#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) +#define C_038010_DST_SEL_X 0xFFF8FFFF +#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) +#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) +#define C_038010_DST_SEL_Y 0xFFC7FFFF +#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) +#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) +#define C_038010_DST_SEL_Z 0xFE3FFFFF +#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) +#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) +#define C_038010_DST_SEL_W 0xF1FFFFFF +#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) +#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) +#define C_038010_BASE_LEVEL 0x0FFFFFFF +#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 +#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) +#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) +#define C_038014_LAST_LEVEL 0xFFFFFFF0 +#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) +#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) +#define C_038014_BASE_ARRAY 0xFFFE000F +#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) +#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) +#define C_038014_LAST_ARRAY 0xC001FFFF +#define R_038018_SQ_TEX_RESOURCE_WORD6_0 0x038018 +#define S_038018_MPEG_CLAMP(x) (((x) & 0x3) << 0) +#define G_038018_MPEG_CLAMP(x) (((x) >> 0) & 0x3) +#define C_038018_MPEG_CLAMP 0xFFFFFFFC +#define S_038018_PERF_MODULATION(x) (((x) & 0x7) << 5) +#define G_038018_PERF_MODULATION(x) (((x) >> 5) & 0x7) +#define C_038018_PERF_MODULATION 0xFFFFFF1F +#define S_038018_INTERLACED(x) (((x) & 0x1) << 8) +#define G_038018_INTERLACED(x) (((x) >> 8) & 0x1) +#define C_038018_INTERLACED 0xFFFFFEFF +#define S_038018_TYPE(x) (((x) & 0x3) << 30) +#define G_038018_TYPE(x) (((x) >> 30) & 0x3) +#define C_038018_TYPE 0x3FFFFFFF +#define R_008040_WAIT_UNTIL 0x008040 +#define S_008040_WAIT_CP_DMA_IDLE(x) (((x) & 0x1) << 8) +#define G_008040_WAIT_CP_DMA_IDLE(x) (((x) >> 8) & 0x1) +#define C_008040_WAIT_CP_DMA_IDLE 0xFFFFFEFF +#define S_008040_WAIT_CMDFIFO(x) (((x) & 0x1) << 10) +#define G_008040_WAIT_CMDFIFO(x) (((x) >> 10) & 0x1) +#define C_008040_WAIT_CMDFIFO 0xFFFFFBFF +#define S_008040_WAIT_2D_IDLE(x) (((x) & 0x1) << 14) +#define G_008040_WAIT_2D_IDLE(x) (((x) >> 14) & 0x1) +#define C_008040_WAIT_2D_IDLE 0xFFFFBFFF +#define S_008040_WAIT_3D_IDLE(x) (((x) & 0x1) << 15) +#define G_008040_WAIT_3D_IDLE(x) (((x) >> 15) & 0x1) +#define C_008040_WAIT_3D_IDLE 0xFFFF7FFF +#define S_008040_WAIT_2D_IDLECLEAN(x) (((x) & 0x1) << 16) +#define G_008040_WAIT_2D_IDLECLEAN(x) (((x) >> 16) & 0x1) +#define C_008040_WAIT_2D_IDLECLEAN 0xFFFEFFFF +#define S_008040_WAIT_3D_IDLECLEAN(x) (((x) & 0x1) << 17) +#define G_008040_WAIT_3D_IDLECLEAN(x) (((x) >> 17) & 0x1) +#define C_008040_WAIT_3D_IDLECLEAN 0xFFFDFFFF +#define S_008040_WAIT_EXTERN_SIG(x) (((x) & 0x1) << 19) +#define G_008040_WAIT_EXTERN_SIG(x) (((x) >> 19) & 0x1) +#define C_008040_WAIT_EXTERN_SIG 0xFFF7FFFF +#define S_008040_CMDFIFO_ENTRIES(x) (((x) & 0x1F) << 20) +#define G_008040_CMDFIFO_ENTRIES(x) (((x) >> 20) & 0x1F) +#define C_008040_CMDFIFO_ENTRIES 0xFE0FFFFF +#define R_008958_VGT_PRIMITIVE_TYPE 0x008958 +#define S_008958_PRIM_TYPE(x) (((x) & 0x3F) << 0) +#define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F) +#define C_008958_PRIM_TYPE 0xFFFFFFC0 +#define R_008C00_SQ_CONFIG 0x008C00 +#define S_008C00_VC_ENABLE(x) (((x) & 0x1) << 0) +#define G_008C00_VC_ENABLE(x) (((x) >> 0) & 0x1) +#define C_008C00_VC_ENABLE 0xFFFFFFFE +#define S_008C00_EXPORT_SRC_C(x) (((x) & 0x1) << 1) +#define G_008C00_EXPORT_SRC_C(x) (((x) >> 1) & 0x1) +#define C_008C00_EXPORT_SRC_C 0xFFFFFFFD +#define S_008C00_DX9_CONSTS(x) (((x) & 0x1) << 2) +#define G_008C00_DX9_CONSTS(x) (((x) >> 2) & 0x1) +#define C_008C00_DX9_CONSTS 0xFFFFFFFB +#define S_008C00_ALU_INST_PREFER_VECTOR(x) (((x) & 0x1) << 3) +#define G_008C00_ALU_INST_PREFER_VECTOR(x) (((x) >> 3) & 0x1) +#define C_008C00_ALU_INST_PREFER_VECTOR 0xFFFFFFF7 +#define S_008C00_DX10_CLAMP(x) (((x) & 0x1) << 4) +#define G_008C00_DX10_CLAMP(x) (((x) >> 4) & 0x1) +#define C_008C00_DX10_CLAMP 0xFFFFFFEF +#define S_008C00_ALU_PREFER_ONE_WATERFALL(x) (((x) & 0x1) << 5) +#define G_008C00_ALU_PREFER_ONE_WATERFALL(x) (((x) >> 5) & 0x1) +#define C_008C00_ALU_PREFER_ONE_WATERFALL 0xFFFFFFDF +#define S_008C00_ALU_MAX_ONE_WATERFALL(x) (((x) & 0x1) << 6) +#define G_008C00_ALU_MAX_ONE_WATERFALL(x) (((x) >> 6) & 0x1) +#define C_008C00_ALU_MAX_ONE_WATERFALL 0xFFFFFFBF +#define S_008C00_CLAUSE_SEQ_PRIO(x) (((x) & 0x3) << 8) +#define G_008C00_CLAUSE_SEQ_PRIO(x) (((x) >> 8) & 0x3) +#define C_008C00_CLAUSE_SEQ_PRIO 0xFFFFFCFF +#define S_008C00_PS_PRIO(x) (((x) & 0x3) << 24) +#define G_008C00_PS_PRIO(x) (((x) >> 24) & 0x3) +#define C_008C00_PS_PRIO 0xFCFFFFFF +#define S_008C00_VS_PRIO(x) (((x) & 0x3) << 26) +#define G_008C00_VS_PRIO(x) (((x) >> 26) & 0x3) +#define C_008C00_VS_PRIO 0xF3FFFFFF +#define S_008C00_GS_PRIO(x) (((x) & 0x3) << 28) +#define G_008C00_GS_PRIO(x) (((x) >> 28) & 0x3) +#define C_008C00_GS_PRIO 0xCFFFFFFF +#define S_008C00_ES_PRIO(x) (((x) & 0x3) << 30) +#define G_008C00_ES_PRIO(x) (((x) >> 30) & 0x3) +#define C_008C00_ES_PRIO 0x3FFFFFFF +#define R_008C04_SQ_GPR_RESOURCE_MGMT_1 0x008C04 +#define S_008C04_NUM_PS_GPRS(x) (((x) & 0xFF) << 0) +#define G_008C04_NUM_PS_GPRS(x) (((x) >> 0) & 0xFF) +#define C_008C04_NUM_PS_GPRS 0xFFFFFF00 +#define S_008C04_NUM_VS_GPRS(x) (((x) & 0xFF) << 16) +#define G_008C04_NUM_VS_GPRS(x) (((x) >> 16) & 0xFF) +#define C_008C04_NUM_VS_GPRS 0xFF00FFFF +#define S_008C04_NUM_CLAUSE_TEMP_GPRS(x) (((x) & 0xF) << 28) +#define G_008C04_NUM_CLAUSE_TEMP_GPRS(x) (((x) >> 28) & 0xF) +#define C_008C04_NUM_CLAUSE_TEMP_GPRS 0x0FFFFFFF +#define R_008C08_SQ_GPR_RESOURCE_MGMT_2 0x008C08 +#define S_008C08_NUM_GS_GPRS(x) (((x) & 0xFF) << 0) +#define G_008C08_NUM_GS_GPRS(x) (((x) >> 0) & 0xFF) +#define C_008C08_NUM_GS_GPRS 0xFFFFFF00 +#define S_008C08_NUM_ES_GPRS(x) (((x) & 0xFF) << 16) +#define G_008C08_NUM_ES_GPRS(x) (((x) >> 16) & 0xFF) +#define C_008C08_NUM_ES_GPRS 0xFF00FFFF +#define R_008C0C_SQ_THREAD_RESOURCE_MGMT 0x008C0C +#define S_008C0C_NUM_PS_THREADS(x) (((x) & 0xFF) << 0) +#define G_008C0C_NUM_PS_THREADS(x) (((x) >> 0) & 0xFF) +#define C_008C0C_NUM_PS_THREADS 0xFFFFFF00 +#define S_008C0C_NUM_VS_THREADS(x) (((x) & 0xFF) << 8) +#define G_008C0C_NUM_VS_THREADS(x) (((x) >> 8) & 0xFF) +#define C_008C0C_NUM_VS_THREADS 0xFFFF00FF +#define S_008C0C_NUM_GS_THREADS(x) (((x) & 0xFF) << 16) +#define G_008C0C_NUM_GS_THREADS(x) (((x) >> 16) & 0xFF) +#define C_008C0C_NUM_GS_THREADS 0xFF00FFFF +#define S_008C0C_NUM_ES_THREADS(x) (((x) & 0xFF) << 24) +#define G_008C0C_NUM_ES_THREADS(x) (((x) >> 24) & 0xFF) +#define C_008C0C_NUM_ES_THREADS 0x00FFFFFF +#define R_008C10_SQ_STACK_RESOURCE_MGMT_1 0x008C10 +#define S_008C10_NUM_PS_STACK_ENTRIES(x) (((x) & 0xFFF) << 0) +#define G_008C10_NUM_PS_STACK_ENTRIES(x) (((x) >> 0) & 0xFFF) +#define C_008C10_NUM_PS_STACK_ENTRIES 0xFFFFF000 +#define S_008C10_NUM_VS_STACK_ENTRIES(x) (((x) & 0xFFF) << 16) +#define G_008C10_NUM_VS_STACK_ENTRIES(x) (((x) >> 16) & 0xFFF) +#define C_008C10_NUM_VS_STACK_ENTRIES 0xF000FFFF +#define R_008C14_SQ_STACK_RESOURCE_MGMT_2 0x008C14 +#define S_008C14_NUM_GS_STACK_ENTRIES(x) (((x) & 0xFFF) << 0) +#define G_008C14_NUM_GS_STACK_ENTRIES(x) (((x) >> 0) & 0xFFF) +#define C_008C14_NUM_GS_STACK_ENTRIES 0xFFFFF000 +#define S_008C14_NUM_ES_STACK_ENTRIES(x) (((x) & 0xFFF) << 16) +#define G_008C14_NUM_ES_STACK_ENTRIES(x) (((x) >> 16) & 0xFFF) +#define C_008C14_NUM_ES_STACK_ENTRIES 0xF000FFFF +#define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x008D8C +#define S_008D8C_RING0_OFFSET(x) (((x) & 0xFF) << 0) +#define G_008D8C_RING0_OFFSET(x) (((x) >> 0) & 0xFF) +#define C_008D8C_RING0_OFFSET 0xFFFFFF00 +#define S_008D8C_ISOLATE_ES_ENABLE(x) (((x) & 0x1) << 12) +#define G_008D8C_ISOLATE_ES_ENABLE(x) (((x) >> 12) & 0x1) +#define C_008D8C_ISOLATE_ES_ENABLE 0xFFFFEFFF +#define S_008D8C_ISOLATE_GS_ENABLE(x) (((x) & 0x1) << 13) +#define G_008D8C_ISOLATE_GS_ENABLE(x) (((x) >> 13) & 0x1) +#define C_008D8C_ISOLATE_GS_ENABLE 0xFFFFDFFF +#define S_008D8C_VS_PC_LIMIT_ENABLE(x) (((x) & 0x1) << 14) +#define G_008D8C_VS_PC_LIMIT_ENABLE(x) (((x) >> 14) & 0x1) +#define C_008D8C_VS_PC_LIMIT_ENABLE 0xFFFFBFFF +#define R_009508_TA_CNTL_AUX 0x009508 +#define S_009508_DISABLE_CUBE_WRAP(x) (((x) & 0x1) << 0) +#define G_009508_DISABLE_CUBE_WRAP(x) (((x) >> 0) & 0x1) +#define C_009508_DISABLE_CUBE_WRAP 0xFFFFFFFE +#define S_009508_SYNC_GRADIENT(x) (((x) & 0x1) << 24) +#define G_009508_SYNC_GRADIENT(x) (((x) >> 24) & 0x1) +#define C_009508_SYNC_GRADIENT 0xFEFFFFFF +#define S_009508_SYNC_WALKER(x) (((x) & 0x1) << 25) +#define G_009508_SYNC_WALKER(x) (((x) >> 25) & 0x1) +#define C_009508_SYNC_WALKER 0xFDFFFFFF +#define S_009508_SYNC_ALIGNER(x) (((x) & 0x1) << 26) +#define G_009508_SYNC_ALIGNER(x) (((x) >> 26) & 0x1) +#define C_009508_SYNC_ALIGNER 0xFBFFFFFF +#define S_009508_BILINEAR_PRECISION(x) (((x) & 0x1) << 31) +#define G_009508_BILINEAR_PRECISION(x) (((x) >> 31) & 0x1) +#define C_009508_BILINEAR_PRECISION 0x7FFFFFFF +#define R_009714_VC_ENHANCE 0x009714 +#define R_009830_DB_DEBUG 0x009830 +#define R_009838_DB_WATERMARKS 0x009838 +#define S_009838_DEPTH_FREE(x) (((x) & 0x1F) << 0) +#define G_009838_DEPTH_FREE(x) (((x) >> 0) & 0x1F) +#define C_009838_DEPTH_FREE 0xFFFFFFE0 +#define S_009838_DEPTH_FLUSH(x) (((x) & 0x3F) << 5) +#define G_009838_DEPTH_FLUSH(x) (((x) >> 5) & 0x3F) +#define C_009838_DEPTH_FLUSH 0xFFFFF81F +#define S_009838_FORCE_SUMMARIZE(x) (((x) & 0xF) << 11) +#define G_009838_FORCE_SUMMARIZE(x) (((x) >> 11) & 0xF) +#define C_009838_FORCE_SUMMARIZE 0xFFFF87FF +#define S_009838_DEPTH_PENDING_FREE(x) (((x) & 0x1F) << 15) +#define G_009838_DEPTH_PENDING_FREE(x) (((x) >> 15) & 0x1F) +#define C_009838_DEPTH_PENDING_FREE 0xFFF07FFF +#define S_009838_DEPTH_CACHELINE_FREE(x) (((x) & 0x1F) << 20) +#define G_009838_DEPTH_CACHELINE_FREE(x) (((x) >> 20) & 0x1F) +#define C_009838_DEPTH_CACHELINE_FREE 0xFE0FFFFF +#define S_009838_EARLY_Z_PANIC_DISABLE(x) (((x) & 0x1) << 25) +#define G_009838_EARLY_Z_PANIC_DISABLE(x) (((x) >> 25) & 0x1) +#define C_009838_EARLY_Z_PANIC_DISABLE 0xFDFFFFFF +#define S_009838_LATE_Z_PANIC_DISABLE(x) (((x) & 0x1) << 26) +#define G_009838_LATE_Z_PANIC_DISABLE(x) (((x) >> 26) & 0x1) +#define C_009838_LATE_Z_PANIC_DISABLE 0xFBFFFFFF +#define S_009838_RE_Z_PANIC_DISABLE(x) (((x) & 0x1) << 27) +#define G_009838_RE_Z_PANIC_DISABLE(x) (((x) >> 27) & 0x1) +#define C_009838_RE_Z_PANIC_DISABLE 0xF7FFFFFF +#define S_009838_DB_EXTRA_DEBUG(x) (((x) & 0xF) << 28) +#define G_009838_DB_EXTRA_DEBUG(x) (((x) >> 28) & 0xF) +#define C_009838_DB_EXTRA_DEBUG 0x0FFFFFFF +#define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030 +#define S_028030_TL_X(x) (((x) & 0x7FFF) << 0) +#define G_028030_TL_X(x) (((x) >> 0) & 0x7FFF) +#define C_028030_TL_X 0xFFFF8000 +#define S_028030_TL_Y(x) (((x) & 0x7FFF) << 16) +#define G_028030_TL_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028030_TL_Y 0x8000FFFF +#define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034 +#define S_028034_BR_X(x) (((x) & 0x7FFF) << 0) +#define G_028034_BR_X(x) (((x) >> 0) & 0x7FFF) +#define C_028034_BR_X 0xFFFF8000 +#define S_028034_BR_Y(x) (((x) & 0x7FFF) << 16) +#define G_028034_BR_Y(x) (((x) >> 16) & 0x7FFF) +#define C_028034_BR_Y 0x8000FFFF +#define R_028200_PA_SC_WINDOW_OFFSET 0x028200 +#define S_028200_WINDOW_X_OFFSET(x) (((x) & 0x7FFF) << 0) +#define G_028200_WINDOW_X_OFFSET(x) (((x) >> 0) & 0x7FFF) +#define C_028200_WINDOW_X_OFFSET 0xFFFF8000 +#define S_028200_WINDOW_Y_OFFSET(x) (((x) & 0x7FFF) << 16) +#define G_028200_WINDOW_Y_OFFSET(x) (((x) >> 16) & 0x7FFF) +#define C_028200_WINDOW_Y_OFFSET 0x8000FFFF +#define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204 +#define S_028204_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028204_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028204_TL_X 0xFFFFC000 +#define S_028204_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028204_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028204_TL_Y 0xC000FFFF +#define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208 +#define S_028208_BR_X(x) (((x) & 0x3FFF) << 0) +#define G_028208_BR_X(x) (((x) >> 0) & 0x3FFF) +#define C_028208_BR_X 0xFFFFC000 +#define S_028208_BR_Y(x) (((x) & 0x3FFF) << 16) +#define G_028208_BR_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028208_BR_Y 0xC000FFFF +#define R_02820C_PA_SC_CLIPRECT_RULE 0x02820C +#define S_02820C_CLIP_RULE(x) (((x) & 0xFFFF) << 0) +#define G_02820C_CLIP_RULE(x) (((x) >> 0) & 0xFFFF) +#define C_02820C_CLIP_RULE 0xFFFF0000 +#define R_028210_PA_SC_CLIPRECT_0_TL 0x028210 +#define S_028210_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028210_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028210_TL_X 0xFFFFC000 +#define S_028210_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028210_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028210_TL_Y 0xC000FFFF +#define R_028214_PA_SC_CLIPRECT_0_BR 0x028214 +#define S_028214_BR_X(x) (((x) & 0x3FFF) << 0) +#define G_028214_BR_X(x) (((x) >> 0) & 0x3FFF) +#define C_028214_BR_X 0xFFFFC000 +#define S_028214_BR_Y(x) (((x) & 0x3FFF) << 16) +#define G_028214_BR_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028214_BR_Y 0xC000FFFF +#define R_028218_PA_SC_CLIPRECT_1_TL 0x028218 +#define R_02821C_PA_SC_CLIPRECT_1_BR 0x02821C +#define R_028220_PA_SC_CLIPRECT_2_TL 0x028220 +#define R_028224_PA_SC_CLIPRECT_2_BR 0x028224 +#define R_028228_PA_SC_CLIPRECT_3_TL 0x028228 +#define R_02822C_PA_SC_CLIPRECT_3_BR 0x02822C +#define R_028230_PA_SC_EDGERULE 0x028230 +#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240 +#define S_028240_TL_X(x) (((x) & 0x3FFF) << 0) +#define G_028240_TL_X(x) (((x) >> 0) & 0x3FFF) +#define C_028240_TL_X 0xFFFFC000 +#define S_028240_TL_Y(x) (((x) & 0x3FFF) << 16) +#define G_028240_TL_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028240_TL_Y 0xC000FFFF +#define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) +#define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) +#define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF +#define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244 +#define S_028244_BR_X(x) (((x) & 0x3FFF) << 0) +#define G_028244_BR_X(x) (((x) >> 0) & 0x3FFF) +#define C_028244_BR_X 0xFFFFC000 +#define S_028244_BR_Y(x) (((x) & 0x3FFF) << 16) +#define G_028244_BR_Y(x) (((x) >> 16) & 0x3FFF) +#define C_028244_BR_Y 0xC000FFFF +#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0 +#define S_0282D0_VPORT_ZMIN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0282D0_VPORT_ZMIN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0282D0_VPORT_ZMIN 0x00000000 +#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4 +#define S_0282D4_VPORT_ZMAX(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0282D4_VPORT_ZMAX(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0282D4_VPORT_ZMAX 0x00000000 +#define R_028350_SX_MISC 0x028350 +#define S_028350_MULTIPASS(x) (((x) & 0x1) << 0) +#define G_028350_MULTIPASS(x) (((x) >> 0) & 0x1) +#define C_028350_MULTIPASS 0xFFFFFFFE +#define R_028380_SQ_VTX_SEMANTIC_0 0x028380 +#define S_028380_SEMANTIC_ID(x) (((x) & 0xFF) << 0) +#define G_028380_SEMANTIC_ID(x) (((x) >> 0) & 0xFF) +#define C_028380_SEMANTIC_ID 0xFFFFFF00 +#define R_028384_SQ_VTX_SEMANTIC_1 0x028384 +#define R_028388_SQ_VTX_SEMANTIC_2 0x028388 +#define R_02838C_SQ_VTX_SEMANTIC_3 0x02838C +#define R_028390_SQ_VTX_SEMANTIC_4 0x028390 +#define R_028394_SQ_VTX_SEMANTIC_5 0x028394 +#define R_028398_SQ_VTX_SEMANTIC_6 0x028398 +#define R_02839C_SQ_VTX_SEMANTIC_7 0x02839C +#define R_0283A0_SQ_VTX_SEMANTIC_8 0x0283A0 +#define R_0283A4_SQ_VTX_SEMANTIC_9 0x0283A4 +#define R_0283A8_SQ_VTX_SEMANTIC_10 0x0283A8 +#define R_0283AC_SQ_VTX_SEMANTIC_11 0x0283AC +#define R_0283B0_SQ_VTX_SEMANTIC_12 0x0283B0 +#define R_0283B4_SQ_VTX_SEMANTIC_13 0x0283B4 +#define R_0283B8_SQ_VTX_SEMANTIC_14 0x0283B8 +#define R_0283BC_SQ_VTX_SEMANTIC_15 0x0283BC +#define R_0283C0_SQ_VTX_SEMANTIC_16 0x0283C0 +#define R_0283C4_SQ_VTX_SEMANTIC_17 0x0283C4 +#define R_0283C8_SQ_VTX_SEMANTIC_18 0x0283C8 +#define R_0283CC_SQ_VTX_SEMANTIC_19 0x0283CC +#define R_0283D0_SQ_VTX_SEMANTIC_20 0x0283D0 +#define R_0283D4_SQ_VTX_SEMANTIC_21 0x0283D4 +#define R_0283D8_SQ_VTX_SEMANTIC_22 0x0283D8 +#define R_0283DC_SQ_VTX_SEMANTIC_23 0x0283DC +#define R_0283E0_SQ_VTX_SEMANTIC_24 0x0283E0 +#define R_0283E4_SQ_VTX_SEMANTIC_25 0x0283E4 +#define R_0283E8_SQ_VTX_SEMANTIC_26 0x0283E8 +#define R_0283EC_SQ_VTX_SEMANTIC_27 0x0283EC +#define R_0283F0_SQ_VTX_SEMANTIC_28 0x0283F0 +#define R_0283F4_SQ_VTX_SEMANTIC_29 0x0283F4 +#define R_0283F8_SQ_VTX_SEMANTIC_30 0x0283F8 +#define R_0283FC_SQ_VTX_SEMANTIC_31 0x0283FC +#define R_028400_VGT_MAX_VTX_INDX 0x028400 +#define S_028400_MAX_INDX(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028400_MAX_INDX(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028400_MAX_INDX 0x00000000 +#define R_028404_VGT_MIN_VTX_INDX 0x028404 +#define S_028404_MIN_INDX(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028404_MIN_INDX(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028404_MIN_INDX 0x00000000 +#define R_028408_VGT_INDX_OFFSET 0x028408 +#define S_028408_INDX_OFFSET(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028408_INDX_OFFSET(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028408_INDX_OFFSET 0x00000000 +#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x02840C +#define S_02840C_RESET_INDX(x) (((x) & 0xFFFFFFFF) << 0) +#define G_02840C_RESET_INDX(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_02840C_RESET_INDX 0x00000000 +#define R_028410_SX_ALPHA_TEST_CONTROL 0x028410 +#define S_028410_ALPHA_FUNC(x) (((x) & 0x7) << 0) +#define G_028410_ALPHA_FUNC(x) (((x) >> 0) & 0x7) +#define C_028410_ALPHA_FUNC 0xFFFFFFF8 +#define S_028410_ALPHA_TEST_ENABLE(x) (((x) & 0x1) << 3) +#define G_028410_ALPHA_TEST_ENABLE(x) (((x) >> 3) & 0x1) +#define C_028410_ALPHA_TEST_ENABLE 0xFFFFFFF7 +#define S_028410_ALPHA_TEST_BYPASS(x) (((x) & 0x1) << 8) +#define G_028410_ALPHA_TEST_BYPASS(x) (((x) >> 8) & 0x1) +#define C_028410_ALPHA_TEST_BYPASS 0xFFFFFEFF +#define R_028414_CB_BLEND_RED 0x028414 +#define S_028414_BLEND_RED(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028414_BLEND_RED(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028414_BLEND_RED 0x00000000 +#define R_028418_CB_BLEND_GREEN 0x028418 +#define S_028418_BLEND_GREEN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028418_BLEND_GREEN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028418_BLEND_GREEN 0x00000000 +#define R_02841C_CB_BLEND_BLUE 0x02841C +#define S_02841C_BLEND_BLUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_02841C_BLEND_BLUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_02841C_BLEND_BLUE 0x00000000 +#define R_028420_CB_BLEND_ALPHA 0x028420 +#define S_028420_BLEND_ALPHA(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028420_BLEND_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028420_BLEND_ALPHA 0x00000000 +#define R_028438_SX_ALPHA_REF 0x028438 +#define S_028438_ALPHA_REF(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028438_ALPHA_REF(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028438_ALPHA_REF 0x00000000 +#define R_0286C8_SPI_THREAD_GROUPING 0x0286C8 +#define S_0286C8_PS_GROUPING(x) (((x) & 0x1F) << 0) +#define G_0286C8_PS_GROUPING(x) (((x) >> 0) & 0x1F) +#define C_0286C8_PS_GROUPING 0xFFFFFFE0 +#define S_0286C8_VS_GROUPING(x) (((x) & 0x1F) << 8) +#define G_0286C8_VS_GROUPING(x) (((x) >> 8) & 0x1F) +#define C_0286C8_VS_GROUPING 0xFFFFE0FF +#define S_0286C8_GS_GROUPING(x) (((x) & 0x1F) << 16) +#define G_0286C8_GS_GROUPING(x) (((x) >> 16) & 0x1F) +#define C_0286C8_GS_GROUPING 0xFFE0FFFF +#define S_0286C8_ES_GROUPING(x) (((x) & 0x1F) << 24) +#define G_0286C8_ES_GROUPING(x) (((x) >> 24) & 0x1F) +#define C_0286C8_ES_GROUPING 0xE0FFFFFF +#define R_0286D8_SPI_INPUT_Z 0x0286D8 +#define S_0286D8_PROVIDE_Z_TO_SPI(x) (((x) & 0x1) << 0) +#define G_0286D8_PROVIDE_Z_TO_SPI(x) (((x) >> 0) & 0x1) +#define C_0286D8_PROVIDE_Z_TO_SPI 0xFFFFFFFE +#define R_0286DC_SPI_FOG_CNTL 0x0286DC +#define S_0286DC_PASS_FOG_THROUGH_PS(x) (((x) & 0x1) << 0) +#define G_0286DC_PASS_FOG_THROUGH_PS(x) (((x) >> 0) & 0x1) +#define C_0286DC_PASS_FOG_THROUGH_PS 0xFFFFFFFE +#define S_0286DC_PIXEL_FOG_FUNC(x) (((x) & 0x3) << 1) +#define G_0286DC_PIXEL_FOG_FUNC(x) (((x) >> 1) & 0x3) +#define C_0286DC_PIXEL_FOG_FUNC 0xFFFFFFF9 +#define S_0286DC_PIXEL_FOG_SRC_SEL(x) (((x) & 0x1) << 3) +#define G_0286DC_PIXEL_FOG_SRC_SEL(x) (((x) >> 3) & 0x1) +#define C_0286DC_PIXEL_FOG_SRC_SEL 0xFFFFFFF7 +#define S_0286DC_VS_FOG_CLAMP_DISABLE(x) (((x) & 0x1) << 4) +#define G_0286DC_VS_FOG_CLAMP_DISABLE(x) (((x) >> 4) & 0x1) +#define C_0286DC_VS_FOG_CLAMP_DISABLE 0xFFFFFFEF +#define R_0286E0_SPI_FOG_FUNC_SCALE 0x0286E0 +#define S_0286E0_VALUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0286E0_VALUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0286E0_VALUE 0x00000000 +#define R_0286E4_SPI_FOG_FUNC_BIAS 0x0286E4 +#define S_0286E4_VALUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_0286E4_VALUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_0286E4_VALUE 0x00000000 +#define R_0287A0_CB_SHADER_CONTROL 0x0287A0 +#define S_0287A0_RT0_ENABLE(x) (((x) & 0x1) << 0) +#define G_0287A0_RT0_ENABLE(x) (((x) >> 0) & 0x1) +#define C_0287A0_RT0_ENABLE 0xFFFFFFFE +#define S_0287A0_RT1_ENABLE(x) (((x) & 0x1) << 1) +#define G_0287A0_RT1_ENABLE(x) (((x) >> 1) & 0x1) +#define C_0287A0_RT1_ENABLE 0xFFFFFFFD +#define S_0287A0_RT2_ENABLE(x) (((x) & 0x1) << 2) +#define G_0287A0_RT2_ENABLE(x) (((x) >> 2) & 0x1) +#define C_0287A0_RT2_ENABLE 0xFFFFFFFB +#define S_0287A0_RT3_ENABLE(x) (((x) & 0x1) << 3) +#define G_0287A0_RT3_ENABLE(x) (((x) >> 3) & 0x1) +#define C_0287A0_RT3_ENABLE 0xFFFFFFF7 +#define S_0287A0_RT4_ENABLE(x) (((x) & 0x1) << 4) +#define G_0287A0_RT4_ENABLE(x) (((x) >> 4) & 0x1) +#define C_0287A0_RT4_ENABLE 0xFFFFFFEF +#define S_0287A0_RT5_ENABLE(x) (((x) & 0x1) << 5) +#define G_0287A0_RT5_ENABLE(x) (((x) >> 5) & 0x1) +#define C_0287A0_RT5_ENABLE 0xFFFFFFDF +#define S_0287A0_RT6_ENABLE(x) (((x) & 0x1) << 6) +#define G_0287A0_RT6_ENABLE(x) (((x) >> 6) & 0x1) +#define C_0287A0_RT6_ENABLE 0xFFFFFFBF +#define S_0287A0_RT7_ENABLE(x) (((x) & 0x1) << 7) +#define G_0287A0_RT7_ENABLE(x) (((x) >> 7) & 0x1) +#define C_0287A0_RT7_ENABLE 0xFFFFFF7F +#define R_028894_SQ_PGM_START_FS 0x028894 +#define S_028894_PGM_START(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028894_PGM_START(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028894_PGM_START 0x00000000 +#define R_0288A4_SQ_PGM_RESOURCES_FS 0x0288A4 +#define S_0288A4_NUM_GPRS(x) (((x) & 0xFF) << 0) +#define G_0288A4_NUM_GPRS(x) (((x) >> 0) & 0xFF) +#define C_0288A4_NUM_GPRS 0xFFFFFF00 +#define S_0288A4_STACK_SIZE(x) (((x) & 0xFF) << 8) +#define G_0288A4_STACK_SIZE(x) (((x) >> 8) & 0xFF) +#define C_0288A4_STACK_SIZE 0xFFFF00FF +#define S_0288A4_DX10_CLAMP(x) (((x) & 0x1) << 21) +#define G_0288A4_DX10_CLAMP(x) (((x) >> 21) & 0x1) +#define C_0288A4_DX10_CLAMP 0xFFDFFFFF +#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 +#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288A8_ITEMSIZE 0xFFFF8000 +#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC +#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288AC_ITEMSIZE 0xFFFF8000 +#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 +#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288B0_ITEMSIZE 0xFFFF8000 +#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 +#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288B4_ITEMSIZE 0xFFFF8000 +#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 +#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288B8_ITEMSIZE 0xFFFF8000 +#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC +#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288BC_ITEMSIZE 0xFFFF8000 +#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 +#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288C0_ITEMSIZE 0xFFFF8000 +#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 +#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288C4_ITEMSIZE 0xFFFF8000 +#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 +#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) +#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) +#define C_0288C8_ITEMSIZE 0xFFFF8000 +#define R_0288DC_SQ_PGM_CF_OFFSET_FS 0x0288DC +#define S_0288DC_PGM_CF_OFFSET(x) (((x) & 0xFFFFF) << 0) +#define G_0288DC_PGM_CF_OFFSET(x) (((x) >> 0) & 0xFFFFF) +#define C_0288DC_PGM_CF_OFFSET 0xFFF00000 +#define R_028A10_VGT_OUTPUT_PATH_CNTL 0x028A10 +#define S_028A10_PATH_SELECT(x) (((x) & 0x3) << 0) +#define G_028A10_PATH_SELECT(x) (((x) >> 0) & 0x3) +#define C_028A10_PATH_SELECT 0xFFFFFFFC +#define R_028A14_VGT_HOS_CNTL 0x028A14 +#define S_028A14_TESS_MODE(x) (((x) & 0x3) << 0) +#define G_028A14_TESS_MODE(x) (((x) >> 0) & 0x3) +#define C_028A14_TESS_MODE 0xFFFFFFFC +#define R_028A18_VGT_HOS_MAX_TESS_LEVEL 0x028A18 +#define S_028A18_MAX_TESS(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028A18_MAX_TESS(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028A18_MAX_TESS 0x00000000 +#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL 0x028A1C +#define S_028A1C_MIN_TESS(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028A1C_MIN_TESS(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028A1C_MIN_TESS 0x00000000 +#define R_028A20_VGT_HOS_REUSE_DEPTH 0x028A20 +#define S_028A20_REUSE_DEPTH(x) (((x) & 0xFF) << 0) +#define G_028A20_REUSE_DEPTH(x) (((x) >> 0) & 0xFF) +#define C_028A20_REUSE_DEPTH 0xFFFFFF00 +#define R_028A24_VGT_GROUP_PRIM_TYPE 0x028A24 +#define S_028A24_PRIM_TYPE(x) (((x) & 0x1F) << 0) +#define G_028A24_PRIM_TYPE(x) (((x) >> 0) & 0x1F) +#define C_028A24_PRIM_TYPE 0xFFFFFFE0 +#define S_028A24_RETAIN_ORDER(x) (((x) & 0x1) << 14) +#define G_028A24_RETAIN_ORDER(x) (((x) >> 14) & 0x1) +#define C_028A24_RETAIN_ORDER 0xFFFFBFFF +#define S_028A24_RETAIN_QUADS(x) (((x) & 0x1) << 15) +#define G_028A24_RETAIN_QUADS(x) (((x) >> 15) & 0x1) +#define C_028A24_RETAIN_QUADS 0xFFFF7FFF +#define S_028A24_PRIM_ORDER(x) (((x) & 0x7) << 16) +#define G_028A24_PRIM_ORDER(x) (((x) >> 16) & 0x7) +#define C_028A24_PRIM_ORDER 0xFFF8FFFF +#define R_028A28_VGT_GROUP_FIRST_DECR 0x028A28 +#define S_028A28_FIRST_DECR(x) (((x) & 0xF) << 0) +#define G_028A28_FIRST_DECR(x) (((x) >> 0) & 0xF) +#define C_028A28_FIRST_DECR 0xFFFFFFF0 +#define R_028A2C_VGT_GROUP_DECR 0x028A2C +#define S_028A2C_DECR(x) (((x) & 0xF) << 0) +#define G_028A2C_DECR(x) (((x) >> 0) & 0xF) +#define C_028A2C_DECR 0xFFFFFFF0 +#define R_028A30_VGT_GROUP_VECT_0_CNTL 0x028A30 +#define S_028A30_COMP_X_EN(x) (((x) & 0x1) << 0) +#define G_028A30_COMP_X_EN(x) (((x) >> 0) & 0x1) +#define C_028A30_COMP_X_EN 0xFFFFFFFE +#define S_028A30_COMP_Y_EN(x) (((x) & 0x1) << 1) +#define G_028A30_COMP_Y_EN(x) (((x) >> 1) & 0x1) +#define C_028A30_COMP_Y_EN 0xFFFFFFFD +#define S_028A30_COMP_Z_EN(x) (((x) & 0x1) << 2) +#define G_028A30_COMP_Z_EN(x) (((x) >> 2) & 0x1) +#define C_028A30_COMP_Z_EN 0xFFFFFFFB +#define S_028A30_COMP_W_EN(x) (((x) & 0x1) << 3) +#define G_028A30_COMP_W_EN(x) (((x) >> 3) & 0x1) +#define C_028A30_COMP_W_EN 0xFFFFFFF7 +#define S_028A30_STRIDE(x) (((x) & 0xFF) << 8) +#define G_028A30_STRIDE(x) (((x) >> 8) & 0xFF) +#define C_028A30_STRIDE 0xFFFF00FF +#define S_028A30_SHIFT(x) (((x) & 0xFF) << 16) +#define G_028A30_SHIFT(x) (((x) >> 16) & 0xFF) +#define C_028A30_SHIFT 0xFF00FFFF +#define R_028A34_VGT_GROUP_VECT_1_CNTL 0x028A34 +#define S_028A34_COMP_X_EN(x) (((x) & 0x1) << 0) +#define G_028A34_COMP_X_EN(x) (((x) >> 0) & 0x1) +#define C_028A34_COMP_X_EN 0xFFFFFFFE +#define S_028A34_COMP_Y_EN(x) (((x) & 0x1) << 1) +#define G_028A34_COMP_Y_EN(x) (((x) >> 1) & 0x1) +#define C_028A34_COMP_Y_EN 0xFFFFFFFD +#define S_028A34_COMP_Z_EN(x) (((x) & 0x1) << 2) +#define G_028A34_COMP_Z_EN(x) (((x) >> 2) & 0x1) +#define C_028A34_COMP_Z_EN 0xFFFFFFFB +#define S_028A34_COMP_W_EN(x) (((x) & 0x1) << 3) +#define G_028A34_COMP_W_EN(x) (((x) >> 3) & 0x1) +#define C_028A34_COMP_W_EN 0xFFFFFFF7 +#define S_028A34_STRIDE(x) (((x) & 0xFF) << 8) +#define G_028A34_STRIDE(x) (((x) >> 8) & 0xFF) +#define C_028A34_STRIDE 0xFFFF00FF +#define S_028A34_SHIFT(x) (((x) & 0xFF) << 16) +#define G_028A34_SHIFT(x) (((x) >> 16) & 0xFF) +#define C_028A34_SHIFT 0xFF00FFFF +#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL 0x028A38 +#define S_028A38_X_CONV(x) (((x) & 0xF) << 0) +#define G_028A38_X_CONV(x) (((x) >> 0) & 0xF) +#define C_028A38_X_CONV 0xFFFFFFF0 +#define S_028A38_X_OFFSET(x) (((x) & 0xF) << 4) +#define G_028A38_X_OFFSET(x) (((x) >> 4) & 0xF) +#define C_028A38_X_OFFSET 0xFFFFFF0F +#define S_028A38_Y_CONV(x) (((x) & 0xF) << 8) +#define G_028A38_Y_CONV(x) (((x) >> 8) & 0xF) +#define C_028A38_Y_CONV 0xFFFFF0FF +#define S_028A38_Y_OFFSET(x) (((x) & 0xF) << 12) +#define G_028A38_Y_OFFSET(x) (((x) >> 12) & 0xF) +#define C_028A38_Y_OFFSET 0xFFFF0FFF +#define S_028A38_Z_CONV(x) (((x) & 0xF) << 16) +#define G_028A38_Z_CONV(x) (((x) >> 16) & 0xF) +#define C_028A38_Z_CONV 0xFFF0FFFF +#define S_028A38_Z_OFFSET(x) (((x) & 0xF) << 20) +#define G_028A38_Z_OFFSET(x) (((x) >> 20) & 0xF) +#define C_028A38_Z_OFFSET 0xFF0FFFFF +#define S_028A38_W_CONV(x) (((x) & 0xF) << 24) +#define G_028A38_W_CONV(x) (((x) >> 24) & 0xF) +#define C_028A38_W_CONV 0xF0FFFFFF +#define S_028A38_W_OFFSET(x) (((x) & 0xF) << 28) +#define G_028A38_W_OFFSET(x) (((x) >> 28) & 0xF) +#define C_028A38_W_OFFSET 0x0FFFFFFF +#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL 0x028A3C +#define S_028A3C_X_CONV(x) (((x) & 0xF) << 0) +#define G_028A3C_X_CONV(x) (((x) >> 0) & 0xF) +#define C_028A3C_X_CONV 0xFFFFFFF0 +#define S_028A3C_X_OFFSET(x) (((x) & 0xF) << 4) +#define G_028A3C_X_OFFSET(x) (((x) >> 4) & 0xF) +#define C_028A3C_X_OFFSET 0xFFFFFF0F +#define S_028A3C_Y_CONV(x) (((x) & 0xF) << 8) +#define G_028A3C_Y_CONV(x) (((x) >> 8) & 0xF) +#define C_028A3C_Y_CONV 0xFFFFF0FF +#define S_028A3C_Y_OFFSET(x) (((x) & 0xF) << 12) +#define G_028A3C_Y_OFFSET(x) (((x) >> 12) & 0xF) +#define C_028A3C_Y_OFFSET 0xFFFF0FFF +#define S_028A3C_Z_CONV(x) (((x) & 0xF) << 16) +#define G_028A3C_Z_CONV(x) (((x) >> 16) & 0xF) +#define C_028A3C_Z_CONV 0xFFF0FFFF +#define S_028A3C_Z_OFFSET(x) (((x) & 0xF) << 20) +#define G_028A3C_Z_OFFSET(x) (((x) >> 20) & 0xF) +#define C_028A3C_Z_OFFSET 0xFF0FFFFF +#define S_028A3C_W_CONV(x) (((x) & 0xF) << 24) +#define G_028A3C_W_CONV(x) (((x) >> 24) & 0xF) +#define C_028A3C_W_CONV 0xF0FFFFFF +#define S_028A3C_W_OFFSET(x) (((x) & 0xF) << 28) +#define G_028A3C_W_OFFSET(x) (((x) >> 28) & 0xF) +#define C_028A3C_W_OFFSET 0x0FFFFFFF +#define R_028A40_VGT_GS_MODE 0x028A40 +#define S_028A40_MODE(x) (((x) & 0x3) << 0) +#define G_028A40_MODE(x) (((x) >> 0) & 0x3) +#define C_028A40_MODE 0xFFFFFFFC +#define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 2) +#define G_028A40_ES_PASSTHRU(x) (((x) >> 2) & 0x1) +#define C_028A40_ES_PASSTHRU 0xFFFFFFFB +#define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3) +#define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3) +#define C_028A40_CUT_MODE 0xFFFFFFE7 +#define R_028A4C_PA_SC_MODE_CNTL 0x028A4C +#define S_028A4C_MSAA_ENABLE(x) (((x) & 0x1) << 0) +#define G_028A4C_MSAA_ENABLE(x) (((x) >> 0) & 0x1) +#define C_028A4C_MSAA_ENABLE 0xFFFFFFFE +#define S_028A4C_CLIPRECT_ENABLE(x) (((x) & 0x1) << 1) +#define G_028A4C_CLIPRECT_ENABLE(x) (((x) >> 1) & 0x1) +#define C_028A4C_CLIPRECT_ENABLE 0xFFFFFFFD +#define S_028A4C_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 2) +#define G_028A4C_LINE_STIPPLE_ENABLE(x) (((x) >> 2) & 0x1) +#define C_028A4C_LINE_STIPPLE_ENABLE 0xFFFFFFFB +#define S_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x) (((x) & 0x1) << 3) +#define G_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x) (((x) >> 3) & 0x1) +#define C_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB 0xFFFFFFF7 +#define S_028A4C_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 4) +#define G_028A4C_WALK_ORDER_ENABLE(x) (((x) >> 4) & 0x1) +#define C_028A4C_WALK_ORDER_ENABLE 0xFFFFFFEF +#define S_028A4C_HALVE_DETAIL_SAMPLE_PERF(x) (((x) & 0x1) << 5) +#define G_028A4C_HALVE_DETAIL_SAMPLE_PERF(x) (((x) >> 5) & 0x1) +#define C_028A4C_HALVE_DETAIL_SAMPLE_PERF 0xFFFFFFDF +#define S_028A4C_WALK_SIZE(x) (((x) & 0x1) << 6) +#define G_028A4C_WALK_SIZE(x) (((x) >> 6) & 0x1) +#define C_028A4C_WALK_SIZE 0xFFFFFFBF +#define S_028A4C_WALK_ALIGNMENT(x) (((x) & 0x1) << 7) +#define G_028A4C_WALK_ALIGNMENT(x) (((x) >> 7) & 0x1) +#define C_028A4C_WALK_ALIGNMENT 0xFFFFFF7F +#define S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) & 0x1) << 8) +#define G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) >> 8) & 0x1) +#define C_028A4C_WALK_ALIGN8_PRIM_FITS_ST 0xFFFFFEFF +#define S_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) & 0x1) << 9) +#define G_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) >> 9) & 0x1) +#define C_028A4C_TILE_COVER_NO_SCISSOR 0xFFFFFDFF +#define S_028A4C_KILL_PIX_POST_HI_Z(x) (((x) & 0x1) << 10) +#define G_028A4C_KILL_PIX_POST_HI_Z(x) (((x) >> 10) & 0x1) +#define C_028A4C_KILL_PIX_POST_HI_Z 0xFFFFFBFF +#define S_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) & 0x1) << 11) +#define G_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) >> 11) & 0x1) +#define C_028A4C_KILL_PIX_POST_DETAIL_MASK 0xFFFFF7FF +#define S_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x) (((x) & 0x1) << 12) +#define G_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x) (((x) >> 12) & 0x1) +#define C_028A4C_MULTI_CHIP_SUPERTILE_ENABLE 0xFFFFEFFF +#define S_028A4C_TILE_COVER_DISABLE(x) (((x) & 0x1) << 13) +#define G_028A4C_TILE_COVER_DISABLE(x) (((x) >> 13) & 0x1) +#define C_028A4C_TILE_COVER_DISABLE 0xFFFFDFFF +#define S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) & 0x1) << 14) +#define G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) >> 14) & 0x1) +#define C_028A4C_FORCE_EOV_CNTDWN_ENABLE 0xFFFFBFFF +#define S_028A4C_FORCE_EOV_TILE_ENABLE(x) (((x) & 0x1) << 15) +#define G_028A4C_FORCE_EOV_TILE_ENABLE(x) (((x) >> 15) & 0x1) +#define C_028A4C_FORCE_EOV_TILE_ENABLE 0xFFFF7FFF +#define S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) & 0x1) << 16) +#define G_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) >> 16) & 0x1) +#define C_028A4C_FORCE_EOV_REZ_ENABLE 0xFFFEFFFF +#define S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 17) +#define G_028A4C_PS_ITER_SAMPLE(x) (((x) >> 17) & 0x1) +#define C_028A4C_PS_ITER_SAMPLE 0xFFFDFFFF +#define R_028A84_VGT_PRIMITIVEID_EN 0x028A84 +#define S_028A84_PRIMITIVEID_EN(x) (((x) & 0x1) << 0) +#define G_028A84_PRIMITIVEID_EN(x) (((x) >> 0) & 0x1) +#define C_028A84_PRIMITIVEID_EN 0xFFFFFFFE +#define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN 0x028A94 +#define S_028A94_RESET_EN(x) (((x) & 0x1) << 0) +#define G_028A94_RESET_EN(x) (((x) >> 0) & 0x1) +#define C_028A94_RESET_EN 0xFFFFFFFE +#define R_028AA0_VGT_INSTANCE_STEP_RATE_0 0x028AA0 +#define S_028AA0_STEP_RATE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028AA0_STEP_RATE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028AA0_STEP_RATE 0x00000000 +#define R_028AA4_VGT_INSTANCE_STEP_RATE_1 0x028AA4 +#define S_028AA4_STEP_RATE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028AA4_STEP_RATE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028AA4_STEP_RATE 0x00000000 +#define R_028AB0_VGT_STRMOUT_EN 0x028AB0 +#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) +#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) +#define C_028AB0_STREAMOUT 0xFFFFFFFE +#define R_028AB4_VGT_REUSE_OFF 0x028AB4 +#define S_028AB4_REUSE_OFF(x) (((x) & 0x1) << 0) +#define G_028AB4_REUSE_OFF(x) (((x) >> 0) & 0x1) +#define C_028AB4_REUSE_OFF 0xFFFFFFFE +#define R_028AB8_VGT_VTX_CNT_EN 0x028AB8 +#define S_028AB8_VTX_CNT_EN(x) (((x) & 0x1) << 0) +#define G_028AB8_VTX_CNT_EN(x) (((x) >> 0) & 0x1) +#define C_028AB8_VTX_CNT_EN 0xFFFFFFFE +#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 +#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) +#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) +#define C_028B20_BUFFER_0_EN 0xFFFFFFFE +#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) +#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) +#define C_028B20_BUFFER_1_EN 0xFFFFFFFD +#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) +#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) +#define C_028B20_BUFFER_2_EN 0xFFFFFFFB +#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) +#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) +#define C_028B20_BUFFER_3_EN 0xFFFFFFF7 +#define R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 0x028C20 +#define S_028C20_S4_X(x) (((x) & 0xF) << 0) +#define G_028C20_S4_X(x) (((x) >> 0) & 0xF) +#define C_028C20_S4_X 0xFFFFFFF0 +#define S_028C20_S4_Y(x) (((x) & 0xF) << 4) +#define G_028C20_S4_Y(x) (((x) >> 4) & 0xF) +#define C_028C20_S4_Y 0xFFFFFF0F +#define S_028C20_S5_X(x) (((x) & 0xF) << 8) +#define G_028C20_S5_X(x) (((x) >> 8) & 0xF) +#define C_028C20_S5_X 0xFFFFF0FF +#define S_028C20_S5_Y(x) (((x) & 0xF) << 12) +#define G_028C20_S5_Y(x) (((x) >> 12) & 0xF) +#define C_028C20_S5_Y 0xFFFF0FFF +#define S_028C20_S6_X(x) (((x) & 0xF) << 16) +#define G_028C20_S6_X(x) (((x) >> 16) & 0xF) +#define C_028C20_S6_X 0xFFF0FFFF +#define S_028C20_S6_Y(x) (((x) & 0xF) << 20) +#define G_028C20_S6_Y(x) (((x) >> 20) & 0xF) +#define C_028C20_S6_Y 0xFF0FFFFF +#define S_028C20_S7_X(x) (((x) & 0xF) << 24) +#define G_028C20_S7_X(x) (((x) >> 24) & 0xF) +#define C_028C20_S7_X 0xF0FFFFFF +#define S_028C20_S7_Y(x) (((x) & 0xF) << 28) +#define G_028C20_S7_Y(x) (((x) >> 28) & 0xF) +#define C_028C20_S7_Y 0x0FFFFFFF +#define R_028C30_CB_CLRCMP_CONTROL 0x028C30 +#define S_028C30_CLRCMP_FCN_SRC(x) (((x) & 0x7) << 0) +#define G_028C30_CLRCMP_FCN_SRC(x) (((x) >> 0) & 0x7) +#define C_028C30_CLRCMP_FCN_SRC 0xFFFFFFF8 +#define S_028C30_CLRCMP_FCN_DST(x) (((x) & 0x7) << 8) +#define G_028C30_CLRCMP_FCN_DST(x) (((x) >> 8) & 0x7) +#define C_028C30_CLRCMP_FCN_DST 0xFFFFF8FF +#define S_028C30_CLRCMP_FCN_SEL(x) (((x) & 0x3) << 24) +#define G_028C30_CLRCMP_FCN_SEL(x) (((x) >> 24) & 0x3) +#define C_028C30_CLRCMP_FCN_SEL 0xFCFFFFFF +#define R_028C34_CB_CLRCMP_SRC 0x028C34 +#define S_028C34_CLRCMP_SRC(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028C34_CLRCMP_SRC(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028C34_CLRCMP_SRC 0x00000000 +#define R_028C38_CB_CLRCMP_DST 0x028C38 +#define S_028C38_CLRCMP_DST(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028C38_CLRCMP_DST(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028C38_CLRCMP_DST 0x00000000 +#define R_028C3C_CB_CLRCMP_MSK 0x028C3C +#define S_028C3C_CLRCMP_MSK(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028C3C_CLRCMP_MSK(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028C3C_CLRCMP_MSK 0x00000000 +#define R_0085F0_CP_COHER_CNTL 0x0085F0 +#define S_0085F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0) +#define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1) +#define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE +#define S_0085F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1) +#define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1) +#define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD +#define S_0085F0_SO0_DEST_BASE_ENA(x) (((x) & 0x1) << 2) +#define G_0085F0_SO0_DEST_BASE_ENA(x) (((x) >> 2) & 0x1) +#define C_0085F0_SO0_DEST_BASE_ENA 0xFFFFFFFB +#define S_0085F0_SO1_DEST_BASE_ENA(x) (((x) & 0x1) << 3) +#define G_0085F0_SO1_DEST_BASE_ENA(x) (((x) >> 3) & 0x1) +#define C_0085F0_SO1_DEST_BASE_ENA 0xFFFFFFF7 +#define S_0085F0_SO2_DEST_BASE_ENA(x) (((x) & 0x1) << 4) +#define G_0085F0_SO2_DEST_BASE_ENA(x) (((x) >> 4) & 0x1) +#define C_0085F0_SO2_DEST_BASE_ENA 0xFFFFFFEF +#define S_0085F0_SO3_DEST_BASE_ENA(x) (((x) & 0x1) << 5) +#define G_0085F0_SO3_DEST_BASE_ENA(x) (((x) >> 5) & 0x1) +#define C_0085F0_SO3_DEST_BASE_ENA 0xFFFFFFDF +#define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6) +#define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1) +#define C_0085F0_CB0_DEST_BASE_ENA 0xFFFFFFBF +#define S_0085F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7) +#define G_0085F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1) +#define C_0085F0_CB1_DEST_BASE_ENA 0xFFFFFF7F +#define S_0085F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8) +#define G_0085F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1) +#define C_0085F0_CB2_DEST_BASE_ENA 0xFFFFFEFF +#define S_0085F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9) +#define G_0085F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1) +#define C_0085F0_CB3_DEST_BASE_ENA 0xFFFFFDFF +#define S_0085F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10) +#define G_0085F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1) +#define C_0085F0_CB4_DEST_BASE_ENA 0xFFFFFBFF +#define S_0085F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11) +#define G_0085F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1) +#define C_0085F0_CB5_DEST_BASE_ENA 0xFFFFF7FF +#define S_0085F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12) +#define G_0085F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1) +#define C_0085F0_CB6_DEST_BASE_ENA 0xFFFFEFFF +#define S_0085F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13) +#define G_0085F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1) +#define C_0085F0_CB7_DEST_BASE_ENA 0xFFFFDFFF +#define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14) +#define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1) +#define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF +#define S_0085F0_CR_DEST_BASE_ENA(x) (((x) & 0x1) << 15) +#define G_0085F0_CR_DEST_BASE_ENA(x) (((x) >> 15) & 0x1) +#define C_0085F0_CR_DEST_BASE_ENA 0xFFFF7FFF +#define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23) +#define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1) +#define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF +#define S_0085F0_VC_ACTION_ENA(x) (((x) & 0x1) << 24) +#define G_0085F0_VC_ACTION_ENA(x) (((x) >> 24) & 0x1) +#define C_0085F0_VC_ACTION_ENA 0xFEFFFFFF +#define S_0085F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25) +#define G_0085F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1) +#define C_0085F0_CB_ACTION_ENA 0xFDFFFFFF +#define S_0085F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26) +#define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1) +#define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF +#define S_0085F0_SH_ACTION_ENA(x) (((x) & 0x1) << 27) +#define G_0085F0_SH_ACTION_ENA(x) (((x) >> 27) & 0x1) +#define C_0085F0_SH_ACTION_ENA 0xF7FFFFFF +#define S_0085F0_SMX_ACTION_ENA(x) (((x) & 0x1) << 28) +#define G_0085F0_SMX_ACTION_ENA(x) (((x) >> 28) & 0x1) +#define C_0085F0_SMX_ACTION_ENA 0xEFFFFFFF +#define S_0085F0_CR0_ACTION_ENA(x) (((x) & 0x1) << 29) +#define G_0085F0_CR0_ACTION_ENA(x) (((x) >> 29) & 0x1) +#define C_0085F0_CR0_ACTION_ENA 0xDFFFFFFF +#define S_0085F0_CR1_ACTION_ENA(x) (((x) & 0x1) << 30) +#define G_0085F0_CR1_ACTION_ENA(x) (((x) >> 30) & 0x1) +#define C_0085F0_CR1_ACTION_ENA 0xBFFFFFFF +#define S_0085F0_CR2_ACTION_ENA(x) (((x) & 0x1) << 31) +#define G_0085F0_CR2_ACTION_ENA(x) (((x) >> 31) & 0x1) +#define C_0085F0_CR2_ACTION_ENA 0x7FFFFFFF + + +#define R_02812C_CB_CLEAR_ALPHA 0x02812C +#define S_02812C_CLEAR_ALPHA(x) (((x) & 0xFFFFFFFF) << 0) +#define G_02812C_CLEAR_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_02812C_CLEAR_ALPHA 0x00000000 +#define R_028128_CB_CLEAR_BLUE 0x028128 +#define S_028128_CLEAR_BLUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028128_CLEAR_BLUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028128_CLEAR_BLUE 0x00000000 +#define R_028124_CB_CLEAR_GREEN 0x028124 +#define S_028124_CLEAR_GREEN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028124_CLEAR_GREEN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028124_CLEAR_GREEN 0x00000000 +#define R_028120_CB_CLEAR_RED 0x028120 +#define S_028120_CLEAR_RED(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028120_CLEAR_RED(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028120_CLEAR_RED 0x00000000 +#define R_02842C_CB_FOG_BLUE 0x02842C +#define S_02842C_FOG_BLUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_02842C_FOG_BLUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_02842C_FOG_BLUE 0x00000000 +#define R_028428_CB_FOG_GREEN 0x028428 +#define S_028428_FOG_GREEN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028428_FOG_GREEN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028428_FOG_GREEN 0x00000000 +#define R_028424_CB_FOG_RED 0x028424 +#define S_028424_FOG_RED(x) (((x) & 0xFFFFFFFF) << 0) +#define G_028424_FOG_RED(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_028424_FOG_RED 0x00000000 +#define R_03C000_SQ_TEX_SAMPLER_WORD0_0 0x03C000 +#define S_03C000_CLAMP_X(x) (((x) & 0x7) << 0) +#define G_03C000_CLAMP_X(x) (((x) >> 0) & 0x7) +#define C_03C000_CLAMP_X 0xFFFFFFF8 +#define S_03C000_CLAMP_Y(x) (((x) & 0x7) << 3) +#define G_03C000_CLAMP_Y(x) (((x) >> 3) & 0x7) +#define C_03C000_CLAMP_Y 0xFFFFFFC7 +#define S_03C000_CLAMP_Z(x) (((x) & 0x7) << 6) +#define G_03C000_CLAMP_Z(x) (((x) >> 6) & 0x7) +#define C_03C000_CLAMP_Z 0xFFFFFE3F +#define S_03C000_XY_MAG_FILTER(x) (((x) & 0x7) << 9) +#define G_03C000_XY_MAG_FILTER(x) (((x) >> 9) & 0x7) +#define C_03C000_XY_MAG_FILTER 0xFFFFF1FF +#define S_03C000_XY_MIN_FILTER(x) (((x) & 0x7) << 12) +#define G_03C000_XY_MIN_FILTER(x) (((x) >> 12) & 0x7) +#define C_03C000_XY_MIN_FILTER 0xFFFF8FFF +#define S_03C000_Z_FILTER(x) (((x) & 0x3) << 15) +#define G_03C000_Z_FILTER(x) (((x) >> 15) & 0x3) +#define C_03C000_Z_FILTER 0xFFFE7FFF +#define S_03C000_MIP_FILTER(x) (((x) & 0x3) << 17) +#define G_03C000_MIP_FILTER(x) (((x) >> 17) & 0x3) +#define C_03C000_MIP_FILTER 0xFFF9FFFF +#define S_03C000_BORDER_COLOR_TYPE(x) (((x) & 0x3) << 22) +#define G_03C000_BORDER_COLOR_TYPE(x) (((x) >> 22) & 0x3) +#define C_03C000_BORDER_COLOR_TYPE 0xFF3FFFFF +#define S_03C000_POINT_SAMPLING_CLAMP(x) (((x) & 0x1) << 24) +#define G_03C000_POINT_SAMPLING_CLAMP(x) (((x) >> 24) & 0x1) +#define C_03C000_POINT_SAMPLING_CLAMP 0xFEFFFFFF +#define S_03C000_TEX_ARRAY_OVERRIDE(x) (((x) & 0x1) << 25) +#define G_03C000_TEX_ARRAY_OVERRIDE(x) (((x) >> 25) & 0x1) +#define C_03C000_TEX_ARRAY_OVERRIDE 0xFDFFFFFF +#define S_03C000_DEPTH_COMPARE_FUNCTION(x) (((x) & 0x7) << 26) +#define G_03C000_DEPTH_COMPARE_FUNCTION(x) (((x) >> 26) & 0x7) +#define C_03C000_DEPTH_COMPARE_FUNCTION 0xE3FFFFFF +#define S_03C000_CHROMA_KEY(x) (((x) & 0x3) << 29) +#define G_03C000_CHROMA_KEY(x) (((x) >> 29) & 0x3) +#define C_03C000_CHROMA_KEY 0x9FFFFFFF +#define S_03C000_LOD_USES_MINOR_AXIS(x) (((x) & 0x1) << 31) +#define G_03C000_LOD_USES_MINOR_AXIS(x) (((x) >> 31) & 0x1) +#define C_03C000_LOD_USES_MINOR_AXIS 0x7FFFFFFF +#define R_03C004_SQ_TEX_SAMPLER_WORD1_0 0x03C004 +#define S_03C004_MIN_LOD(x) (((x) & 0x3FF) << 0) +#define G_03C004_MIN_LOD(x) (((x) >> 0) & 0x3FF) +#define C_03C004_MIN_LOD 0xFFFFFC00 +#define S_03C004_MAX_LOD(x) (((x) & 0x3FF) << 10) +#define G_03C004_MAX_LOD(x) (((x) >> 10) & 0x3FF) +#define C_03C004_MAX_LOD 0xFFF003FF +#define S_03C004_LOD_BIAS(x) (((x) & 0xFFF) << 20) +#define G_03C004_LOD_BIAS(x) (((x) >> 20) & 0xFFF) +#define C_03C004_LOD_BIAS 0x000FFFFF +#define R_03C008_SQ_TEX_SAMPLER_WORD2_0 0x03C008 +#define S_03C008_LOD_BIAS_SEC(x) (((x) & 0xFFF) << 0) +#define G_03C008_LOD_BIAS_SEC(x) (((x) >> 0) & 0xFFF) +#define C_03C008_LOD_BIAS_SEC 0xFFFFF000 +#define S_03C008_MC_COORD_TRUNCATE(x) (((x) & 0x1) << 12) +#define G_03C008_MC_COORD_TRUNCATE(x) (((x) >> 12) & 0x1) +#define C_03C008_MC_COORD_TRUNCATE 0xFFFFEFFF +#define S_03C008_FORCE_DEGAMMA(x) (((x) & 0x1) << 13) +#define G_03C008_FORCE_DEGAMMA(x) (((x) >> 13) & 0x1) +#define C_03C008_FORCE_DEGAMMA 0xFFFFDFFF +#define S_03C008_HIGH_PRECISION_FILTER(x) (((x) & 0x1) << 14) +#define G_03C008_HIGH_PRECISION_FILTER(x) (((x) >> 14) & 0x1) +#define C_03C008_HIGH_PRECISION_FILTER 0xFFFFBFFF +#define S_03C008_PERF_MIP(x) (((x) & 0x7) << 15) +#define G_03C008_PERF_MIP(x) (((x) >> 15) & 0x7) +#define C_03C008_PERF_MIP 0xFFFC7FFF +#define S_03C008_PERF_Z(x) (((x) & 0x3) << 18) +#define G_03C008_PERF_Z(x) (((x) >> 18) & 0x3) +#define C_03C008_PERF_Z 0xFFF3FFFF +#define S_03C008_FETCH_4(x) (((x) & 0x1) << 26) +#define G_03C008_FETCH_4(x) (((x) >> 26) & 0x1) +#define C_03C008_FETCH_4 0xFBFFFFFF +#define S_03C008_SAMPLE_IS_PCF(x) (((x) & 0x1) << 27) +#define G_03C008_SAMPLE_IS_PCF(x) (((x) >> 27) & 0x1) +#define C_03C008_SAMPLE_IS_PCF 0xF7FFFFFF +#define S_03C008_TYPE(x) (((x) & 0x1) << 31) +#define G_03C008_TYPE(x) (((x) >> 31) & 0x1) +#define C_03C008_TYPE 0x7FFFFFFF +#define R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA 0x00A40C +#define S_00A40C_BORDER_ALPHA(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A40C_BORDER_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A40C_BORDER_ALPHA 0x00000000 +#define R_00A408_TD_PS_SAMPLER0_BORDER_BLUE 0x00A408 +#define S_00A408_BORDER_BLUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A408_BORDER_BLUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A408_BORDER_BLUE 0x00000000 +#define R_00A404_TD_PS_SAMPLER0_BORDER_GREEN 0x00A404 +#define S_00A404_BORDER_GREEN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A404_BORDER_GREEN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A404_BORDER_GREEN 0x00000000 +#define R_00A400_TD_PS_SAMPLER0_BORDER_RED 0x00A400 +#define S_00A400_BORDER_RED(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A400_BORDER_RED(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A400_BORDER_RED 0x00000000 +#define R_00A60C_TD_VS_SAMPLER0_BORDER_ALPHA 0x00A60C +#define S_00A60C_BORDER_ALPHA(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A60C_BORDER_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A60C_BORDER_ALPHA 0x00000000 +#define R_00A608_TD_VS_SAMPLER0_BORDER_BLUE 0x00A608 +#define S_00A608_BORDER_BLUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A608_BORDER_BLUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A608_BORDER_BLUE 0x00000000 +#define R_00A604_TD_VS_SAMPLER0_BORDER_GREEN 0x00A604 +#define S_00A604_BORDER_GREEN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A604_BORDER_GREEN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A604_BORDER_GREEN 0x00000000 +#define R_00A600_TD_VS_SAMPLER0_BORDER_RED 0x00A600 +#define S_00A600_BORDER_RED(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A600_BORDER_RED(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A600_BORDER_RED 0x00000000 +#define R_00A80C_TD_GS_SAMPLER0_BORDER_ALPHA 0x00A80C +#define S_00A80C_BORDER_ALPHA(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A80C_BORDER_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A80C_BORDER_ALPHA 0x00000000 +#define R_00A808_TD_GS_SAMPLER0_BORDER_BLUE 0x00A808 +#define S_00A808_BORDER_BLUE(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A808_BORDER_BLUE(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A808_BORDER_BLUE 0x00000000 +#define R_00A804_TD_GS_SAMPLER0_BORDER_GREEN 0x00A804 +#define S_00A804_BORDER_GREEN(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A804_BORDER_GREEN(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A804_BORDER_GREEN 0x00000000 +#define R_00A800_TD_GS_SAMPLER0_BORDER_RED 0x00A800 +#define S_00A800_BORDER_RED(x) (((x) & 0xFFFFFFFF) << 0) +#define G_00A800_BORDER_RED(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_00A800_BORDER_RED 0x00000000 +#define R_030000_SQ_ALU_CONSTANT0_0 0x030000 +#define S_030000_X(x) (((x) & 0xFFFFFFFF) << 0) +#define G_030000_X(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_030000_X 0x00000000 +#define R_030004_SQ_ALU_CONSTANT1_0 0x030004 +#define S_030004_Y(x) (((x) & 0xFFFFFFFF) << 0) +#define G_030004_Y(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_030004_Y 0x00000000 +#define R_030008_SQ_ALU_CONSTANT2_0 0x030008 +#define S_030008_Z(x) (((x) & 0xFFFFFFFF) << 0) +#define G_030008_Z(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_030008_Z 0x00000000 +#define R_03000C_SQ_ALU_CONSTANT3_0 0x03000C +#define S_03000C_W(x) (((x) & 0xFFFFFFFF) << 0) +#define G_03000C_W(x) (((x) >> 0) & 0xFFFFFFFF) +#define C_03000C_W 0x00000000 +#define R_0287E4_VGT_DMA_BASE_HI 0x0287E4 +#define R_0287E8_VGT_DMA_BASE 0x0287E8 +#define R_028E20_PA_CL_UCP0_X 0x028E20 +#define R_028E24_PA_CL_UCP0_Y 0x028E24 +#define R_028E28_PA_CL_UCP0_Z 0x028E28 +#define R_028E2C_PA_CL_UCP0_W 0x028E2C +#define R_028E30_PA_CL_UCP1_X 0x028E30 +#define R_028E34_PA_CL_UCP1_Y 0x028E34 +#define R_028E38_PA_CL_UCP1_Z 0x028E38 +#define R_028E3C_PA_CL_UCP1_W 0x028E3C +#define R_028E40_PA_CL_UCP2_X 0x028E40 +#define R_028E44_PA_CL_UCP2_Y 0x028E44 +#define R_028E48_PA_CL_UCP2_Z 0x028E48 +#define R_028E4C_PA_CL_UCP2_W 0x028E4C +#define R_028E50_PA_CL_UCP3_X 0x028E50 +#define R_028E54_PA_CL_UCP3_Y 0x028E54 +#define R_028E58_PA_CL_UCP3_Z 0x028E58 +#define R_028E5C_PA_CL_UCP3_W 0x028E5C +#define R_028E60_PA_CL_UCP4_X 0x028E60 +#define R_028E64_PA_CL_UCP4_Y 0x028E64 +#define R_028E68_PA_CL_UCP4_Z 0x028E68 +#define R_028E6C_PA_CL_UCP4_W 0x028E6C +#define R_028E70_PA_CL_UCP5_X 0x028E70 +#define R_028E74_PA_CL_UCP5_Y 0x028E74 +#define R_028E78_PA_CL_UCP5_Z 0x028E78 +#define R_028E7C_PA_CL_UCP5_W 0x028E7C +#define R_038000_RESOURCE0_WORD0 0x038000 +#define R_038004_RESOURCE0_WORD1 0x038004 +#define R_038008_RESOURCE0_WORD2 0x038008 +#define R_03800C_RESOURCE0_WORD3 0x03800C +#define R_038010_RESOURCE0_WORD4 0x038010 +#define R_038014_RESOURCE0_WORD5 0x038014 +#define R_038018_RESOURCE0_WORD6 0x038018 + +#define R_028140_ALU_CONST_BUFFER_SIZE_PS_0 0x00028140 +#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0 0x00028180 +#define R_028940_ALU_CONST_CACHE_PS_0 0x00028940 +#define R_028980_ALU_CONST_CACHE_VS_0 0x00028980 + +#define R_03CFF0_SQ_VTX_BASE_VTX_LOC 0x03CFF0 +#define R_03CFF4_SQ_VTX_START_INST_LOC 0x03CFF4 + +#endif diff --git a/src/gallium/winsys/r600/drm/radeon_bo.c b/src/gallium/winsys/r600/drm/radeon_bo.c new file mode 100644 index 00000000000..14a00161c8b --- /dev/null +++ b/src/gallium/winsys/r600/drm/radeon_bo.c @@ -0,0 +1,202 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#define _FILE_OFFSET_BITS 64 +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <sys/mman.h> +#include <errno.h> +#include "r600_priv.h" +#include "xf86drm.h" +#include "radeon_drm.h" + +static int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo) +{ + struct drm_radeon_gem_mmap args; + void *ptr; + int r; + + /* Zero out args to make valgrind happy */ + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + args.offset = 0; + args.size = (uint64_t)bo->size; + r = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_MMAP, + &args, sizeof(args)); + if (r) { + fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n", + bo, bo->handle, r); + return r; + } + ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, radeon->fd, args.addr_ptr); + if (ptr == MAP_FAILED) { + fprintf(stderr, "%s failed to map bo\n", __func__); + return -errno; + } + bo->data = ptr; + + bo->map_count++; + return 0; +} + +static void radeon_bo_fixed_unmap(struct radeon *radeon, struct radeon_bo *bo) +{ + munmap(bo->data, bo->size); + bo->data = NULL; +} + +struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, + unsigned size, unsigned alignment, void *ptr) +{ + struct radeon_bo *bo; + int r; + + bo = calloc(1, sizeof(*bo)); + if (bo == NULL) { + return NULL; + } + bo->size = size; + bo->handle = handle; + pipe_reference_init(&bo->reference, 1); + bo->alignment = alignment; + + if (handle) { + struct drm_gem_open open_arg; + + memset(&open_arg, 0, sizeof(open_arg)); + open_arg.name = handle; + r = drmIoctl(radeon->fd, DRM_IOCTL_GEM_OPEN, &open_arg); + if (r != 0) { + free(bo); + return NULL; + } + bo->handle = open_arg.handle; + bo->size = open_arg.size; + bo->shared = TRUE; + } else { + struct drm_radeon_gem_create args; + + args.size = size; + args.alignment = alignment; + args.initial_domain = RADEON_GEM_DOMAIN_CPU; + args.flags = 0; + args.handle = 0; + r = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_CREATE, + &args, sizeof(args)); + bo->handle = args.handle; + if (r) { + fprintf(stderr, "Failed to allocate :\n"); + fprintf(stderr, " size : %d bytes\n", size); + fprintf(stderr, " alignment : %d bytes\n", alignment); + free(bo); + return NULL; + } + } + if (radeon_bo_fixed_map(radeon, bo)) { + R600_ERR("failed to map bo\n"); + radeon_bo_reference(radeon, &bo, NULL); + return bo; + } + if (ptr) { + memcpy(bo->data, ptr, size); + } + LIST_INITHEAD(&bo->fencedlist); + return bo; +} + +static void radeon_bo_destroy(struct radeon *radeon, struct radeon_bo *bo) +{ + struct drm_gem_close args; + + LIST_DEL(&bo->fencedlist); + radeon_bo_fixed_unmap(radeon, bo); + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + drmIoctl(radeon->fd, DRM_IOCTL_GEM_CLOSE, &args); + memset(bo, 0, sizeof(struct radeon_bo)); + free(bo); +} + +void radeon_bo_reference(struct radeon *radeon, + struct radeon_bo **dst, + struct radeon_bo *src) +{ + struct radeon_bo *old = *dst; + if (pipe_reference(&(*dst)->reference, &src->reference)) { + radeon_bo_destroy(radeon, old); + } + *dst = src; +} + +int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo) +{ + struct drm_radeon_gem_wait_idle args; + int ret; + + if (!bo->fence && !bo->shared) + return 0; + + if (bo->fence <= *bo->ctx->cfence) { + LIST_DELINIT(&bo->fencedlist); + bo->fence = 0; + return 0; + } + + /* Zero out args to make valgrind happy */ + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + do { + ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_WAIT_IDLE, + &args, sizeof(args)); + } while (ret == -EBUSY); + return ret; +} + +int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain) +{ + struct drm_radeon_gem_busy args; + int ret; + + if (!bo->shared) { + if (!bo->fence) + return 0; + if (bo->fence <= *bo->ctx->cfence) { + LIST_DELINIT(&bo->fencedlist); + bo->fence = 0; + return 0; + } + } + + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + args.domain = 0; + + ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_BUSY, + &args, sizeof(args)); + + *domain = args.domain; + return ret; +} diff --git a/src/gallium/winsys/r600/drm/radeon_bo_pb.c b/src/gallium/winsys/r600/drm/radeon_bo_pb.c new file mode 100644 index 00000000000..a3452027f27 --- /dev/null +++ b/src/gallium/winsys/r600/drm/radeon_bo_pb.c @@ -0,0 +1,292 @@ +/* + * Copyright 2010 Dave Airlie + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Dave Airlie + */ +#include <util/u_inlines.h> +#include <util/u_memory.h> +#include <util/u_double_list.h> +#include <pipebuffer/pb_buffer.h> +#include <pipebuffer/pb_bufmgr.h> +#include "r600_priv.h" + +struct radeon_bo_pb { + struct pb_buffer b; + struct radeon_bo *bo; + + struct radeon_bo_pbmgr *mgr; + struct list_head maplist; +}; + +extern const struct pb_vtbl radeon_bo_pb_vtbl; + +static INLINE struct radeon_bo_pb *radeon_bo_pb(struct pb_buffer *buf) +{ + assert(buf); + assert(buf->vtbl == &radeon_bo_pb_vtbl); + return (struct radeon_bo_pb *)buf; +} + +struct radeon_bo_pbmgr { + struct pb_manager b; + struct radeon *radeon; + struct list_head buffer_map_list; +}; + +static INLINE struct radeon_bo_pbmgr *radeon_bo_pbmgr(struct pb_manager *mgr) +{ + assert(mgr); + return (struct radeon_bo_pbmgr *)mgr; +} + +static void radeon_bo_pb_destroy(struct pb_buffer *_buf) +{ + struct radeon_bo_pb *buf = radeon_bo_pb(_buf); + + LIST_DEL(&buf->maplist); + + if (buf->bo->data != NULL) { + radeon_bo_unmap(buf->mgr->radeon, buf->bo); + } + radeon_bo_reference(buf->mgr->radeon, &buf->bo, NULL); + FREE(buf); +} + +static void * +radeon_bo_pb_map_internal(struct pb_buffer *_buf, + unsigned flags, void *ctx) +{ + struct radeon_bo_pb *buf = radeon_bo_pb(_buf); + struct pipe_context *pctx = ctx; + + if (flags & PB_USAGE_UNSYNCHRONIZED) { + if (!buf->bo->data && radeon_bo_map(buf->mgr->radeon, buf->bo)) { + return NULL; + } + LIST_DELINIT(&buf->maplist); + return buf->bo->data; + } + + if (p_atomic_read(&buf->bo->reference.count) > 1) { + if (flags & PB_USAGE_DONTBLOCK) { + return NULL; + } + if (ctx) { + pctx->flush(pctx, 0, NULL); + } + } + + if (flags & PB_USAGE_DONTBLOCK) { + uint32_t domain; + if (radeon_bo_busy(buf->mgr->radeon, buf->bo, &domain)) + return NULL; + if (radeon_bo_map(buf->mgr->radeon, buf->bo)) { + return NULL; + } + goto out; + } + + if (buf->bo->data != NULL) { + if (radeon_bo_wait(buf->mgr->radeon, buf->bo)) { + return NULL; + } + } else { + if (radeon_bo_map(buf->mgr->radeon, buf->bo)) { + return NULL; + } + if (radeon_bo_wait(buf->mgr->radeon, buf->bo)) { + radeon_bo_unmap(buf->mgr->radeon, buf->bo); + return NULL; + } + } +out: + LIST_DELINIT(&buf->maplist); + return buf->bo->data; +} + +static void radeon_bo_pb_unmap_internal(struct pb_buffer *_buf) +{ + struct radeon_bo_pb *buf = radeon_bo_pb(_buf); + LIST_ADDTAIL(&buf->maplist, &buf->mgr->buffer_map_list); +} + +static void +radeon_bo_pb_get_base_buffer(struct pb_buffer *buf, + struct pb_buffer **base_buf, + unsigned *offset) +{ + *base_buf = buf; + *offset = 0; +} + +static enum pipe_error +radeon_bo_pb_validate(struct pb_buffer *_buf, + struct pb_validate *vl, + unsigned flags) +{ + /* Always pinned */ + return PIPE_OK; +} + +static void +radeon_bo_pb_fence(struct pb_buffer *buf, + struct pipe_fence_handle *fence) +{ +} + +const struct pb_vtbl radeon_bo_pb_vtbl = { + radeon_bo_pb_destroy, + radeon_bo_pb_map_internal, + radeon_bo_pb_unmap_internal, + radeon_bo_pb_validate, + radeon_bo_pb_fence, + radeon_bo_pb_get_base_buffer, +}; + +struct pb_buffer * +radeon_bo_pb_create_buffer_from_handle(struct pb_manager *_mgr, + uint32_t handle) +{ + struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr); + struct radeon *radeon = mgr->radeon; + struct radeon_bo_pb *bo; + struct radeon_bo *hw_bo; + + hw_bo = radeon_bo(radeon, handle, 0, 0, NULL); + if (hw_bo == NULL) + return NULL; + + bo = CALLOC_STRUCT(radeon_bo_pb); + if (!bo) { + radeon_bo_reference(radeon, &hw_bo, NULL); + return NULL; + } + + LIST_INITHEAD(&bo->maplist); + pipe_reference_init(&bo->b.base.reference, 1); + bo->b.base.alignment = 0; + bo->b.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ; + bo->b.base.size = hw_bo->size; + bo->b.vtbl = &radeon_bo_pb_vtbl; + bo->mgr = mgr; + + bo->bo = hw_bo; + + return &bo->b; +} + +static struct pb_buffer * +radeon_bo_pb_create_buffer(struct pb_manager *_mgr, + pb_size size, + const struct pb_desc *desc) +{ + struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr); + struct radeon *radeon = mgr->radeon; + struct radeon_bo_pb *bo; + + bo = CALLOC_STRUCT(radeon_bo_pb); + if (!bo) + goto error1; + + pipe_reference_init(&bo->b.base.reference, 1); + bo->b.base.alignment = desc->alignment; + bo->b.base.usage = desc->usage; + bo->b.base.size = size; + bo->b.vtbl = &radeon_bo_pb_vtbl; + bo->mgr = mgr; + + LIST_INITHEAD(&bo->maplist); + + bo->bo = radeon_bo(radeon, 0, size, + desc->alignment, NULL); + if (bo->bo == NULL) + goto error2; + return &bo->b; + +error2: + FREE(bo); +error1: + return NULL; +} + +static void +radeon_bo_pbmgr_flush(struct pb_manager *mgr) +{ + /* NOP */ +} + +static void +radeon_bo_pbmgr_destroy(struct pb_manager *_mgr) +{ + struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr); + FREE(mgr); +} + +struct pb_manager *radeon_bo_pbmgr_create(struct radeon *radeon) +{ + struct radeon_bo_pbmgr *mgr; + + mgr = CALLOC_STRUCT(radeon_bo_pbmgr); + if (!mgr) + return NULL; + + mgr->b.destroy = radeon_bo_pbmgr_destroy; + mgr->b.create_buffer = radeon_bo_pb_create_buffer; + mgr->b.flush = radeon_bo_pbmgr_flush; + + mgr->radeon = radeon; + LIST_INITHEAD(&mgr->buffer_map_list); + return &mgr->b; +} + +void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr) +{ + struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr); + struct radeon_bo_pb *rpb = NULL; + struct radeon_bo_pb *t_rpb; + + LIST_FOR_EACH_ENTRY_SAFE(rpb, t_rpb, &mgr->buffer_map_list, maplist) { + radeon_bo_unmap(mgr->radeon, rpb->bo); + LIST_DELINIT(&rpb->maplist); + } + + LIST_INITHEAD(&mgr->buffer_map_list); +} + +struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf) +{ + struct radeon_bo_pb *buf; + if (_buf->vtbl == &radeon_bo_pb_vtbl) { + buf = radeon_bo_pb(_buf); + return buf->bo; + } else { + struct pb_buffer *base_buf; + pb_size offset; + pb_get_base_buffer(_buf, &base_buf, &offset); + if (base_buf->vtbl == &radeon_bo_pb_vtbl) { + buf = radeon_bo_pb(base_buf); + return buf->bo; + } + } + return NULL; +} diff --git a/src/gallium/winsys/r600/drm/radeon_pciid.c b/src/gallium/winsys/r600/drm/radeon_pciid.c new file mode 100644 index 00000000000..08cc1c41e37 --- /dev/null +++ b/src/gallium/winsys/r600/drm/radeon_pciid.c @@ -0,0 +1,528 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <stdlib.h> +#include "r600.h" + +struct pci_id { + unsigned vendor; + unsigned device; + unsigned family; +}; + +struct pci_id radeon_pci_id[] = { + {0x1002, 0x3150, CHIP_RV380}, + {0x1002, 0x3152, CHIP_RV380}, + {0x1002, 0x3154, CHIP_RV380}, + {0x1002, 0x3E50, CHIP_RV380}, + {0x1002, 0x3E54, CHIP_RV380}, + {0x1002, 0x4136, CHIP_RS100}, + {0x1002, 0x4137, CHIP_RS200}, + {0x1002, 0x4144, CHIP_R300}, + {0x1002, 0x4145, CHIP_R300}, + {0x1002, 0x4146, CHIP_R300}, + {0x1002, 0x4147, CHIP_R300}, + {0x1002, 0x4148, CHIP_R350}, + {0x1002, 0x4149, CHIP_R350}, + {0x1002, 0x414A, CHIP_R350}, + {0x1002, 0x414B, CHIP_R350}, + {0x1002, 0x4150, CHIP_RV350}, + {0x1002, 0x4151, CHIP_RV350}, + {0x1002, 0x4152, CHIP_RV350}, + {0x1002, 0x4153, CHIP_RV350}, + {0x1002, 0x4154, CHIP_RV350}, + {0x1002, 0x4155, CHIP_RV350}, + {0x1002, 0x4156, CHIP_RV350}, + {0x1002, 0x4237, CHIP_RS200}, + {0x1002, 0x4242, CHIP_R200}, + {0x1002, 0x4243, CHIP_R200}, + {0x1002, 0x4336, CHIP_RS100}, + {0x1002, 0x4337, CHIP_RS200}, + {0x1002, 0x4437, CHIP_RS200}, + {0x1002, 0x4966, CHIP_RV250}, + {0x1002, 0x4967, CHIP_RV250}, + {0x1002, 0x4A48, CHIP_R420}, + {0x1002, 0x4A49, CHIP_R420}, + {0x1002, 0x4A4A, CHIP_R420}, + {0x1002, 0x4A4B, CHIP_R420}, + {0x1002, 0x4A4C, CHIP_R420}, + {0x1002, 0x4A4D, CHIP_R420}, + {0x1002, 0x4A4E, CHIP_R420}, + {0x1002, 0x4A4F, CHIP_R420}, + {0x1002, 0x4A50, CHIP_R420}, + {0x1002, 0x4A54, CHIP_R420}, + {0x1002, 0x4B48, CHIP_R420}, + {0x1002, 0x4B49, CHIP_R420}, + {0x1002, 0x4B4A, CHIP_R420}, + {0x1002, 0x4B4B, CHIP_R420}, + {0x1002, 0x4B4C, CHIP_R420}, + {0x1002, 0x4C57, CHIP_RV200}, + {0x1002, 0x4C58, CHIP_RV200}, + {0x1002, 0x4C59, CHIP_RV100}, + {0x1002, 0x4C5A, CHIP_RV100}, + {0x1002, 0x4C64, CHIP_RV250}, + {0x1002, 0x4C66, CHIP_RV250}, + {0x1002, 0x4C67, CHIP_RV250}, + {0x1002, 0x4E44, CHIP_R300}, + {0x1002, 0x4E45, CHIP_R300}, + {0x1002, 0x4E46, CHIP_R300}, + {0x1002, 0x4E47, CHIP_R300}, + {0x1002, 0x4E48, CHIP_R350}, + {0x1002, 0x4E49, CHIP_R350}, + {0x1002, 0x4E4A, CHIP_R350}, + {0x1002, 0x4E4B, CHIP_R350}, + {0x1002, 0x4E50, CHIP_RV350}, + {0x1002, 0x4E51, CHIP_RV350}, + {0x1002, 0x4E52, CHIP_RV350}, + {0x1002, 0x4E53, CHIP_RV350}, + {0x1002, 0x4E54, CHIP_RV350}, + {0x1002, 0x4E56, CHIP_RV350}, + {0x1002, 0x5144, CHIP_R100}, + {0x1002, 0x5145, CHIP_R100}, + {0x1002, 0x5146, CHIP_R100}, + {0x1002, 0x5147, CHIP_R100}, + {0x1002, 0x5148, CHIP_R200}, + {0x1002, 0x514C, CHIP_R200}, + {0x1002, 0x514D, CHIP_R200}, + {0x1002, 0x5157, CHIP_RV200}, + {0x1002, 0x5158, CHIP_RV200}, + {0x1002, 0x5159, CHIP_RV100}, + {0x1002, 0x515A, CHIP_RV100}, + {0x1002, 0x515E, CHIP_RV100}, + {0x1002, 0x5460, CHIP_RV380}, + {0x1002, 0x5462, CHIP_RV380}, + {0x1002, 0x5464, CHIP_RV380}, + {0x1002, 0x5657, CHIP_RV380}, + {0x1002, 0x5548, CHIP_R423}, + {0x1002, 0x5549, CHIP_R423}, + {0x1002, 0x554A, CHIP_R423}, + {0x1002, 0x554B, CHIP_R423}, + {0x1002, 0x554C, CHIP_R423}, + {0x1002, 0x554D, CHIP_R423}, + {0x1002, 0x554E, CHIP_R423}, + {0x1002, 0x554F, CHIP_R423}, + {0x1002, 0x5550, CHIP_R423}, + {0x1002, 0x5551, CHIP_R423}, + {0x1002, 0x5552, CHIP_R423}, + {0x1002, 0x5554, CHIP_R423}, + {0x1002, 0x564A, CHIP_RV410}, + {0x1002, 0x564B, CHIP_RV410}, + {0x1002, 0x564F, CHIP_RV410}, + {0x1002, 0x5652, CHIP_RV410}, + {0x1002, 0x5653, CHIP_RV410}, + {0x1002, 0x5834, CHIP_RS300}, + {0x1002, 0x5835, CHIP_RS300}, + {0x1002, 0x5954, CHIP_RS480}, + {0x1002, 0x5955, CHIP_RS480}, + {0x1002, 0x5974, CHIP_RS480}, + {0x1002, 0x5975, CHIP_RS480}, + {0x1002, 0x5960, CHIP_RV280}, + {0x1002, 0x5961, CHIP_RV280}, + {0x1002, 0x5962, CHIP_RV280}, + {0x1002, 0x5964, CHIP_RV280}, + {0x1002, 0x5965, CHIP_RV280}, + {0x1002, 0x5969, CHIP_RV100}, + {0x1002, 0x5a41, CHIP_RS400}, + {0x1002, 0x5a42, CHIP_RS400}, + {0x1002, 0x5a61, CHIP_RS400}, + {0x1002, 0x5a62, CHIP_RS400}, + {0x1002, 0x5b60, CHIP_RV380}, + {0x1002, 0x5b62, CHIP_RV380}, + {0x1002, 0x5b63, CHIP_RV380}, + {0x1002, 0x5b64, CHIP_RV380}, + {0x1002, 0x5b65, CHIP_RV380}, + {0x1002, 0x5c61, CHIP_RV280}, + {0x1002, 0x5c63, CHIP_RV280}, + {0x1002, 0x5d48, CHIP_R423}, + {0x1002, 0x5d49, CHIP_R423}, + {0x1002, 0x5d4a, CHIP_R423}, + {0x1002, 0x5d4c, CHIP_R423}, + {0x1002, 0x5d4d, CHIP_R423}, + {0x1002, 0x5d4e, CHIP_R423}, + {0x1002, 0x5d4f, CHIP_R423}, + {0x1002, 0x5d50, CHIP_R423}, + {0x1002, 0x5d52, CHIP_R423}, + {0x1002, 0x5d57, CHIP_R423}, + {0x1002, 0x5e48, CHIP_RV410}, + {0x1002, 0x5e4a, CHIP_RV410}, + {0x1002, 0x5e4b, CHIP_RV410}, + {0x1002, 0x5e4c, CHIP_RV410}, + {0x1002, 0x5e4d, CHIP_RV410}, + {0x1002, 0x5e4f, CHIP_RV410}, + {0x1002, 0x6880, CHIP_CYPRESS}, + {0x1002, 0x6888, CHIP_CYPRESS}, + {0x1002, 0x6889, CHIP_CYPRESS}, + {0x1002, 0x688A, CHIP_CYPRESS}, + {0x1002, 0x6898, CHIP_CYPRESS}, + {0x1002, 0x6899, CHIP_CYPRESS}, + {0x1002, 0x689c, CHIP_HEMLOCK}, + {0x1002, 0x689d, CHIP_HEMLOCK}, + {0x1002, 0x689e, CHIP_CYPRESS}, + {0x1002, 0x68a0, CHIP_JUNIPER}, + {0x1002, 0x68a1, CHIP_JUNIPER}, + {0x1002, 0x68a8, CHIP_JUNIPER}, + {0x1002, 0x68a9, CHIP_JUNIPER}, + {0x1002, 0x68b0, CHIP_JUNIPER}, + {0x1002, 0x68b8, CHIP_JUNIPER}, + {0x1002, 0x68b9, CHIP_JUNIPER}, + {0x1002, 0x68be, CHIP_JUNIPER}, + {0x1002, 0x68c0, CHIP_REDWOOD}, + {0x1002, 0x68c1, CHIP_REDWOOD}, + {0x1002, 0x68c8, CHIP_REDWOOD}, + {0x1002, 0x68c9, CHIP_REDWOOD}, + {0x1002, 0x68d8, CHIP_REDWOOD}, + {0x1002, 0x68d9, CHIP_REDWOOD}, + {0x1002, 0x68da, CHIP_REDWOOD}, + {0x1002, 0x68de, CHIP_REDWOOD}, + {0x1002, 0x68e0, CHIP_CEDAR}, + {0x1002, 0x68e1, CHIP_CEDAR}, + {0x1002, 0x68e4, CHIP_CEDAR}, + {0x1002, 0x68e5, CHIP_CEDAR}, + {0x1002, 0x68e8, CHIP_CEDAR}, + {0x1002, 0x68e9, CHIP_CEDAR}, + {0x1002, 0x68f1, CHIP_CEDAR}, + {0x1002, 0x68f8, CHIP_CEDAR}, + {0x1002, 0x68f9, CHIP_CEDAR}, + {0x1002, 0x68fe, CHIP_CEDAR}, + {0x1002, 0x7100, CHIP_R520}, + {0x1002, 0x7101, CHIP_R520}, + {0x1002, 0x7102, CHIP_R520}, + {0x1002, 0x7103, CHIP_R520}, + {0x1002, 0x7104, CHIP_R520}, + {0x1002, 0x7105, CHIP_R520}, + {0x1002, 0x7106, CHIP_R520}, + {0x1002, 0x7108, CHIP_R520}, + {0x1002, 0x7109, CHIP_R520}, + {0x1002, 0x710A, CHIP_R520}, + {0x1002, 0x710B, CHIP_R520}, + {0x1002, 0x710C, CHIP_R520}, + {0x1002, 0x710E, CHIP_R520}, + {0x1002, 0x710F, CHIP_R520}, + {0x1002, 0x7140, CHIP_RV515}, + {0x1002, 0x7141, CHIP_RV515}, + {0x1002, 0x7142, CHIP_RV515}, + {0x1002, 0x7143, CHIP_RV515}, + {0x1002, 0x7144, CHIP_RV515}, + {0x1002, 0x7145, CHIP_RV515}, + {0x1002, 0x7146, CHIP_RV515}, + {0x1002, 0x7147, CHIP_RV515}, + {0x1002, 0x7149, CHIP_RV515}, + {0x1002, 0x714A, CHIP_RV515}, + {0x1002, 0x714B, CHIP_RV515}, + {0x1002, 0x714C, CHIP_RV515}, + {0x1002, 0x714D, CHIP_RV515}, + {0x1002, 0x714E, CHIP_RV515}, + {0x1002, 0x714F, CHIP_RV515}, + {0x1002, 0x7151, CHIP_RV515}, + {0x1002, 0x7152, CHIP_RV515}, + {0x1002, 0x7153, CHIP_RV515}, + {0x1002, 0x715E, CHIP_RV515}, + {0x1002, 0x715F, CHIP_RV515}, + {0x1002, 0x7180, CHIP_RV515}, + {0x1002, 0x7181, CHIP_RV515}, + {0x1002, 0x7183, CHIP_RV515}, + {0x1002, 0x7186, CHIP_RV515}, + {0x1002, 0x7187, CHIP_RV515}, + {0x1002, 0x7188, CHIP_RV515}, + {0x1002, 0x718A, CHIP_RV515}, + {0x1002, 0x718B, CHIP_RV515}, + {0x1002, 0x718C, CHIP_RV515}, + {0x1002, 0x718D, CHIP_RV515}, + {0x1002, 0x718F, CHIP_RV515}, + {0x1002, 0x7193, CHIP_RV515}, + {0x1002, 0x7196, CHIP_RV515}, + {0x1002, 0x719B, CHIP_RV515}, + {0x1002, 0x719F, CHIP_RV515}, + {0x1002, 0x71C0, CHIP_RV530}, + {0x1002, 0x71C1, CHIP_RV530}, + {0x1002, 0x71C2, CHIP_RV530}, + {0x1002, 0x71C3, CHIP_RV530}, + {0x1002, 0x71C4, CHIP_RV530}, + {0x1002, 0x71C5, CHIP_RV530}, + {0x1002, 0x71C6, CHIP_RV530}, + {0x1002, 0x71C7, CHIP_RV530}, + {0x1002, 0x71CD, CHIP_RV530}, + {0x1002, 0x71CE, CHIP_RV530}, + {0x1002, 0x71D2, CHIP_RV530}, + {0x1002, 0x71D4, CHIP_RV530}, + {0x1002, 0x71D5, CHIP_RV530}, + {0x1002, 0x71D6, CHIP_RV530}, + {0x1002, 0x71DA, CHIP_RV530}, + {0x1002, 0x71DE, CHIP_RV530}, + {0x1002, 0x7200, CHIP_RV515}, + {0x1002, 0x7210, CHIP_RV515}, + {0x1002, 0x7211, CHIP_RV515}, + {0x1002, 0x7240, CHIP_R580}, + {0x1002, 0x7243, CHIP_R580}, + {0x1002, 0x7244, CHIP_R580}, + {0x1002, 0x7245, CHIP_R580}, + {0x1002, 0x7246, CHIP_R580}, + {0x1002, 0x7247, CHIP_R580}, + {0x1002, 0x7248, CHIP_R580}, + {0x1002, 0x7249, CHIP_R580}, + {0x1002, 0x724A, CHIP_R580}, + {0x1002, 0x724B, CHIP_R580}, + {0x1002, 0x724C, CHIP_R580}, + {0x1002, 0x724D, CHIP_R580}, + {0x1002, 0x724E, CHIP_R580}, + {0x1002, 0x724F, CHIP_R580}, + {0x1002, 0x7280, CHIP_RV570}, + {0x1002, 0x7281, CHIP_RV560}, + {0x1002, 0x7283, CHIP_RV560}, + {0x1002, 0x7284, CHIP_R580}, + {0x1002, 0x7287, CHIP_RV560}, + {0x1002, 0x7288, CHIP_RV570}, + {0x1002, 0x7289, CHIP_RV570}, + {0x1002, 0x728B, CHIP_RV570}, + {0x1002, 0x728C, CHIP_RV570}, + {0x1002, 0x7290, CHIP_RV560}, + {0x1002, 0x7291, CHIP_RV560}, + {0x1002, 0x7293, CHIP_RV560}, + {0x1002, 0x7297, CHIP_RV560}, + {0x1002, 0x7834, CHIP_RS300}, + {0x1002, 0x7835, CHIP_RS300}, + {0x1002, 0x791e, CHIP_RS690}, + {0x1002, 0x791f, CHIP_RS690}, + {0x1002, 0x793f, CHIP_RS600}, + {0x1002, 0x7941, CHIP_RS600}, + {0x1002, 0x7942, CHIP_RS600}, + {0x1002, 0x796c, CHIP_RS740}, + {0x1002, 0x796d, CHIP_RS740}, + {0x1002, 0x796e, CHIP_RS740}, + {0x1002, 0x796f, CHIP_RS740}, + {0x1002, 0x9400, CHIP_R600}, + {0x1002, 0x9401, CHIP_R600}, + {0x1002, 0x9402, CHIP_R600}, + {0x1002, 0x9403, CHIP_R600}, + {0x1002, 0x9405, CHIP_R600}, + {0x1002, 0x940A, CHIP_R600}, + {0x1002, 0x940B, CHIP_R600}, + {0x1002, 0x940F, CHIP_R600}, + {0x1002, 0x94A0, CHIP_RV740}, + {0x1002, 0x94A1, CHIP_RV740}, + {0x1002, 0x94A3, CHIP_RV740}, + {0x1002, 0x94B1, CHIP_RV740}, + {0x1002, 0x94B3, CHIP_RV740}, + {0x1002, 0x94B4, CHIP_RV740}, + {0x1002, 0x94B5, CHIP_RV740}, + {0x1002, 0x94B9, CHIP_RV740}, + {0x1002, 0x9440, CHIP_RV770}, + {0x1002, 0x9441, CHIP_RV770}, + {0x1002, 0x9442, CHIP_RV770}, + {0x1002, 0x9443, CHIP_RV770}, + {0x1002, 0x9444, CHIP_RV770}, + {0x1002, 0x9446, CHIP_RV770}, + {0x1002, 0x944A, CHIP_RV770}, + {0x1002, 0x944B, CHIP_RV770}, + {0x1002, 0x944C, CHIP_RV770}, + {0x1002, 0x944E, CHIP_RV770}, + {0x1002, 0x9450, CHIP_RV770}, + {0x1002, 0x9452, CHIP_RV770}, + {0x1002, 0x9456, CHIP_RV770}, + {0x1002, 0x945A, CHIP_RV770}, + {0x1002, 0x945B, CHIP_RV770}, + {0x1002, 0x9460, CHIP_RV770}, + {0x1002, 0x9462, CHIP_RV770}, + {0x1002, 0x946A, CHIP_RV770}, + {0x1002, 0x946B, CHIP_RV770}, + {0x1002, 0x947A, CHIP_RV770}, + {0x1002, 0x947B, CHIP_RV770}, + {0x1002, 0x9480, CHIP_RV730}, + {0x1002, 0x9487, CHIP_RV730}, + {0x1002, 0x9488, CHIP_RV730}, + {0x1002, 0x9489, CHIP_RV730}, + {0x1002, 0x948F, CHIP_RV730}, + {0x1002, 0x9490, CHIP_RV730}, + {0x1002, 0x9491, CHIP_RV730}, + {0x1002, 0x9495, CHIP_RV730}, + {0x1002, 0x9498, CHIP_RV730}, + {0x1002, 0x949C, CHIP_RV730}, + {0x1002, 0x949E, CHIP_RV730}, + {0x1002, 0x949F, CHIP_RV730}, + {0x1002, 0x94C0, CHIP_RV610}, + {0x1002, 0x94C1, CHIP_RV610}, + {0x1002, 0x94C3, CHIP_RV610}, + {0x1002, 0x94C4, CHIP_RV610}, + {0x1002, 0x94C5, CHIP_RV610}, + {0x1002, 0x94C6, CHIP_RV610}, + {0x1002, 0x94C7, CHIP_RV610}, + {0x1002, 0x94C8, CHIP_RV610}, + {0x1002, 0x94C9, CHIP_RV610}, + {0x1002, 0x94CB, CHIP_RV610}, + {0x1002, 0x94CC, CHIP_RV610}, + {0x1002, 0x94CD, CHIP_RV610}, + {0x1002, 0x9500, CHIP_RV670}, + {0x1002, 0x9501, CHIP_RV670}, + {0x1002, 0x9504, CHIP_RV670}, + {0x1002, 0x9505, CHIP_RV670}, + {0x1002, 0x9506, CHIP_RV670}, + {0x1002, 0x9507, CHIP_RV670}, + {0x1002, 0x9508, CHIP_RV670}, + {0x1002, 0x9509, CHIP_RV670}, + {0x1002, 0x950F, CHIP_RV670}, + {0x1002, 0x9511, CHIP_RV670}, + {0x1002, 0x9515, CHIP_RV670}, + {0x1002, 0x9517, CHIP_RV670}, + {0x1002, 0x9519, CHIP_RV670}, + {0x1002, 0x9540, CHIP_RV710}, + {0x1002, 0x9541, CHIP_RV710}, + {0x1002, 0x9542, CHIP_RV710}, + {0x1002, 0x954E, CHIP_RV710}, + {0x1002, 0x954F, CHIP_RV710}, + {0x1002, 0x9552, CHIP_RV710}, + {0x1002, 0x9553, CHIP_RV710}, + {0x1002, 0x9555, CHIP_RV710}, + {0x1002, 0x9557, CHIP_RV710}, + {0x1002, 0x9580, CHIP_RV630}, + {0x1002, 0x9581, CHIP_RV630}, + {0x1002, 0x9583, CHIP_RV630}, + {0x1002, 0x9586, CHIP_RV630}, + {0x1002, 0x9587, CHIP_RV630}, + {0x1002, 0x9588, CHIP_RV630}, + {0x1002, 0x9589, CHIP_RV630}, + {0x1002, 0x958A, CHIP_RV630}, + {0x1002, 0x958B, CHIP_RV630}, + {0x1002, 0x958C, CHIP_RV630}, + {0x1002, 0x958D, CHIP_RV630}, + {0x1002, 0x958E, CHIP_RV630}, + {0x1002, 0x958F, CHIP_RV630}, + {0x1002, 0x9590, CHIP_RV635}, + {0x1002, 0x9591, CHIP_RV635}, + {0x1002, 0x9593, CHIP_RV635}, + {0x1002, 0x9595, CHIP_RV635}, + {0x1002, 0x9596, CHIP_RV635}, + {0x1002, 0x9597, CHIP_RV635}, + {0x1002, 0x9598, CHIP_RV635}, + {0x1002, 0x9599, CHIP_RV635}, + {0x1002, 0x959B, CHIP_RV635}, + {0x1002, 0x95C0, CHIP_RV620}, + {0x1002, 0x95C2, CHIP_RV620}, + {0x1002, 0x95C4, CHIP_RV620}, + {0x1002, 0x95C5, CHIP_RV620}, + {0x1002, 0x95C6, CHIP_RV620}, + {0x1002, 0x95C7, CHIP_RV620}, + {0x1002, 0x95C9, CHIP_RV620}, + {0x1002, 0x95CC, CHIP_RV620}, + {0x1002, 0x95CD, CHIP_RV620}, + {0x1002, 0x95CE, CHIP_RV620}, + {0x1002, 0x95CF, CHIP_RV620}, + {0x1002, 0x9610, CHIP_RS780}, + {0x1002, 0x9611, CHIP_RS780}, + {0x1002, 0x9612, CHIP_RS780}, + {0x1002, 0x9613, CHIP_RS780}, + {0x1002, 0x9614, CHIP_RS780}, + {0x1002, 0x9615, CHIP_RS780}, + {0x1002, 0x9616, CHIP_RS780}, + {0x1002, 0x9710, CHIP_RS880}, + {0x1002, 0x9711, CHIP_RS880}, + {0x1002, 0x9712, CHIP_RS880}, + {0x1002, 0x9713, CHIP_RS880}, + {0x1002, 0x9714, CHIP_RS880}, + {0x1002, 0x9715, CHIP_RS880}, + {0, 0}, +}; + +unsigned radeon_family_from_device(unsigned device) +{ + unsigned i; + + for (i = 0; ; i++) { + if (!radeon_pci_id[i].vendor) + return CHIP_UNKNOWN; + if (radeon_pci_id[i].device == device) + return radeon_pci_id[i].family; + } + return CHIP_UNKNOWN; +} + +int radeon_is_family_compatible(unsigned family1, unsigned family2) +{ + switch (family1) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + switch (family2) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + return 1; + default: + return 0; + } + break; + case CHIP_R100: + case CHIP_RV100: + case CHIP_RS100: + case CHIP_RV200: + case CHIP_RS200: + case CHIP_R200: + case CHIP_RV250: + case CHIP_RS300: + case CHIP_RV280: + case CHIP_R300: + case CHIP_R350: + case CHIP_RV350: + case CHIP_RV380: + case CHIP_R420: + case CHIP_R423: + case CHIP_RV410: + case CHIP_RS400: + case CHIP_RS480: + case CHIP_RS600: + case CHIP_RS690: + case CHIP_RS740: + case CHIP_RV515: + case CHIP_R520: + case CHIP_RV530: + case CHIP_RV560: + case CHIP_RV570: + case CHIP_R580: + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + default: + return 0; + } +} diff --git a/src/gallium/winsys/radeon/drm/radeon_buffer.h b/src/gallium/winsys/radeon/drm/radeon_buffer.h index b48b6358e01..a8137d85e83 100644 --- a/src/gallium/winsys/radeon/drm/radeon_buffer.h +++ b/src/gallium/winsys/radeon/drm/radeon_buffer.h @@ -43,8 +43,9 @@ #include "radeon_winsys.h" - -#define RADEON_MAX_BOS 24 +#define RADEON_PB_USAGE_VERTEX (1 << 28) +#define RADEON_PB_USAGE_DOMAIN_GTT (1 << 29) +#define RADEON_PB_USAGE_DOMAIN_VRAM (1 << 30) static INLINE struct pb_buffer * radeon_pb_buffer(struct r300_winsys_buffer *buffer) @@ -61,22 +62,26 @@ radeon_libdrm_winsys_buffer(struct pb_buffer *buffer) struct pb_manager * radeon_drm_bufmgr_create(struct radeon_libdrm_winsys *rws); -boolean radeon_drm_bufmgr_add_buffer(struct pb_buffer *_buf, - uint32_t rd, uint32_t wd); - +void radeon_drm_bufmgr_add_buffer(struct r300_winsys_cs *cs, + struct r300_winsys_buffer *buf, + enum r300_buffer_domain rd, + enum r300_buffer_domain wd); -void radeon_drm_bufmgr_write_reloc(struct pb_buffer *_buf, - uint32_t rd, uint32_t wd, - uint32_t flags); +void radeon_drm_bufmgr_write_reloc(struct r300_winsys_cs *cs, + struct r300_winsys_buffer *buf, + enum r300_buffer_domain rd, + enum r300_buffer_domain wd); struct pb_buffer *radeon_drm_bufmgr_create_buffer_from_handle(struct pb_manager *_mgr, uint32_t handle); -void radeon_drm_bufmgr_get_tiling(struct pb_buffer *_buf, +void radeon_drm_bufmgr_get_tiling(struct r300_winsys_screen *ws, + struct r300_winsys_buffer *buf, enum r300_buffer_tiling *microtiled, enum r300_buffer_tiling *macrotiled); -void radeon_drm_bufmgr_set_tiling(struct pb_buffer *_buf, +void radeon_drm_bufmgr_set_tiling(struct r300_winsys_screen *ws, + struct r300_winsys_buffer *buf, enum r300_buffer_tiling microtiled, enum r300_buffer_tiling macrotiled, uint32_t pitch); @@ -86,6 +91,19 @@ void radeon_drm_bufmgr_flush_maps(struct pb_manager *_mgr); boolean radeon_drm_bufmgr_get_handle(struct pb_buffer *_buf, struct winsys_handle *whandle); -boolean radeon_drm_bufmgr_is_buffer_referenced(struct pb_buffer *_buf, +boolean radeon_drm_bufmgr_is_buffer_referenced(struct r300_winsys_cs *cs, + struct r300_winsys_buffer *buf, enum r300_reference_domain domain); + +void radeon_drm_bufmgr_wait(struct r300_winsys_screen *ws, + struct r300_winsys_buffer *buf); + +void *radeon_drm_buffer_map(struct r300_winsys_screen *ws, + struct r300_winsys_buffer *buf, + struct r300_winsys_cs *cs, + enum pipe_transfer_usage usage); + +void radeon_drm_buffer_unmap(struct r300_winsys_screen *ws, + struct r300_winsys_buffer *buf); + #endif diff --git a/src/gallium/winsys/radeon/drm/radeon_drm.c b/src/gallium/winsys/radeon/drm/radeon_drm.c index 8d981b22e3d..86d4f949697 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm.c @@ -32,14 +32,13 @@ #include "radeon_drm.h" #include "radeon_r300.h" #include "radeon_buffer.h" +#include "radeon_drm_public.h" #include "r300_winsys.h" -#include "trace/tr_drm.h" #include "util/u_memory.h" #include "xf86drm.h" -#include <sys/ioctl.h> static struct radeon_libdrm_winsys * radeon_winsys_create(int fd) @@ -55,6 +54,31 @@ radeon_winsys_create(int fd) return rws; } +/* Enable/disable Hyper-Z access. Return TRUE on success. */ +static boolean radeon_set_hyperz_access(int fd, boolean enable) +{ +#ifndef RADEON_INFO_WANT_HYPERZ +#define RADEON_INFO_WANT_HYPERZ 7 +#endif + + struct drm_radeon_info info = {0}; + unsigned value = enable ? 1 : 0; + + if (!debug_get_bool_option("RADEON_HYPERZ", FALSE)) + return FALSE; + + info.value = (unsigned long)&value; + info.request = RADEON_INFO_WANT_HYPERZ; + + if (drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info)) != 0) + return FALSE; + + if (enable && !value) + return FALSE; + + return TRUE; +} + /* Helper function to do the ioctls needed for setup and init. */ static void do_ioctls(int fd, struct radeon_libdrm_winsys* winsys) { @@ -103,6 +127,10 @@ static void do_ioctls(int fd, struct radeon_libdrm_winsys* winsys) winsys->drm_2_3_0 = version->version_major > 2 || version->version_minor >= 3; + winsys->drm_2_6_0 = version->version_major > 2 || + (version->version_major == 2 && + version->version_minor >= 6); + info.request = RADEON_INFO_DEVICE_ID; retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info)); if (retval) { @@ -130,6 +158,8 @@ static void do_ioctls(int fd, struct radeon_libdrm_winsys* winsys) } winsys->z_pipes = target; + winsys->hyperz = radeon_set_hyperz_access(fd, TRUE); + retval = drmCommandWriteRead(fd, DRM_RADEON_GEM_INFO, &gem_info, sizeof(gem_info)); if (retval) { @@ -142,20 +172,20 @@ static void do_ioctls(int fd, struct radeon_libdrm_winsys* winsys) debug_printf("radeon: Successfully grabbed chipset info from kernel!\n" "radeon: DRM version: %d.%d.%d ID: 0x%04x GB: %d Z: %d\n" - "radeon: GART size: %d MB VRAM size: %d MB\n", + "radeon: GART size: %d MB VRAM size: %d MB\n" + "radeon: HyperZ: %s\n", version->version_major, version->version_minor, version->version_patchlevel, winsys->pci_id, winsys->gb_pipes, winsys->z_pipes, winsys->gart_size / 1024 / 1024, - winsys->vram_size / 1024 / 1024); + winsys->vram_size / 1024 / 1024, + winsys->hyperz ? "YES" : "NO"); drmFreeVersion(version); } /* Create a pipe_screen. */ -struct pipe_screen* radeon_create_screen(struct drm_api* api, - int drmFB, - struct drm_create_screen_arg *arg) +struct r300_winsys_screen* r300_drm_winsys_screen_create(int drmFB) { struct radeon_libdrm_winsys* rws; boolean ret; @@ -173,22 +203,10 @@ struct pipe_screen* radeon_create_screen(struct drm_api* api, ret = radeon_setup_winsys(drmFB, rws); if (ret == FALSE) goto fail; - return r300_create_screen(&rws->base); + return &rws->base; } fail: FREE(rws); return NULL; } - -static struct drm_api radeon_drm_api_hooks = { - .name = "radeon", - .driver_name = "radeon", - .create_screen = radeon_create_screen, - .destroy = NULL, -}; - -struct drm_api* drm_api_create() -{ - return trace_drm_create(&radeon_drm_api_hooks); -} diff --git a/src/gallium/winsys/radeon/drm/radeon_drm.h b/src/gallium/winsys/radeon/drm/radeon_drm.h index 78451b6f011..df6dd91ad54 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm.h +++ b/src/gallium/winsys/radeon/drm/radeon_drm.h @@ -30,14 +30,7 @@ #ifndef RADEON_DRM_H #define RADEON_DRM_H -#include "state_tracker/drm_api.h" - - -struct pipe_screen* radeon_create_screen(struct drm_api* api, - int drmFB, - struct drm_create_screen_arg *arg); - -void radeon_destroy_drm_api(struct drm_api* api); +#include "state_tracker/drm_driver.h" /* Guess at whether this chipset should use r300g. * diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_buffer.c b/src/gallium/winsys/radeon/drm/radeon_drm_buffer.c index 9824ada5b33..78723948d41 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_buffer.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_buffer.c @@ -5,13 +5,16 @@ #include "radeon_cs_gem.h" #include "radeon_buffer.h" +#include "util/u_hash_table.h" #include "util/u_inlines.h" #include "util/u_memory.h" #include "util/u_simple_list.h" #include "pipebuffer/pb_buffer.h" #include "pipebuffer/pb_bufmgr.h" +#include "os/os_thread.h" #include "radeon_winsys.h" + struct radeon_drm_bufmgr; struct radeon_drm_buffer { @@ -38,9 +41,19 @@ radeon_drm_buffer(struct pb_buffer *buf) } struct radeon_drm_bufmgr { + /* Base class. */ struct pb_manager base; + + /* Winsys. */ struct radeon_libdrm_winsys *rws; + + /* List of mapped buffers and its mutex. */ struct radeon_drm_buffer buffer_map_list; + pipe_mutex buffer_map_list_mutex; + + /* List of buffer handles and its mutex. */ + struct util_hash_table *buffer_handles; + pipe_mutex buffer_handles_mutex; }; static INLINE struct radeon_drm_bufmgr * @@ -54,59 +67,123 @@ static void radeon_drm_buffer_destroy(struct pb_buffer *_buf) { struct radeon_drm_buffer *buf = radeon_drm_buffer(_buf); + int name; if (buf->bo->ptr != NULL) { - remove_from_list(buf); - radeon_bo_unmap(buf->bo); - buf->bo->ptr = NULL; + pipe_mutex_lock(buf->mgr->buffer_map_list_mutex); + /* Now test it again inside the mutex. */ + if (buf->bo->ptr != NULL) { + remove_from_list(buf); + radeon_bo_unmap(buf->bo); + buf->bo->ptr = NULL; + } + pipe_mutex_unlock(buf->mgr->buffer_map_list_mutex); + } + name = radeon_gem_name_bo(buf->bo); + if (name) { + pipe_mutex_lock(buf->mgr->buffer_handles_mutex); + util_hash_table_remove(buf->mgr->buffer_handles, + (void*)(uintptr_t)name); + pipe_mutex_unlock(buf->mgr->buffer_handles_mutex); } radeon_bo_unref(buf->bo); FREE(buf); } +static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage) +{ + unsigned res = 0; + + if (usage & PIPE_TRANSFER_READ) + res |= PB_USAGE_CPU_READ; + + if (usage & PIPE_TRANSFER_WRITE) + res |= PB_USAGE_CPU_WRITE; + + if (usage & PIPE_TRANSFER_DONTBLOCK) + res |= PB_USAGE_DONTBLOCK; + + if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) + res |= PB_USAGE_UNSYNCHRONIZED; + + return res; +} + static void * -radeon_drm_buffer_map(struct pb_buffer *_buf, - unsigned flags) +radeon_drm_buffer_map_internal(struct pb_buffer *_buf, + unsigned flags, void *flush_ctx) { struct radeon_drm_buffer *buf = radeon_drm_buffer(_buf); + struct radeon_libdrm_cs *cs = flush_ctx; int write = 0; - if (flags & PIPE_TRANSFER_DONTBLOCK) { - if ((_buf->base.usage & PIPE_BIND_VERTEX_BUFFER) || - (_buf->base.usage & PIPE_BIND_INDEX_BUFFER)) - if (radeon_bo_is_referenced_by_cs(buf->bo, buf->mgr->rws->cs)) + /* Note how we use radeon_bo_is_referenced_by_cs here. There are + * basically two places this map function can be called from: + * - pb_map + * - create_buffer (in the buffer reuse case) + * + * Since pb managers are per-winsys managers, not per-context managers, + * and we shouldn't reuse buffers if they are in-use in any context, + * we simply ask: is this buffer referenced by *any* CS? + * + * The problem with buffer_create is that it comes from pipe_screen, + * so we have no CS to look at, though luckily the following code + * is sufficient to tell whether the buffer is in use. */ + if (flags & PB_USAGE_DONTBLOCK) { + if (_buf->base.usage & RADEON_PB_USAGE_VERTEX) + if (radeon_bo_is_referenced_by_cs(buf->bo, NULL)) return NULL; } - if (buf->bo->ptr != NULL) + if (buf->bo->ptr != NULL) { + pipe_mutex_lock(buf->mgr->buffer_map_list_mutex); + /* Now test ptr again inside the mutex. We might have gotten a race + * during the first test. */ + if (buf->bo->ptr != NULL) { + remove_from_list(buf); + } + pipe_mutex_unlock(buf->mgr->buffer_map_list_mutex); return buf->bo->ptr; + } - if (flags & PIPE_TRANSFER_DONTBLOCK) { + if (flags & PB_USAGE_DONTBLOCK) { uint32_t domain; if (radeon_bo_is_busy(buf->bo, &domain)) return NULL; } - if (radeon_bo_is_referenced_by_cs(buf->bo, buf->mgr->rws->cs)) { - buf->mgr->rws->flush_cb(buf->mgr->rws->flush_data); + /* If we don't have any CS and the buffer is referenced, + * we cannot flush. */ + assert(cs || !radeon_bo_is_referenced_by_cs(buf->bo, NULL)); + + if (cs && radeon_bo_is_referenced_by_cs(buf->bo, cs->cs)) { + cs->flush_cs(cs->flush_data); } - if (flags & PIPE_TRANSFER_WRITE) { + if (flags & PB_USAGE_CPU_WRITE) { write = 1; } if (radeon_bo_map(buf->bo, write)) { return NULL; } - insert_at_tail(&buf->mgr->buffer_map_list, buf); + + pipe_mutex_lock(buf->mgr->buffer_map_list_mutex); + remove_from_list(buf); + pipe_mutex_unlock(buf->mgr->buffer_map_list_mutex); return buf->bo->ptr; } static void -radeon_drm_buffer_unmap(struct pb_buffer *_buf) +radeon_drm_buffer_unmap_internal(struct pb_buffer *_buf) { - (void)_buf; + struct radeon_drm_buffer *buf = radeon_drm_buffer(_buf); + pipe_mutex_lock(buf->mgr->buffer_map_list_mutex); + if (is_empty_list(buf)) { /* = is not inserted... */ + insert_at_tail(&buf->mgr->buffer_map_list, buf); + } + pipe_mutex_unlock(buf->mgr->buffer_map_list_mutex); } static void @@ -120,7 +197,7 @@ radeon_drm_buffer_get_base_buffer(struct pb_buffer *buf, static enum pipe_error -radeon_drm_buffer_validate(struct pb_buffer *_buf, +radeon_drm_buffer_validate(struct pb_buffer *_buf, struct pb_validate *vl, unsigned flags) { @@ -136,46 +213,30 @@ radeon_drm_buffer_fence(struct pb_buffer *buf, const struct pb_vtbl radeon_drm_buffer_vtbl = { radeon_drm_buffer_destroy, - radeon_drm_buffer_map, - radeon_drm_buffer_unmap, + radeon_drm_buffer_map_internal, + radeon_drm_buffer_unmap_internal, radeon_drm_buffer_validate, radeon_drm_buffer_fence, radeon_drm_buffer_get_base_buffer, }; - -static uint32_t radeon_domain_from_usage(unsigned usage) -{ - uint32_t domain = 0; - - if (usage & PIPE_BIND_RENDER_TARGET) { - domain |= RADEON_GEM_DOMAIN_VRAM; - } - if (usage & PIPE_BIND_DEPTH_STENCIL) { - domain |= RADEON_GEM_DOMAIN_VRAM; - } - if (usage & PIPE_BIND_SAMPLER_VIEW) { - domain |= RADEON_GEM_DOMAIN_VRAM; - } - /* also need BIND_BLIT_SOURCE/DESTINATION ? */ - if (usage & PIPE_BIND_VERTEX_BUFFER) { - domain |= RADEON_GEM_DOMAIN_GTT; - } - if (usage & PIPE_BIND_INDEX_BUFFER) { - domain |= RADEON_GEM_DOMAIN_GTT; - } - - return domain; -} - -struct pb_buffer *radeon_drm_bufmgr_create_buffer_from_handle(struct pb_manager *_mgr, - uint32_t handle) +static struct pb_buffer * +radeon_drm_bufmgr_create_buffer_from_handle_unsafe(struct pb_manager *_mgr, + uint32_t handle) { struct radeon_drm_bufmgr *mgr = radeon_drm_bufmgr(_mgr); struct radeon_libdrm_winsys *rws = mgr->rws; struct radeon_drm_buffer *buf; struct radeon_bo *bo; + buf = util_hash_table_get(mgr->buffer_handles, (void*)(uintptr_t)handle); + + if (buf) { + struct pb_buffer *b = NULL; + pb_reference(&b, &buf->base); + return b; + } + bo = radeon_bo_open(rws->bom, handle, 0, 0, 0, 0); if (bo == NULL) @@ -191,16 +252,32 @@ struct pb_buffer *radeon_drm_bufmgr_create_buffer_from_handle(struct pb_manager pipe_reference_init(&buf->base.base.reference, 1); buf->base.base.alignment = 0; - buf->base.base.usage = PIPE_BIND_SAMPLER_VIEW; - buf->base.base.size = 0; + buf->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ; + buf->base.base.size = bo->size; buf->base.vtbl = &radeon_drm_buffer_vtbl; buf->mgr = mgr; buf->bo = bo; + util_hash_table_set(mgr->buffer_handles, (void*)(uintptr_t)handle, buf); + return &buf->base; } +struct pb_buffer * +radeon_drm_bufmgr_create_buffer_from_handle(struct pb_manager *_mgr, + uint32_t handle) +{ + struct radeon_drm_bufmgr *mgr = radeon_drm_bufmgr(_mgr); + struct pb_buffer *pb; + + pipe_mutex_lock(mgr->buffer_handles_mutex); + pb = radeon_drm_bufmgr_create_buffer_from_handle_unsafe(_mgr, handle); + pipe_mutex_unlock(mgr->buffer_handles_mutex); + + return pb; +} + static struct pb_buffer * radeon_drm_bufmgr_create_buffer(struct pb_manager *_mgr, pb_size size, @@ -223,7 +300,11 @@ radeon_drm_bufmgr_create_buffer(struct pb_manager *_mgr, buf->mgr = mgr; make_empty_list(buf); - domain = radeon_domain_from_usage(desc->usage); + + domain = + (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT ? RADEON_GEM_DOMAIN_GTT : 0) | + (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ? RADEON_GEM_DOMAIN_VRAM : 0); + buf->bo = radeon_bo_open(rws->bom, 0, size, desc->alignment, domain, 0); if (buf->bo == NULL) @@ -247,9 +328,22 @@ static void radeon_drm_bufmgr_destroy(struct pb_manager *_mgr) { struct radeon_drm_bufmgr *mgr = radeon_drm_bufmgr(_mgr); + util_hash_table_destroy(mgr->buffer_handles); + pipe_mutex_destroy(mgr->buffer_map_list_mutex); + pipe_mutex_destroy(mgr->buffer_handles_mutex); FREE(mgr); } +static unsigned handle_hash(void *key) +{ + return (unsigned)key; +} + +static int handle_compare(void *key1, void *key2) +{ + return !((int)key1 == (int)key2); +} + struct pb_manager * radeon_drm_bufmgr_create(struct radeon_libdrm_winsys *rws) { @@ -265,12 +359,16 @@ radeon_drm_bufmgr_create(struct radeon_libdrm_winsys *rws) mgr->rws = rws; make_empty_list(&mgr->buffer_map_list); + mgr->buffer_handles = util_hash_table_create(handle_hash, handle_compare); + pipe_mutex_init(mgr->buffer_map_list_mutex); + pipe_mutex_init(mgr->buffer_handles_mutex); return &mgr->base; } static struct radeon_drm_buffer *get_drm_buffer(struct pb_buffer *_buf) { - struct radeon_drm_buffer *buf; + struct radeon_drm_buffer *buf = NULL; + if (_buf->vtbl == &radeon_drm_buffer_vtbl) { buf = radeon_drm_buffer(_buf); } else { @@ -278,24 +376,42 @@ static struct radeon_drm_buffer *get_drm_buffer(struct pb_buffer *_buf) pb_size offset; pb_get_base_buffer(_buf, &base_buf, &offset); - buf = radeon_drm_buffer(base_buf); + if (base_buf->vtbl == &radeon_drm_buffer_vtbl) + buf = radeon_drm_buffer(base_buf); } + return buf; } +void *radeon_drm_buffer_map(struct r300_winsys_screen *ws, + struct r300_winsys_buffer *buf, + struct r300_winsys_cs *cs, + enum pipe_transfer_usage usage) +{ + struct pb_buffer *_buf = radeon_pb_buffer(buf); + + return pb_map(_buf, get_pb_usage_from_transfer_flags(usage), radeon_libdrm_cs(cs)); +} + +void radeon_drm_buffer_unmap(struct r300_winsys_screen *ws, + struct r300_winsys_buffer *buf) +{ + struct pb_buffer *_buf = radeon_pb_buffer(buf); + + pb_unmap(_buf); +} + boolean radeon_drm_bufmgr_get_handle(struct pb_buffer *_buf, struct winsys_handle *whandle) { - int retval, fd; struct drm_gem_flink flink; struct radeon_drm_buffer *buf = get_drm_buffer(_buf); + if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { if (!buf->flinked) { - fd = buf->mgr->rws->fd; flink.handle = buf->bo->handle; - retval = ioctl(fd, DRM_IOCTL_GEM_FLINK, &flink); - if (retval) { + if (ioctl(buf->mgr->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) { return FALSE; } @@ -309,11 +425,12 @@ boolean radeon_drm_bufmgr_get_handle(struct pb_buffer *_buf, return TRUE; } -void radeon_drm_bufmgr_get_tiling(struct pb_buffer *_buf, +void radeon_drm_bufmgr_get_tiling(struct r300_winsys_screen *ws, + struct r300_winsys_buffer *_buf, enum r300_buffer_tiling *microtiled, enum r300_buffer_tiling *macrotiled) { - struct radeon_drm_buffer *buf = get_drm_buffer(_buf); + struct radeon_drm_buffer *buf = get_drm_buffer(radeon_pb_buffer(_buf)); uint32_t flags = 0, pitch; radeon_bo_get_tiling(buf->bo, &flags, &pitch); @@ -327,13 +444,14 @@ void radeon_drm_bufmgr_get_tiling(struct pb_buffer *_buf, *macrotiled = R300_BUFFER_TILED; } -void radeon_drm_bufmgr_set_tiling(struct pb_buffer *_buf, +void radeon_drm_bufmgr_set_tiling(struct r300_winsys_screen *ws, + struct r300_winsys_buffer *_buf, enum r300_buffer_tiling microtiled, enum r300_buffer_tiling macrotiled, uint32_t pitch) { - struct radeon_drm_buffer *buf = get_drm_buffer(_buf); - uint32_t flags = 0, old_flags, old_pitch; + struct radeon_drm_buffer *buf = get_drm_buffer(radeon_pb_buffer(_buf)); + uint32_t flags = 0; if (microtiled == R300_BUFFER_TILED) flags |= RADEON_BO_FLAGS_MICRO_TILE; /* XXX Remove this ifdef when libdrm version 2.4.19 becomes mandatory. */ @@ -344,51 +462,63 @@ void radeon_drm_bufmgr_set_tiling(struct pb_buffer *_buf, if (macrotiled == R300_BUFFER_TILED) flags |= RADEON_BO_FLAGS_MACRO_TILE; - radeon_bo_get_tiling(buf->bo, &old_flags, &old_pitch); - - if (flags != old_flags || pitch != old_pitch) { - /* Tiling determines how DRM treats the buffer data. - * We must flush CS when changing it if the buffer is referenced. */ - if (radeon_bo_is_referenced_by_cs(buf->bo, buf->mgr->rws->cs)) { - buf->mgr->rws->flush_cb(buf->mgr->rws->flush_data); - } - } radeon_bo_set_tiling(buf->bo, flags, pitch); +} + +static uint32_t get_gem_domain(enum r300_buffer_domain domain) +{ + uint32_t res = 0; + if (domain & R300_DOMAIN_GTT) + res |= RADEON_GEM_DOMAIN_GTT; + if (domain & R300_DOMAIN_VRAM) + res |= RADEON_GEM_DOMAIN_VRAM; + return res; } -boolean radeon_drm_bufmgr_add_buffer(struct pb_buffer *_buf, - uint32_t rd, uint32_t wd) +void radeon_drm_bufmgr_add_buffer(struct r300_winsys_cs *rcs, + struct r300_winsys_buffer *_buf, + enum r300_buffer_domain rd, + enum r300_buffer_domain wd) { - struct radeon_drm_buffer *buf = get_drm_buffer(_buf); - radeon_cs_space_add_persistent_bo(buf->mgr->rws->cs, buf->bo, - rd, wd); - return TRUE; + struct radeon_libdrm_cs *cs = radeon_libdrm_cs(rcs); + struct radeon_drm_buffer *buf = get_drm_buffer(radeon_pb_buffer(_buf)); + uint32_t gem_rd = get_gem_domain(rd); + uint32_t gem_wd = get_gem_domain(wd); + + radeon_cs_space_add_persistent_bo(cs->cs, buf->bo, gem_rd, gem_wd); } -void radeon_drm_bufmgr_write_reloc(struct pb_buffer *_buf, - uint32_t rd, uint32_t wd, - uint32_t flags) +void radeon_drm_bufmgr_write_reloc(struct r300_winsys_cs *rcs, + struct r300_winsys_buffer *_buf, + enum r300_buffer_domain rd, + enum r300_buffer_domain wd) { - struct radeon_drm_buffer *buf = get_drm_buffer(_buf); + struct radeon_libdrm_cs *cs = radeon_libdrm_cs(rcs); + struct radeon_drm_buffer *buf = get_drm_buffer(radeon_pb_buffer(_buf)); int retval; + uint32_t gem_rd = get_gem_domain(rd); + uint32_t gem_wd = get_gem_domain(wd); - retval = radeon_cs_write_reloc(buf->mgr->rws->cs, - buf->bo, rd, wd, flags); + cs->cs->cdw = cs->base.cdw; + retval = radeon_cs_write_reloc(cs->cs, buf->bo, gem_rd, gem_wd, 0); + cs->base.cdw = cs->cs->cdw; if (retval) { - debug_printf("radeon: Relocation of %p (%d, %d, %d) failed!\n", - buf, rd, wd, flags); + fprintf(stderr, "radeon: Relocation of %p (%d, %d, %d) failed!\n", + buf, gem_rd, gem_wd, 0); } } -boolean radeon_drm_bufmgr_is_buffer_referenced(struct pb_buffer *_buf, +boolean radeon_drm_bufmgr_is_buffer_referenced(struct r300_winsys_cs *rcs, + struct r300_winsys_buffer *_buf, enum r300_reference_domain domain) { - struct radeon_drm_buffer *buf = get_drm_buffer(_buf); + struct radeon_libdrm_cs *cs = radeon_libdrm_cs(rcs); + struct radeon_drm_buffer *buf = get_drm_buffer(radeon_pb_buffer(_buf)); uint32_t tmp; if (domain & R300_REF_CS) { - if (radeon_bo_is_referenced_by_cs(buf->bo, buf->mgr->rws->cs)) { + if (radeon_bo_is_referenced_by_cs(buf->bo, cs->cs)) { return TRUE; } } @@ -402,12 +532,13 @@ boolean radeon_drm_bufmgr_is_buffer_referenced(struct pb_buffer *_buf, return FALSE; } - void radeon_drm_bufmgr_flush_maps(struct pb_manager *_mgr) { struct radeon_drm_bufmgr *mgr = radeon_drm_bufmgr(_mgr); struct radeon_drm_buffer *rpb, *t_rpb; + pipe_mutex_lock(mgr->buffer_map_list_mutex); + foreach_s(rpb, t_rpb, &mgr->buffer_map_list) { radeon_bo_unmap(rpb->bo); rpb->bo->ptr = NULL; @@ -415,4 +546,14 @@ void radeon_drm_bufmgr_flush_maps(struct pb_manager *_mgr) } make_empty_list(&mgr->buffer_map_list); + + pipe_mutex_unlock(mgr->buffer_map_list_mutex); +} + +void radeon_drm_bufmgr_wait(struct r300_winsys_screen *ws, + struct r300_winsys_buffer *_buf) +{ + struct radeon_drm_buffer *buf = get_drm_buffer(radeon_pb_buffer(_buf)); + + radeon_bo_wait(buf->bo); } diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_public.h b/src/gallium/winsys/radeon/drm/radeon_drm_public.h new file mode 100644 index 00000000000..0d96ae8c470 --- /dev/null +++ b/src/gallium/winsys/radeon/drm/radeon_drm_public.h @@ -0,0 +1,9 @@ + +#ifndef RADEON_DRM_PUBLIC_H +#define RADEON_DRM_PUBLIC_H + +struct r300_winsys_screen; + +struct r300_winsys_screen *r300_drm_winsys_screen_create(int drmFD); + +#endif diff --git a/src/gallium/winsys/radeon/drm/radeon_r300.c b/src/gallium/winsys/radeon/drm/radeon_r300.c index 80923de9373..420522f5c1f 100644 --- a/src/gallium/winsys/radeon/drm/radeon_r300.c +++ b/src/gallium/winsys/radeon/drm/radeon_r300.c @@ -25,30 +25,69 @@ #include "radeon_bo_gem.h" #include "radeon_cs_gem.h" -#include "state_tracker/drm_api.h" +#include "state_tracker/drm_driver.h" + +#include "util/u_memory.h" + +static unsigned get_pb_usage_from_create_flags(unsigned bind, unsigned usage, + enum r300_buffer_domain domain) +{ + unsigned res = 0; + + if (bind & (PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET | + PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT)) + res |= PB_USAGE_GPU_WRITE; + + if (bind & PIPE_BIND_SAMPLER_VIEW) + res |= PB_USAGE_GPU_READ | PB_USAGE_GPU_WRITE; + + if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) + res |= PB_USAGE_GPU_READ; + + if (bind & PIPE_BIND_TRANSFER_WRITE) + res |= PB_USAGE_CPU_WRITE; + + if (bind & PIPE_BIND_TRANSFER_READ) + res |= PB_USAGE_CPU_READ; + + /* Is usage of any use for us? Probably not. */ + + /* Now add driver-specific usage flags. */ + if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) + res |= RADEON_PB_USAGE_VERTEX; + + if (domain & R300_DOMAIN_GTT) + res |= RADEON_PB_USAGE_DOMAIN_GTT; + + if (domain & R300_DOMAIN_VRAM) + res |= RADEON_PB_USAGE_DOMAIN_VRAM; + + return res; +} static struct r300_winsys_buffer * radeon_r300_winsys_buffer_create(struct r300_winsys_screen *rws, - unsigned alignment, - unsigned usage, - unsigned size) + unsigned size, + unsigned alignment, + unsigned bind, + unsigned usage, + enum r300_buffer_domain domain) { - struct radeon_libdrm_winsys *ws = radeon_winsys_screen(rws); + struct radeon_libdrm_winsys *ws = radeon_libdrm_winsys(rws); struct pb_desc desc; struct pb_manager *provider; struct pb_buffer *buffer; memset(&desc, 0, sizeof(desc)); desc.alignment = alignment; - desc.usage = usage; + desc.usage = get_pb_usage_from_create_flags(bind, usage, domain); - if (usage & PIPE_BIND_CONSTANT_BUFFER) - provider = ws->mman; - else if ((usage & PIPE_BIND_VERTEX_BUFFER) || - (usage & PIPE_BIND_INDEX_BUFFER)) + /* Assign a buffer manager. */ + if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) provider = ws->cman; else provider = ws->kman; + buffer = provider->create_buffer(provider, size, &desc); if (!buffer) return NULL; @@ -56,48 +95,6 @@ radeon_r300_winsys_buffer_create(struct r300_winsys_screen *rws, return radeon_libdrm_winsys_buffer(buffer); } -static void radeon_r300_winsys_buffer_destroy(struct r300_winsys_buffer *buf) -{ - struct pb_buffer *_buf = radeon_pb_buffer(buf); - - pb_destroy(_buf); -} -static void radeon_r300_winsys_buffer_set_tiling(struct r300_winsys_screen *rws, - struct r300_winsys_buffer *buf, - uint32_t pitch, - enum r300_buffer_tiling microtiled, - enum r300_buffer_tiling macrotiled) -{ - struct pb_buffer *_buf = radeon_pb_buffer(buf); - radeon_drm_bufmgr_set_tiling(_buf, microtiled, macrotiled, pitch); -} - -static void radeon_r300_winsys_buffer_get_tiling(struct r300_winsys_screen *rws, - struct r300_winsys_buffer *buf, - enum r300_buffer_tiling *microtiled, - enum r300_buffer_tiling *macrotiled) -{ - struct pb_buffer *_buf = radeon_pb_buffer(buf); - radeon_drm_bufmgr_get_tiling(_buf, microtiled, macrotiled); -} - -static void *radeon_r300_winsys_buffer_map(struct r300_winsys_screen *ws, - struct r300_winsys_buffer *buf, - unsigned usage) -{ - struct pb_buffer *_buf = radeon_pb_buffer(buf); - - return pb_map(_buf, usage); -} - -static void radeon_r300_winsys_buffer_unmap(struct r300_winsys_screen *ws, - struct r300_winsys_buffer *buf) -{ - struct pb_buffer *_buf = radeon_pb_buffer(buf); - - pb_unmap(_buf); -} - static void radeon_r300_winsys_buffer_reference(struct r300_winsys_screen *rws, struct r300_winsys_buffer **pdst, struct r300_winsys_buffer *src) @@ -110,156 +107,96 @@ static void radeon_r300_winsys_buffer_reference(struct r300_winsys_screen *rws, *pdst = radeon_libdrm_winsys_buffer(_dst); } -static boolean radeon_r300_winsys_is_buffer_referenced(struct r300_winsys_screen *rws, - struct r300_winsys_buffer *buf, - enum r300_reference_domain domain) -{ - struct pb_buffer *_buf = radeon_pb_buffer(buf); - - return radeon_drm_bufmgr_is_buffer_referenced(_buf, domain); -} - static struct r300_winsys_buffer *radeon_r300_winsys_buffer_from_handle(struct r300_winsys_screen *rws, - struct pipe_screen *screen, - struct winsys_handle *whandle, - unsigned *stride) + struct winsys_handle *whandle, + unsigned *stride, + unsigned *size) { - struct radeon_libdrm_winsys *ws = radeon_winsys_screen(rws); + struct radeon_libdrm_winsys *ws = radeon_libdrm_winsys(rws); struct pb_buffer *_buf; _buf = radeon_drm_bufmgr_create_buffer_from_handle(ws->kman, whandle->handle); - *stride = whandle->stride; + + if (stride) + *stride = whandle->stride; + if (size) + *size = _buf->base.size; + return radeon_libdrm_winsys_buffer(_buf); } static boolean radeon_r300_winsys_buffer_get_handle(struct r300_winsys_screen *rws, struct r300_winsys_buffer *buffer, - unsigned stride, - struct winsys_handle *whandle) + unsigned stride, + struct winsys_handle *whandle) { struct pb_buffer *_buf = radeon_pb_buffer(buffer); - boolean ret; - ret = radeon_drm_bufmgr_get_handle(_buf, whandle); - if (ret) - whandle->stride = stride; - return ret; -} - -static void radeon_set_flush_cb(struct r300_winsys_screen *rws, - void (*flush_cb)(void *), - void *data) -{ - struct radeon_libdrm_winsys *ws = radeon_winsys_screen(rws); - ws->flush_cb = flush_cb; - ws->flush_data = data; - radeon_cs_space_set_flush(ws->cs, flush_cb, data); -} - -static boolean radeon_add_buffer(struct r300_winsys_screen *rws, - struct r300_winsys_buffer *buf, - uint32_t rd, - uint32_t wd) -{ - struct pb_buffer *_buf = radeon_pb_buffer(buf); - - return radeon_drm_bufmgr_add_buffer(_buf, rd, wd); + whandle->stride = stride; + return radeon_drm_bufmgr_get_handle(_buf, whandle); } -static boolean radeon_validate(struct r300_winsys_screen *rws) +static void radeon_r300_winsys_cs_set_flush(struct r300_winsys_cs *rcs, + void (*flush)(void *), + void *user) { - struct radeon_libdrm_winsys *ws = radeon_winsys_screen(rws); - if (radeon_cs_space_check(ws->cs) < 0) { - return FALSE; - } - - /* Things are fine, we can proceed as normal. */ - return TRUE; -} - -static boolean radeon_check_cs(struct r300_winsys_screen *rws, int size) -{ - struct radeon_libdrm_winsys *ws = radeon_winsys_screen(rws); - struct radeon_cs *cs = ws->cs; - - return radeon_validate(rws) && cs->cdw + size <= cs->ndw; -} - -static void radeon_begin_cs(struct r300_winsys_screen *rws, - int size, - const char* file, - const char* function, - int line) -{ - struct radeon_libdrm_winsys *ws = radeon_winsys_screen(rws); - radeon_cs_begin(ws->cs, size, file, function, line); -} - -static void radeon_write_cs_dword(struct r300_winsys_screen *rws, - uint32_t dword) -{ - struct radeon_libdrm_winsys *ws = radeon_winsys_screen(rws); - radeon_cs_write_dword(ws->cs, dword); + struct radeon_libdrm_cs *cs = radeon_libdrm_cs(rcs); + cs->flush_cs = flush; + cs->flush_data = user; + radeon_cs_space_set_flush(cs->cs, flush, user); } -static void radeon_write_cs_table(struct r300_winsys_screen *rws, - const void *table, unsigned count) +static boolean radeon_r300_winsys_cs_validate(struct r300_winsys_cs *rcs) { - struct radeon_libdrm_winsys *ws = radeon_winsys_screen(rws); - radeon_cs_write_table(ws->cs, table, count); -} + struct radeon_libdrm_cs *cs = radeon_libdrm_cs(rcs); -static void radeon_write_cs_reloc(struct r300_winsys_screen *rws, - struct r300_winsys_buffer *buf, - uint32_t rd, - uint32_t wd, - uint32_t flags) -{ - struct pb_buffer *_buf = radeon_pb_buffer(buf); - radeon_drm_bufmgr_write_reloc(_buf, rd, wd, flags); + return radeon_cs_space_check(cs->cs) >= 0; } -static void radeon_reset_bos(struct r300_winsys_screen *rws) +static void radeon_r300_winsys_cs_reset_buffers(struct r300_winsys_cs *rcs) { - struct radeon_libdrm_winsys *ws = radeon_winsys_screen(rws); - radeon_cs_space_reset_bos(ws->cs); + struct radeon_libdrm_cs *cs = radeon_libdrm_cs(rcs); + radeon_cs_space_reset_bos(cs->cs); } -static void radeon_end_cs(struct r300_winsys_screen *rws, - const char* file, - const char* function, - int line) +static void radeon_r300_winsys_cs_flush(struct r300_winsys_cs *rcs) { - struct radeon_libdrm_winsys *ws = radeon_winsys_screen(rws); - radeon_cs_end(ws->cs, file, function, line); -} - -static void radeon_flush_cs(struct r300_winsys_screen *rws) -{ - struct radeon_libdrm_winsys *ws = radeon_winsys_screen(rws); + struct radeon_libdrm_cs *cs = radeon_libdrm_cs(rcs); int retval; /* Don't flush a zero-sized CS. */ - if (!ws->cs->cdw) { + if (!cs->base.cdw) { return; } - radeon_drm_bufmgr_flush_maps(ws->kman); + cs->cs->cdw = cs->base.cdw; + + radeon_drm_bufmgr_flush_maps(cs->ws->kman); + /* Emit the CS. */ - retval = radeon_cs_emit(ws->cs); + retval = radeon_cs_emit(cs->cs); if (retval) { - debug_printf("radeon: Bad CS, dumping...\n"); - radeon_cs_print(ws->cs, stderr); + if (debug_get_bool_option("RADEON_DUMP_CS", FALSE)) { + fprintf(stderr, "radeon: The kernel rejected CS, dumping...\n"); + radeon_cs_print(cs->cs, stderr); + } else { + fprintf(stderr, "radeon: The kernel rejected CS, " + "see dmesg for more information.\n"); + } } /* Reset CS. * Someday, when we care about performance, we should really find a way * to rotate between two or three CS objects so that the GPU can be * spinning through one CS while another one is being filled. */ - radeon_cs_erase(ws->cs); + radeon_cs_erase(cs->cs); + + cs->base.ptr = cs->cs->packets; + cs->base.cdw = cs->cs->cdw; + cs->base.ndw = cs->cs->ndw; } static uint32_t radeon_get_value(struct r300_winsys_screen *rws, - enum r300_value_id id) + enum r300_value_id id) { struct radeon_libdrm_winsys *ws = (struct radeon_libdrm_winsys *)rws; @@ -274,28 +211,63 @@ static uint32_t radeon_get_value(struct r300_winsys_screen *rws, return ws->squaretiling; case R300_VID_DRM_2_3_0: return ws->drm_2_3_0; + case R300_VID_DRM_2_6_0: + return ws->drm_2_6_0; + case R300_CAN_HYPERZ: + return ws->hyperz; } return 0; } -static void -radeon_winsys_destroy(struct r300_winsys_screen *rws) +static struct r300_winsys_cs *radeon_r300_winsys_cs_create(struct r300_winsys_screen *rws) +{ + struct radeon_libdrm_winsys *ws = radeon_libdrm_winsys(rws); + struct radeon_libdrm_cs *cs = CALLOC_STRUCT(radeon_libdrm_cs); + + if (!cs) + return NULL; + + /* Size limit on IBs is 64 kibibytes. */ + cs->cs = radeon_cs_create(ws->csm, 1024 * 64 / 4); + if (!cs->cs) { + FREE(cs); + return NULL; + } + + radeon_cs_set_limit(cs->cs, + RADEON_GEM_DOMAIN_GTT, ws->gart_size); + radeon_cs_set_limit(cs->cs, + RADEON_GEM_DOMAIN_VRAM, ws->vram_size); + + cs->ws = ws; + cs->base.ptr = cs->cs->packets; + cs->base.cdw = cs->cs->cdw; + cs->base.ndw = cs->cs->ndw; + return &cs->base; +} + +static void radeon_r300_winsys_cs_destroy(struct r300_winsys_cs *rcs) +{ + struct radeon_libdrm_cs *cs = radeon_libdrm_cs(rcs); + radeon_cs_destroy(cs->cs); + FREE(cs); +} + +static void radeon_winsys_destroy(struct r300_winsys_screen *rws) { struct radeon_libdrm_winsys *ws = (struct radeon_libdrm_winsys *)rws; - radeon_cs_destroy(ws->cs); ws->cman->destroy(ws->cman); ws->kman->destroy(ws->kman); - ws->mman->destroy(ws->mman); radeon_bo_manager_gem_dtor(ws->bom); radeon_cs_manager_gem_dtor(ws->csm); + + FREE(rws); } -boolean -radeon_setup_winsys(int fd, struct radeon_libdrm_winsys* ws) +boolean radeon_setup_winsys(int fd, struct radeon_libdrm_winsys* ws) { - ws->csm = radeon_cs_manager_gem_ctor(fd); if (!ws->csm) goto fail; @@ -310,43 +282,28 @@ radeon_setup_winsys(int fd, struct radeon_libdrm_winsys* ws) if (!ws->cman) goto fail; - ws->mman = pb_malloc_bufmgr_create(); - if (!ws->mman) - goto fail; - - /* Size limit on IBs is 64 kibibytes. */ - ws->cs = radeon_cs_create(ws->csm, 1024 * 64 / 4); - if (!ws->cs) - goto fail; - radeon_cs_set_limit(ws->cs, - RADEON_GEM_DOMAIN_GTT, ws->gart_size); - radeon_cs_set_limit(ws->cs, - RADEON_GEM_DOMAIN_VRAM, ws->vram_size); - - ws->base.add_buffer = radeon_add_buffer; - ws->base.validate = radeon_validate; ws->base.destroy = radeon_winsys_destroy; - ws->base.check_cs = radeon_check_cs; - ws->base.begin_cs = radeon_begin_cs; - ws->base.write_cs_dword = radeon_write_cs_dword; - ws->base.write_cs_table = radeon_write_cs_table; - ws->base.write_cs_reloc = radeon_write_cs_reloc; - ws->base.end_cs = radeon_end_cs; - ws->base.flush_cs = radeon_flush_cs; - ws->base.reset_bos = radeon_reset_bos; - ws->base.set_flush_cb = radeon_set_flush_cb; ws->base.get_value = radeon_get_value; ws->base.buffer_create = radeon_r300_winsys_buffer_create; - ws->base.buffer_destroy = radeon_r300_winsys_buffer_destroy; - ws->base.buffer_set_tiling = radeon_r300_winsys_buffer_set_tiling; - ws->base.buffer_get_tiling = radeon_r300_winsys_buffer_get_tiling; - ws->base.buffer_map = radeon_r300_winsys_buffer_map; - ws->base.buffer_unmap = radeon_r300_winsys_buffer_unmap; + ws->base.buffer_set_tiling = radeon_drm_bufmgr_set_tiling; + ws->base.buffer_get_tiling = radeon_drm_bufmgr_get_tiling; + ws->base.buffer_map = radeon_drm_buffer_map; + ws->base.buffer_unmap = radeon_drm_buffer_unmap; + ws->base.buffer_wait = radeon_drm_bufmgr_wait; ws->base.buffer_reference = radeon_r300_winsys_buffer_reference; ws->base.buffer_from_handle = radeon_r300_winsys_buffer_from_handle; ws->base.buffer_get_handle = radeon_r300_winsys_buffer_get_handle; - ws->base.is_buffer_referenced = radeon_r300_winsys_is_buffer_referenced; + + ws->base.cs_create = radeon_r300_winsys_cs_create; + ws->base.cs_destroy = radeon_r300_winsys_cs_destroy; + ws->base.cs_add_buffer = radeon_drm_bufmgr_add_buffer; + ws->base.cs_validate = radeon_r300_winsys_cs_validate; + ws->base.cs_write_reloc = radeon_drm_bufmgr_write_reloc; + ws->base.cs_flush = radeon_r300_winsys_cs_flush; + ws->base.cs_reset_buffers = radeon_r300_winsys_cs_reset_buffers; + ws->base.cs_set_flush = radeon_r300_winsys_cs_set_flush; + ws->base.cs_is_buffer_referenced = radeon_drm_bufmgr_is_buffer_referenced; return TRUE; fail: @@ -360,10 +317,6 @@ fail: ws->cman->destroy(ws->cman); if (ws->kman) ws->kman->destroy(ws->kman); - if (ws->mman) - ws->mman->destroy(ws->mman); - if (ws->cs) - radeon_cs_destroy(ws->cs); return FALSE; } diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h index ca789be8e93..6f4aa4bce30 100644 --- a/src/gallium/winsys/radeon/drm/radeon_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h @@ -40,8 +40,6 @@ struct radeon_libdrm_winsys { struct pb_manager *cman; - struct pb_manager *mman; - /* PCI ID */ uint32_t pci_id; @@ -67,6 +65,15 @@ struct radeon_libdrm_winsys { */ boolean drm_2_3_0; + /* DRM 2.6.0 + * - Hyper-Z + * - GB_Z_PEQ_CONFIG allowed on rv350->r4xx, we should initialize it + */ + boolean drm_2_6_0; + + /* hyperz user */ + boolean hyperz; + /* DRM FD */ int fd; @@ -75,19 +82,32 @@ struct radeon_libdrm_winsys { /* Radeon CS manager. */ struct radeon_cs_manager *csm; +}; - /* Current CS. */ +struct radeon_libdrm_cs { + struct r300_winsys_cs base; + + /* The winsys. */ + struct radeon_libdrm_winsys *ws; + + /* The libdrm command stream. */ struct radeon_cs *cs; - /* Flush CB */ - void (*flush_cb)(void *); + /* Flush CS. */ + void (*flush_cs)(void *); void *flush_data; }; +static INLINE struct radeon_libdrm_cs * +radeon_libdrm_cs(struct r300_winsys_cs *base) +{ + return (struct radeon_libdrm_cs*)base; +} + static INLINE struct radeon_libdrm_winsys * -radeon_winsys_screen(struct r300_winsys_screen *base) +radeon_libdrm_winsys(struct r300_winsys_screen *base) { - return (struct radeon_libdrm_winsys *)base; + return (struct radeon_libdrm_winsys*)base; } #endif diff --git a/src/gallium/winsys/svga/drm/SConscript b/src/gallium/winsys/svga/drm/SConscript index edaf9458bee..3ad4c725727 100644 --- a/src/gallium/winsys/svga/drm/SConscript +++ b/src/gallium/winsys/svga/drm/SConscript @@ -2,6 +2,8 @@ Import('*') env = env.Clone() +env.ParseConfig('pkg-config --cflags libdrm') + if env['gcc']: env.Append(CCFLAGS = ['-fvisibility=hidden']) env.Append(CPPDEFINES = [ diff --git a/src/gallium/winsys/sw/drm/sw_drm_api.h b/src/gallium/winsys/svga/drm/svga_drm_public.h index ce90a04ae0c..e98c89da1e1 100644 --- a/src/gallium/winsys/sw/drm/sw_drm_api.h +++ b/src/gallium/winsys/svga/drm/svga_drm_public.h @@ -23,12 +23,19 @@ * **********************************************************/ +/** + * @file + * VMware SVGA DRM winsys public interface. Used by targets to create a stack. + * + * @author Jakob Bornecrantz Fonseca <[email protected]> + */ -#ifndef SW_DRM_API_H -#define SW_DRM_API_H +#ifndef SVGA_DRM_PUBLIC_H_ +#define SVGA_DRM_PUBLIC_H_ -struct drm_api; +struct svga_winsys_screen; -struct drm_api * sw_drm_api_create(struct drm_api *api); +struct svga_winsys_screen * +svga_drm_winsys_screen_create(int fd); -#endif +#endif /* SVGA_PUBLIC_H_ */ diff --git a/src/gallium/winsys/svga/drm/vmw_context.c b/src/gallium/winsys/svga/drm/vmw_context.c index 104d03f2730..11626ee637d 100644 --- a/src/gallium/winsys/svga/drm/vmw_context.c +++ b/src/gallium/winsys/svga/drm/vmw_context.c @@ -103,6 +103,9 @@ struct vmw_svga_winsys_context * referred. */ boolean preemptive_flush; + + boolean throttle_set; + uint32_t throttle_us; }; @@ -135,6 +138,7 @@ vmw_swc_flush(struct svga_winsys_context *swc, struct pipe_fence_handle *fence = NULL; unsigned i; enum pipe_error ret; + uint32_t throttle_us; ret = pb_validate_validate(vswc->validate); assert(ret == PIPE_OK); @@ -153,8 +157,13 @@ vmw_swc_flush(struct svga_winsys_context *swc, *reloc->where = ptr; } + throttle_us = vswc->throttle_set ? + vswc->throttle_us : vswc->vws->default_throttle_us; + if (vswc->command.used) vmw_ioctl_command(vswc->vws, + vswc->base.cid, + throttle_us, vswc->command.buffer, vswc->command.used, &vswc->last_fence); @@ -395,3 +404,13 @@ vmw_svga_winsys_context_create(struct svga_winsys_screen *sws) } +void +vmw_svga_context_set_throttling(struct pipe_context *pipe, + uint32_t throttle_us) +{ + struct svga_winsys_context *swc = svga_winsys_context(pipe); + struct vmw_svga_winsys_context *vswc = vmw_svga_winsys_context(swc); + + vswc->throttle_us = throttle_us; + vswc->throttle_set = TRUE; +} diff --git a/src/gallium/winsys/svga/drm/vmw_context.h b/src/gallium/winsys/svga/drm/vmw_context.h index d4884d24e99..aed8b93734b 100644 --- a/src/gallium/winsys/svga/drm/vmw_context.h +++ b/src/gallium/winsys/svga/drm/vmw_context.h @@ -52,5 +52,8 @@ struct pipe_screen; struct svga_winsys_context * vmw_svga_winsys_context_create(struct svga_winsys_screen *sws); +void +vmw_svga_context_set_throttling(struct pipe_context *pipe, + uint32_t throttle_us); #endif /* VMW_CONTEXT_H_ */ diff --git a/src/gallium/winsys/svga/drm/vmw_screen.c b/src/gallium/winsys/svga/drm/vmw_screen.c index 6cc9b382932..51a4c55e5a2 100644 --- a/src/gallium/winsys/svga/drm/vmw_screen.c +++ b/src/gallium/winsys/svga/drm/vmw_screen.c @@ -75,3 +75,13 @@ vmw_winsys_destroy(struct vmw_winsys_screen *vws) vmw_ioctl_cleanup(vws); FREE(vws); } + +void +vmw_winsys_screen_set_throttling(struct pipe_screen *screen, + uint32_t throttle_us) +{ + struct vmw_winsys_screen *vws = + vmw_winsys_screen(svga_winsys_screen(screen)); + + vws->default_throttle_us = throttle_us; +} diff --git a/src/gallium/winsys/svga/drm/vmw_screen.h b/src/gallium/winsys/svga/drm/vmw_screen.h index d3f2c2c7f56..b3de72df881 100644 --- a/src/gallium/winsys/svga/drm/vmw_screen.h +++ b/src/gallium/winsys/svga/drm/vmw_screen.h @@ -53,6 +53,7 @@ struct vmw_winsys_screen struct svga_winsys_screen base; boolean use_old_scanout_flag; + uint32_t default_throttle_us; struct { volatile uint32_t *fifo_map; @@ -96,9 +97,11 @@ vmw_ioctl_surface_destroy(struct vmw_winsys_screen *vws, void vmw_ioctl_command(struct vmw_winsys_screen *vws, - void *commands, - uint32_t size, - uint32_t *fence); + int32_t cid, + uint32_t throttle_us, + void *commands, + uint32_t size, + uint32_t *fence); struct vmw_region * vmw_ioctl_region_create(struct vmw_winsys_screen *vws, uint32_t size); @@ -135,6 +138,7 @@ void vmw_pools_cleanup(struct vmw_winsys_screen *vws); struct vmw_winsys_screen *vmw_winsys_create(int fd, boolean use_old_scanout_flag); void vmw_winsys_destroy(struct vmw_winsys_screen *sws); - +void vmw_winsys_screen_set_throttling(struct pipe_screen *screen, + uint32_t throttle_us); #endif /* VMW_SCREEN_H_ */ diff --git a/src/gallium/winsys/svga/drm/vmw_screen_dri.c b/src/gallium/winsys/svga/drm/vmw_screen_dri.c index f4c1642f2d4..258084a1f10 100644 --- a/src/gallium/winsys/svga/drm/vmw_screen_dri.c +++ b/src/gallium/winsys/svga/drm/vmw_screen_dri.c @@ -30,20 +30,22 @@ #include "util/u_format.h" #include "vmw_screen.h" -#include "trace/tr_drm.h" - -#include "vmw_screen.h" #include "vmw_surface.h" -#include "vmw_fence.h" -#include "vmw_context.h" +#include "svga_drm_public.h" + +#include "state_tracker/drm_driver.h" -#include <state_tracker/dri1_api.h> -#include <state_tracker/drm_api.h> #include "vmwgfx_drm.h" #include <xf86drm.h> #include <stdio.h> +struct dri1_api_version { + int major; + int minor; + int patch_level; +}; + static struct svga_winsys_surface * vmw_drm_surface_from_handle(struct svga_winsys_screen *sws, struct winsys_handle *whandle, @@ -54,11 +56,6 @@ vmw_drm_surface_get_handle(struct svga_winsys_screen *sws, unsigned stride, struct winsys_handle *whandle); -static struct dri1_api dri1_api_hooks; -static struct dri1_api_version ddx_required = { 0, 1, 0 }; -static struct dri1_api_version ddx_compat = { 0, 0, 0 }; -static struct dri1_api_version dri_required = { 4, 0, 0 }; -static struct dri1_api_version dri_compat = { 4, 0, 0 }; static struct dri1_api_version drm_required = { 1, 0, 0 }; static struct dri1_api_version drm_compat = { 1, 0, 0 }; static struct dri1_api_version drm_scanout = { 0, 9, 0 }; @@ -84,71 +81,34 @@ vmw_dri1_check_version(const struct dri1_api_version *cur, return FALSE; } -/* This is actually the entrypoint to the entire driver, called by the - * libGL (or EGL, or ...) code via the drm_api_hooks table at the - * bottom of the file. +/* This is actually the entrypoint to the entire driver, + * called by the target bootstrap code. */ -static struct pipe_screen * -vmw_drm_create_screen(struct drm_api *drm_api, - int fd, - struct drm_create_screen_arg *arg) +struct svga_winsys_screen * +svga_drm_winsys_screen_create(int fd) { struct vmw_winsys_screen *vws; - struct pipe_screen *screen; - struct dri1_create_screen_arg *dri1; boolean use_old_scanout_flag = FALSE; - if (!arg || arg->mode == DRM_CREATE_NORMAL) { - struct dri1_api_version drm_ver; - drmVersionPtr ver; - - ver = drmGetVersion(fd); - if (ver == NULL) - return NULL; + struct dri1_api_version drm_ver; + drmVersionPtr ver; - drm_ver.major = ver->version_major; - drm_ver.minor = ver->version_minor; - drm_ver.patch_level = 0; /* ??? */ + ver = drmGetVersion(fd); + if (ver == NULL) + return NULL; - drmFreeVersion(ver); - if (!vmw_dri1_check_version(&drm_ver, &drm_required, - &drm_compat, "vmwgfx drm driver")) - return NULL; + drm_ver.major = ver->version_major; + drm_ver.minor = ver->version_minor; + drm_ver.patch_level = 0; /* ??? */ - if (!vmw_dri1_check_version(&drm_ver, &drm_scanout, - &drm_compat, "use old scanout field (not a error)")) - use_old_scanout_flag = TRUE; - } + drmFreeVersion(ver); + if (!vmw_dri1_check_version(&drm_ver, &drm_required, + &drm_compat, "vmwgfx drm driver")) + return NULL; - if (arg != NULL) { - switch (arg->mode) { - case DRM_CREATE_NORMAL: - break; - case DRM_CREATE_DRI1: - dri1 = (struct dri1_create_screen_arg *)arg; - if (!vmw_dri1_check_version(&dri1->ddx_version, &ddx_required, - &ddx_compat, "ddx - driver api")) - return NULL; - if (!vmw_dri1_check_version(&dri1->dri_version, &dri_required, - &dri_compat, "dri info")) - return NULL; - if (!vmw_dri1_check_version(&dri1->drm_version, &drm_required, - &drm_compat, "vmwgfx drm driver")) - return NULL; - if (!vmw_dri1_check_version(&dri1->drm_version, &drm_scanout, - &drm_compat, "use old scanout field (not a error)")) - use_old_scanout_flag = TRUE; - dri1->api = &dri1_api_hooks; -#if 0 - break; -#else - assert(!"No dri 1 support for now\n"); - return NULL; -#endif - default: - return NULL; - } - } + if (!vmw_dri1_check_version(&drm_ver, &drm_scanout, + &drm_compat, "use old scanout field (not a error)")) + use_old_scanout_flag = TRUE; vws = vmw_winsys_create( fd, use_old_scanout_flag ); if (!vws) @@ -158,16 +118,7 @@ vmw_drm_create_screen(struct drm_api *drm_api, vws->base.surface_from_handle = vmw_drm_surface_from_handle; vws->base.surface_get_handle = vmw_drm_surface_get_handle; - screen = svga_screen_create( &vws->base ); - if (!screen) - goto out_no_screen; - - return screen; - - /* Failure cases: - */ -out_no_screen: - vmw_winsys_destroy( vws ); + return &vws->base; out_no_vws: return NULL; @@ -205,72 +156,6 @@ vmw_dri1_intersect_src_bbox(struct drm_clip_rect *dst, return TRUE; } -/** - * No fancy get-surface-from-sarea stuff here. - * Just use the present blit. - */ - -static void -vmw_dri1_present_locked(struct pipe_context *locked_pipe, - struct pipe_surface *surf, - const struct drm_clip_rect *rect, - unsigned int num_clip, - int x_draw, int y_draw, - const struct drm_clip_rect *bbox, - struct pipe_fence_handle **p_fence) -{ -#if 0 - struct svga_winsys_surface *srf = - svga_screen_texture_get_winsys_surface(surf->texture); - struct vmw_svga_winsys_surface *vsrf = vmw_svga_winsys_surface(srf); - struct vmw_winsys_screen *vws = - vmw_winsys_screen(svga_winsys_screen(locked_pipe->screen)); - struct drm_clip_rect clip; - int i; - struct - { - SVGA3dCmdHeader header; - SVGA3dCmdPresent body; - SVGA3dCopyRect rect; - } cmd; - boolean visible = FALSE; - uint32_t fence_seq = 0; - - VMW_FUNC; - cmd.header.id = SVGA_3D_CMD_PRESENT; - cmd.header.size = sizeof cmd.body + sizeof cmd.rect; - cmd.body.sid = vsrf->sid; - - for (i = 0; i < num_clip; ++i) { - if (!vmw_dri1_intersect_src_bbox(&clip, x_draw, y_draw, rect++, bbox)) - continue; - - cmd.rect.x = clip.x1; - cmd.rect.y = clip.y1; - cmd.rect.w = clip.x2 - clip.x1; - cmd.rect.h = clip.y2 - clip.y1; - cmd.rect.srcx = (int)clip.x1 - x_draw; - cmd.rect.srcy = (int)clip.y1 - y_draw; - - vmw_printf("%s: Clip %d x %d y %d w %d h %d srcx %d srcy %d\n", - __FUNCTION__, - i, - cmd.rect.x, - cmd.rect.y, - cmd.rect.w, cmd.rect.h, cmd.rect.srcx, cmd.rect.srcy); - - vmw_ioctl_command(vws, &cmd, sizeof cmd.header + cmd.header.size, - &fence_seq); - visible = TRUE; - } - - *p_fence = (visible) ? vmw_pipe_fence(fence_seq) : NULL; - vmw_svga_winsys_surface_reference(&vsrf, NULL); -#else - assert(!"No dri 1 support for now\n"); -#endif -} - static struct svga_winsys_surface * vmw_drm_surface_from_handle(struct svga_winsys_screen *sws, struct winsys_handle *whandle, @@ -317,7 +202,7 @@ vmw_drm_surface_from_handle(struct svga_winsys_screen *sws, whandle->handle, i); goto out_mip; } - } + } vsrf = CALLOC_STRUCT(vmw_svga_winsys_surface); if (!vsrf) @@ -354,21 +239,3 @@ vmw_drm_surface_get_handle(struct svga_winsys_screen *sws, return TRUE; } - - -static struct dri1_api dri1_api_hooks = { - .front_srf_locked = NULL, - .present_locked = vmw_dri1_present_locked -}; - -static struct drm_api vmw_drm_api_hooks = { - .name = "vmwgfx", - .driver_name = "vmwgfx", - .create_screen = vmw_drm_create_screen, - .destroy = NULL, -}; - -struct drm_api* drm_api_create() -{ - return trace_drm_create(&vmw_drm_api_hooks); -} diff --git a/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c b/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c index 5d81fa8c4a6..d92ba389d35 100644 --- a/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c +++ b/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c @@ -241,8 +241,9 @@ vmw_ioctl_surface_destroy(struct vmw_winsys_screen *vws, uint32 sid) } void -vmw_ioctl_command(struct vmw_winsys_screen *vws, void *commands, uint32_t size, - uint32_t * pfence) +vmw_ioctl_command(struct vmw_winsys_screen *vws, int32_t cid, + uint32_t throttle_us, void *commands, uint32_t size, + uint32_t *pfence) { struct drm_vmw_execbuf_arg arg; struct drm_vmw_fence_rep rep; @@ -275,6 +276,7 @@ vmw_ioctl_command(struct vmw_winsys_screen *vws, void *commands, uint32_t size, arg.fence_rep = (unsigned long)&rep; arg.commands = (unsigned long)commands; arg.command_size = size; + arg.throttle_us = throttle_us; do { ret = drmCommandWrite(vws->ioctl.drm_fd, DRM_VMW_EXECBUF, &arg, sizeof(arg)); diff --git a/src/gallium/winsys/svga/drm/vmw_screen_svga.c b/src/gallium/winsys/svga/drm/vmw_screen_svga.c index 2b4e80f0039..d96b2b97427 100644 --- a/src/gallium/winsys/svga/drm/vmw_screen_svga.c +++ b/src/gallium/winsys/svga/drm/vmw_screen_svga.c @@ -81,7 +81,7 @@ vmw_svga_winsys_buffer_map(struct svga_winsys_screen *sws, unsigned flags) { (void)sws; - return pb_map(vmw_pb_buffer(buf), flags); + return pb_map(vmw_pb_buffer(buf), flags, NULL); } diff --git a/src/gallium/winsys/svga/drm/vmwgfx_drm.h b/src/gallium/winsys/svga/drm/vmwgfx_drm.h index 47914bdb711..2f2807df0b2 100644 --- a/src/gallium/winsys/svga/drm/vmwgfx_drm.h +++ b/src/gallium/winsys/svga/drm/vmwgfx_drm.h @@ -50,6 +50,8 @@ #define DRM_VMW_EXECBUF 12 #define DRM_VMW_FIFO_DEBUG 13 #define DRM_VMW_FENCE_WAIT 14 +/* guarded by minor version >= 2 */ +#define DRM_VMW_UPDATE_LAYOUT 15 /*************************************************************************/ @@ -70,6 +72,7 @@ #define DRM_VMW_PARAM_FIFO_OFFSET 3 #define DRM_VMW_PARAM_HW_CAPS 4 #define DRM_VMW_PARAM_FIFO_CAPS 5 +#define DRM_VMW_PARAM_MAX_FB_SIZE 6 /** * struct drm_vmw_getparam_arg @@ -542,4 +545,28 @@ struct drm_vmw_stream_arg { * sure that the stream has been stopped. */ +/*************************************************************************/ +/** + * DRM_VMW_UPDATE_LAYOUT - Update layout + * + * Updates the prefered modes and connection status for connectors. The + * command conisits of one drm_vmw_update_layout_arg pointing out a array + * of num_outputs drm_vmw_rect's. + */ + +/** + * struct drm_vmw_update_layout_arg + * + * @num_outputs: number of active + * @rects: pointer to array of drm_vmw_rect + * + * Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl. + */ + +struct drm_vmw_update_layout_arg { + uint32_t num_outputs; + uint32_t pad64; + uint64_t rects; +}; + #endif diff --git a/src/gallium/winsys/sw/Makefile b/src/gallium/winsys/sw/Makefile index e9182ea5b1b..094e811d57d 100644 --- a/src/gallium/winsys/sw/Makefile +++ b/src/gallium/winsys/sw/Makefile @@ -4,6 +4,16 @@ include $(TOP)/configs/current SUBDIRS = null wrapper +# TODO: this should go through a further indirection level +# (i.e. EGL should set a variable that is checked here) +ifneq ($(findstring x11, $(EGL_PLATFORMS)),) +SUBDIRS += xlib +endif + +ifneq ($(findstring fbdev, $(EGL_PLATFORMS)),) +SUBDIRS += fbdev +endif + default install clean: @for dir in $(SUBDIRS) ; do \ if [ -d $$dir ] ; then \ diff --git a/src/gallium/winsys/sw/drm/sw_drm_api.c b/src/gallium/winsys/sw/drm/sw_drm_api.c deleted file mode 100644 index 2ccde610e60..00000000000 --- a/src/gallium/winsys/sw/drm/sw_drm_api.c +++ /dev/null @@ -1,104 +0,0 @@ -/********************************************************** - * Copyright 2010 VMware, Inc. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - **********************************************************/ - - -#include "util/u_memory.h" -#include "softpipe/sp_public.h" -#include "state_tracker/drm_api.h" -#include "../../sw/wrapper/wrapper_sw_winsys.h" -#include "sw_drm_api.h" - - -/* - * Defines - */ - - -struct sw_drm_api -{ - struct drm_api base; - struct drm_api *api; - struct sw_winsys *sw; -}; - -static INLINE struct sw_drm_api * -sw_drm_api(struct drm_api *api) -{ - return (struct sw_drm_api *)api; -} - - -/* - * Exported functions - */ - - -static struct pipe_screen * -sw_drm_create_screen(struct drm_api *_api, int drmFD, - struct drm_create_screen_arg *arg) -{ - struct sw_drm_api *swapi = sw_drm_api(_api); - struct drm_api *api = swapi->api; - struct sw_winsys *sww; - struct pipe_screen *screen; - - screen = api->create_screen(api, drmFD, arg); - if (!screen) - return NULL; - - sww = wrapper_sw_winsys_warp_pipe_screen(screen); - if (!sww) - return NULL; - - return softpipe_create_screen(sww); -} - -static void -sw_drm_destroy(struct drm_api *api) -{ - struct sw_drm_api *swapi = sw_drm_api(api); - if (swapi->api->destroy) - swapi->api->destroy(swapi->api); - - FREE(swapi); -} - -struct drm_api * -sw_drm_api_create(struct drm_api *api) -{ - struct sw_drm_api *swapi = CALLOC_STRUCT(sw_drm_api); - - if (!swapi) - return api; - - swapi->base.name = api->name; - swapi->base.driver_name = api->driver_name; - swapi->base.create_screen = sw_drm_create_screen; - swapi->base.destroy = sw_drm_destroy; - - swapi->api = api; - - return &swapi->base; -} diff --git a/src/gallium/winsys/sw/drm/Makefile b/src/gallium/winsys/sw/fbdev/Makefile index 79664536aa0..8832aab1934 100644 --- a/src/gallium/winsys/sw/drm/Makefile +++ b/src/gallium/winsys/sw/fbdev/Makefile @@ -1,12 +1,13 @@ TOP = ../../../../.. include $(TOP)/configs/current -LIBNAME = swdrm - -C_SOURCES = sw_drm_api.c +LIBNAME = fbdev LIBRARY_INCLUDES = LIBRARY_DEFINES = +C_SOURCES = \ + fbdev_sw_winsys.c + include ../../../Makefile.template diff --git a/src/gallium/winsys/sw/fbdev/SConscript b/src/gallium/winsys/sw/fbdev/SConscript new file mode 100644 index 00000000000..3b5b4ff1c07 --- /dev/null +++ b/src/gallium/winsys/sw/fbdev/SConscript @@ -0,0 +1,23 @@ +####################################################################### +# SConscript for fbdev winsys + + +Import('*') + +if env['platform'] == 'linux': + + env = env.Clone() + + env.Append(CPPPATH = [ + '#/src/gallium/include', + '#/src/gallium/auxiliary', + '#/src/gallium/drivers', + ]) + + ws_fbdev = env.ConvenienceLibrary( + target = 'ws_fbdev', + source = [ + 'fbdev_sw_winsys.c', + ] + ) + Export('ws_fbdev') diff --git a/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.c b/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.c new file mode 100644 index 00000000000..f4f4cd7969b --- /dev/null +++ b/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.c @@ -0,0 +1,224 @@ +/* + * Mesa 3-D graphics library + * Version: 7.9 + * + * Copyright (C) 2010 LunarG Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Chia-I Wu <[email protected]> + */ + +#include <sys/mman.h> +#include <sys/ioctl.h> +#include <linux/fb.h> + +#include "pipe/p_compiler.h" +#include "util/u_format.h" +#include "util/u_math.h" +#include "util/u_memory.h" +#include "state_tracker/sw_winsys.h" + +#include "fbdev_sw_winsys.h" + +struct fbdev_sw_displaytarget +{ + enum pipe_format format; + unsigned width; + unsigned height; + unsigned stride; + + void *data; + void *mapped; +}; + +struct fbdev_sw_winsys +{ + struct sw_winsys base; + + int fd; + enum pipe_format format; + + struct fb_fix_screeninfo finfo; + void *fbmem; + unsigned rows; + unsigned stride; +}; + +static INLINE struct fbdev_sw_displaytarget * +fbdev_sw_displaytarget(struct sw_displaytarget *dt) +{ + return (struct fbdev_sw_displaytarget *) dt; +} + +static INLINE struct fbdev_sw_winsys * +fbdev_sw_winsys(struct sw_winsys *ws) +{ + return (struct fbdev_sw_winsys *) ws; +} + +static void +fbdev_displaytarget_display(struct sw_winsys *ws, + struct sw_displaytarget *dt, + void *context_private) +{ + struct fbdev_sw_winsys *fbdev = fbdev_sw_winsys(ws); + struct fbdev_sw_displaytarget *fbdt = fbdev_sw_displaytarget(dt); + unsigned rows, len, i; + + rows = MIN2(fbdt->height, fbdev->rows); + len = util_format_get_stride(fbdt->format, fbdt->width); + len = MIN2(len, fbdev->stride); + + for (i = 0; i < rows; i++) { + void *dst = fbdev->fbmem + fbdev->stride * i; + void *src = fbdt->data + fbdt->stride * i; + + memcpy(dst, src, len); + } +} + +static void +fbdev_displaytarget_unmap(struct sw_winsys *ws, + struct sw_displaytarget *dt) +{ + struct fbdev_sw_displaytarget *fbdt = fbdev_sw_displaytarget(dt); + fbdt->mapped = NULL; +} + +static void * +fbdev_displaytarget_map(struct sw_winsys *ws, + struct sw_displaytarget *dt, + unsigned flags) +{ + struct fbdev_sw_displaytarget *fbdt = fbdev_sw_displaytarget(dt); + fbdt->mapped = fbdt->data; + return fbdt->mapped; +} + +static void +fbdev_displaytarget_destroy(struct sw_winsys *ws, + struct sw_displaytarget *dt) +{ + struct fbdev_sw_displaytarget *fbdt = fbdev_sw_displaytarget(dt); + + if (fbdt->data) + align_free(fbdt->data); + + FREE(fbdt); +} + +static struct sw_displaytarget * +fbdev_displaytarget_create(struct sw_winsys *ws, + unsigned tex_usage, + enum pipe_format format, + unsigned width, unsigned height, + unsigned alignment, + unsigned *stride) +{ + struct fbdev_sw_winsys *fbdev = fbdev_sw_winsys(ws); + struct fbdev_sw_displaytarget *fbdt; + unsigned nblocksy, size, format_stride; + + if (fbdev->format != format) + return NULL; + + fbdt = CALLOC_STRUCT(fbdev_sw_displaytarget); + if (!fbdt) + return NULL; + + fbdt->format = format; + fbdt->width = width; + fbdt->height = height; + + format_stride = util_format_get_stride(format, width); + fbdt->stride = align(format_stride, alignment); + + nblocksy = util_format_get_nblocksy(format, height); + size = fbdt->stride * nblocksy; + + fbdt->data = align_malloc(size, alignment); + if (!fbdt->data) { + FREE(fbdt); + return NULL; + } + + *stride = fbdt->stride; + + return (struct sw_displaytarget *) fbdt; +} + +static boolean +fbdev_is_displaytarget_format_supported(struct sw_winsys *ws, + unsigned tex_usage, + enum pipe_format format) +{ + struct fbdev_sw_winsys *fbdev = fbdev_sw_winsys(ws); + return (fbdev->format == format); +} + +static void +fbdev_destroy(struct sw_winsys *ws) +{ + struct fbdev_sw_winsys *fbdev = fbdev_sw_winsys(ws); + + munmap(fbdev->fbmem, fbdev->finfo.smem_len); + FREE(fbdev); +} + +struct sw_winsys * +fbdev_create_sw_winsys(int fd, enum pipe_format format) +{ + struct fbdev_sw_winsys *fbdev; + + fbdev = CALLOC_STRUCT(fbdev_sw_winsys); + if (!fbdev) + return NULL; + + fbdev->fd = fd; + fbdev->format = format; + if (ioctl(fbdev->fd, FBIOGET_FSCREENINFO, &fbdev->finfo)) { + FREE(fbdev); + return NULL; + } + + fbdev->fbmem = mmap(0, fbdev->finfo.smem_len, + PROT_WRITE, MAP_SHARED, fbdev->fd, 0); + if (fbdev->fbmem == MAP_FAILED) { + FREE(fbdev); + return NULL; + } + + fbdev->rows = fbdev->finfo.smem_len / fbdev->finfo.line_length; + fbdev->stride = fbdev->finfo.line_length; + + fbdev->base.destroy = fbdev_destroy; + fbdev->base.is_displaytarget_format_supported = + fbdev_is_displaytarget_format_supported; + + fbdev->base.displaytarget_create = fbdev_displaytarget_create; + fbdev->base.displaytarget_destroy = fbdev_displaytarget_destroy; + fbdev->base.displaytarget_map = fbdev_displaytarget_map; + fbdev->base.displaytarget_unmap = fbdev_displaytarget_unmap; + + fbdev->base.displaytarget_display = fbdev_displaytarget_display; + + return &fbdev->base; +} diff --git a/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.h b/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.h new file mode 100644 index 00000000000..d958ab9db3e --- /dev/null +++ b/src/gallium/winsys/sw/fbdev/fbdev_sw_winsys.h @@ -0,0 +1,38 @@ +/* + * Mesa 3-D graphics library + * Version: 7.8 + * + * Copyright (C) 2010 LunarG Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Chia-I Wu <[email protected]> + */ + +#ifndef FBDEV_SW_WINSYS +#define FBDEV_SW_WINSYS + +struct sw_winsys; +enum pipe_format; + +struct sw_winsys * +fbdev_create_sw_winsys(int fd, enum pipe_format format); + +#endif /* FBDEV_SW_WINSYS */ diff --git a/src/gallium/winsys/sw/null/null_sw_winsys.c b/src/gallium/winsys/sw/null/null_sw_winsys.c index 157efa9973e..73b777f6296 100644 --- a/src/gallium/winsys/sw/null/null_sw_winsys.c +++ b/src/gallium/winsys/sw/null/null_sw_winsys.c @@ -35,6 +35,7 @@ * @author Jose Fonseca */ +#include <stdio.h> #include "pipe/p_format.h" #include "util/u_memory.h" @@ -85,6 +86,7 @@ null_sw_displaytarget_create(struct sw_winsys *winsys, unsigned alignment, unsigned *stride) { + fprintf(stderr, "null_sw_displaytarget_create() returning NULL\n"); return NULL; } diff --git a/src/gallium/winsys/sw/wrapper/SConscript b/src/gallium/winsys/sw/wrapper/SConscript new file mode 100644 index 00000000000..4c60488df0b --- /dev/null +++ b/src/gallium/winsys/sw/wrapper/SConscript @@ -0,0 +1,21 @@ +####################################################################### +# SConscript for xlib winsys + + +Import('*') + +env = env.Clone() + +env.Append(CPPPATH = [ + '#/src/gallium/include', + '#/src/gallium/auxiliary', + '#/src/gallium/drivers', +]) + +ws_wrapper = env.ConvenienceLibrary( + target = 'ws_wrapper', + source = [ + 'wrapper_sw_winsys.c', + ] +) +Export('ws_wrapper') diff --git a/src/gallium/winsys/sw/wrapper/wrapper_sw_winsys.c b/src/gallium/winsys/sw/wrapper/wrapper_sw_winsys.c index d4d4270eb86..3a76098b655 100644 --- a/src/gallium/winsys/sw/wrapper/wrapper_sw_winsys.c +++ b/src/gallium/winsys/sw/wrapper/wrapper_sw_winsys.c @@ -52,6 +52,7 @@ struct wrapper_sw_winsys struct sw_winsys base; struct pipe_screen *screen; struct pipe_context *pipe; + enum pipe_texture_target target; }; struct wrapper_sw_displaytarget @@ -145,6 +146,7 @@ wsw_dt_create(struct sw_winsys *ws, * XXX Why don't we just get the template. */ memset(&templ, 0, sizeof(templ)); + templ.target = wsw->target; templ.width0 = width; templ.height0 = height; templ.format = format; @@ -175,6 +177,18 @@ wsw_dt_from_handle(struct sw_winsys *ws, return wsw_dt_wrap_texture(wsw, tex, stride); } +static boolean +wsw_dt_get_handle(struct sw_winsys *ws, + struct sw_displaytarget *dt, + struct winsys_handle *whandle) +{ + struct wrapper_sw_winsys *wsw = wrapper_sw_winsys(ws); + struct wrapper_sw_displaytarget *wdt = wrapper_sw_displaytarget(dt); + struct pipe_resource *tex = wdt->tex; + + return wsw->screen->resource_get_handle(wsw->screen, tex, whandle); +} + static void * wsw_dt_map(struct sw_winsys *ws, struct sw_displaytarget *dt, @@ -267,6 +281,7 @@ wrapper_sw_winsys_warp_pipe_screen(struct pipe_screen *screen) wsw->base.displaytarget_create = wsw_dt_create; wsw->base.displaytarget_from_handle = wsw_dt_from_handle; + wsw->base.displaytarget_get_handle = wsw_dt_get_handle; wsw->base.displaytarget_map = wsw_dt_map; wsw->base.displaytarget_unmap = wsw_dt_unmap; wsw->base.displaytarget_destroy = wsw_dt_destroy; @@ -277,6 +292,11 @@ wrapper_sw_winsys_warp_pipe_screen(struct pipe_screen *screen) if (!wsw->pipe) goto err_free; + if(screen->get_param(screen, PIPE_CAP_NPOT_TEXTURES)) + wsw->target = PIPE_TEXTURE_2D; + else + wsw->target = PIPE_TEXTURE_RECT; + return &wsw->base; err_free: diff --git a/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c b/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c index 56d2df825df..b78f537c125 100644 --- a/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c +++ b/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c @@ -255,11 +255,17 @@ xm_displaytarget_destroy(struct sw_winsys *ws, } else { FREE(xm_dt->data); + if (xm_dt->tempImage && xm_dt->tempImage->data == xm_dt->data) { + xm_dt->tempImage->data = NULL; + } + xm_dt->data = NULL; } } - if (xm_dt->tempImage) + if (xm_dt->tempImage) { XDestroyImage(xm_dt->tempImage); + xm_dt->tempImage = NULL; + } if (xm_dt->gc) XFreeGC(xm_dt->display, xm_dt->gc); |