diff options
| author | Christian König <[email protected]> | 2018-02-26 14:13:28 +0100 |
|---|---|---|
| committer | Christian König <[email protected]> | 2018-02-28 13:30:32 +0100 |
| commit | 33633690aa51ff5c79909146d6453b50e37dbad0 (patch) | |
| tree | ccebe9d6f47ec77b8bbfe062f119638987696ab9 /src/gallium/winsys | |
| parent | 639c4f2b54a6edbedfc3f75fd05d1588752b0693 (diff) | |
winsys/amdgpu: request high addresses
We now have hopefully fixed all bugs regarding high addresses on Vega10 and
Raven. Start to use the high range to make room for SVM in the low
range.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium/winsys')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index 19f6fedf7c0..12d497d2921 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -38,6 +38,10 @@ #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) #endif +#ifndef AMDGPU_VA_RANGE_HIGH +#define AMDGPU_VA_RANGE_HIGH 0x2 +#endif + /* Set to 1 for verbose output showing committed sparse buffer ranges. */ #define DEBUG_SPARSE_COMMITS 0 @@ -438,7 +442,8 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, alignment = MAX2(alignment, ws->info.pte_fragment_size); r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, size + va_gap_size, alignment, 0, &va, &va_handle, - flags & RADEON_FLAG_32BIT ? AMDGPU_VA_RANGE_32_BIT : 0); + (flags & RADEON_FLAG_32BIT ? AMDGPU_VA_RANGE_32_BIT : 0) | + AMDGPU_VA_RANGE_HIGH); if (r) goto error_va_alloc; @@ -896,7 +901,8 @@ amdgpu_bo_sparse_create(struct amdgpu_winsys *ws, uint64_t size, va_gap_size = ws->check_vm ? 4 * RADEON_SPARSE_PAGE_SIZE : 0; r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, map_size + va_gap_size, RADEON_SPARSE_PAGE_SIZE, - 0, &bo->va, &bo->u.sparse.va_handle, 0); + 0, &bo->va, &bo->u.sparse.va_handle, + AMDGPU_VA_RANGE_HIGH); if (r) goto error_va_alloc; @@ -1290,7 +1296,8 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws, goto error_query; r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, - result.alloc_size, 1 << 20, 0, &va, &va_handle, 0); + result.alloc_size, 1 << 20, 0, &va, &va_handle, + AMDGPU_VA_RANGE_HIGH); if (r) goto error_query; @@ -1401,7 +1408,8 @@ static struct pb_buffer *amdgpu_bo_from_ptr(struct radeon_winsys *rws, goto error; if (amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, - aligned_size, 1 << 12, 0, &va, &va_handle, 0)) + aligned_size, 1 << 12, 0, &va, &va_handle, + AMDGPU_VA_RANGE_HIGH)) goto error_va_alloc; if (amdgpu_bo_va_op(buf_handle, 0, aligned_size, va, 0, AMDGPU_VA_OP_MAP)) |