Merge remote-tracking branch 'origin/master' into pipe-video

Conflicts:
	src/gallium/tests/unit/u_format_test.c
	src/gallium/winsys/r600/drm/r600_hw_context.c

10 files changed, 478 insertions, 989 deletions

diff --git a/src/gallium/winsys/r600/drm/Makefile b/src/gallium/winsys/r600/drm/Makefile
index 7310734f051..fb7b09b3a0d 100644
--- a/src/gallium/winsys/r600/drm/Makefile
+++ b/src/gallium/winsys/r600/drm/Makefile
@@ -15,6 +15,7 @@ C_SOURCES = \
 	r600_bomgr.c
 
 LIBRARY_INCLUDES = -I$(TOP)/src/gallium/drivers/r600 \
+		   -I$(TOP)/include \
 		   $(shell pkg-config libdrm --cflags-only-I)
 
 include ../../../Makefile.template
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index cf8ae5185b4..e4ab690c560 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -43,31 +43,33 @@
 static const struct r600_reg evergreen_config_reg_list[] = {
 	{R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
 	{R_008A14_PA_CL_ENHANCE, 0, 0, 0},
-	{R_008C00_SQ_CONFIG, 0, 0, 0},
-	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
-	{R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
-	{R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
-	{R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 0, 0, 0},
-	{R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, 0, 0, 0},
-	{R_008C20_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
-	{R_008C24_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
-	{R_008C28_SQ_STACK_RESOURCE_MGMT_3, 0, 0, 0},
-	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
-	{R_009100_SPI_CONFIG_CNTL, 0, 0, 0},
-	{R_00913C_SPI_CONFIG_CNTL_1, 0, 0, 0},
+	{R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C18_SQ_THREAD_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C20_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C24_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C28_SQ_STACK_RESOURCE_MGMT_3, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
 };
 
 
 static const struct r600_reg cayman_config_reg_list[] = {
 	{R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
 	{R_008A14_PA_CL_ENHANCE, 0, 0, 0},
-	{R_008C00_SQ_CONFIG, 0, 0, 0},
-	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
-	{CM_R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0, 0},
-	{CM_R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0, 0},
-	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
-	{R_009100_SPI_CONFIG_CNTL, 0, 0, 0},
-	{R_00913C_SPI_CONFIG_CNTL_1, 0, 0, 0},
+	{R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
 };
 
 static const struct r600_reg evergreen_ctl_const_list[] = {
@@ -125,6 +127,8 @@ static const struct r600_reg evergreen_context_reg_list[] = {
 	{R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
 	{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
 	{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
+	{R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
+	{R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
 	{R_028350_SX_MISC, 0, 0, 0},
 	{R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
 	{R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
@@ -158,12 +162,12 @@ static const struct r600_reg evergreen_context_reg_list[] = {
 	{R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
 	{R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
 	{R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
-	{R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
-	{R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 	{R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
 	{R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
 	{R_028408_VGT_INDX_OFFSET, 0, 0, 0},
 	{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 	{R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
 	{R_028414_CB_BLEND_RED, 0, 0, 0},
 	{R_028418_CB_BLEND_GREEN, 0, 0, 0},
@@ -487,6 +491,8 @@ static const struct r600_reg cayman_context_reg_list[] = {
 	{R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
 	{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
 	{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
+	{R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
+	{R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
 	{R_028350_SX_MISC, 0, 0, 0},
 	{R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
 	{R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
@@ -520,12 +526,12 @@ static const struct r600_reg cayman_context_reg_list[] = {
 	{R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
 	{R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
 	{R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
-	{R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
-	{R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 	{R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
 	{R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
 	{R_028408_VGT_INDX_OFFSET, 0, 0, 0},
 	{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
 	{R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
 	{R_028414_CB_BLEND_RED, 0, 0, 0},
 	{R_028418_CB_BLEND_GREEN, 0, 0, 0},
@@ -817,13 +823,13 @@ static const struct r600_reg cayman_context_reg_list[] = {
 };
 
 /* SHADER RESOURCE R600/R700 */
-static int evergreen_state_resource_init(struct r600_context *ctx, u32 offset)
+static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
 {
 	struct r600_reg r600_shader_resource[] = {
-		{R_030000_RESOURCE0_WORD0, 0, 0, 0},
-		{R_030004_RESOURCE0_WORD1, 0, 0, 0},
-		{R_030008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
-		{R_03000C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
+		{R_030000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
+		{R_030004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
+		{R_030008_RESOURCE0_WORD2, 0, 0, 0},
+		{R_03000C_RESOURCE0_WORD3, 0, 0, 0},
 		{R_030010_RESOURCE0_WORD4, 0, 0, 0},
 		{R_030014_RESOURCE0_WORD5, 0, 0, 0},
 		{R_030018_RESOURCE0_WORD6, 0, 0, 0},
@@ -831,10 +837,7 @@ static int evergreen_state_resource_init(struct r600_context *ctx, u32 offset)
 	};
 	unsigned nreg = Elements(r600_shader_resource);
 
-	for (int i = 0; i < nreg; i++) {
-		r600_shader_resource[i].offset += offset;
-	}
-	return r600_context_add_block(ctx, r600_shader_resource, nreg, PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET);
+	return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, EVERGREEN_RESOURCE_OFFSET);
 }
 
 /* SHADER SAMPLER R600/R700 */
@@ -907,6 +910,11 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 	ctx->radeon = radeon;
 	LIST_INITHEAD(&ctx->query_list);
 
+	/* init dirty list */
+	LIST_INITHEAD(&ctx->dirty);
+	LIST_INITHEAD(&ctx->resource_dirty);
+	LIST_INITHEAD(&ctx->enable_list);
+
 	ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
 	if (!ctx->range) {
 		r = -ENOMEM;
@@ -960,24 +968,19 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 		if (r)
 			goto out_err;
 	}
-	/* PS RESOURCE */
-	for (int j = 0, offset = 0; j < 176; j++, offset += 0x20) {
-		r = evergreen_state_resource_init(ctx, offset);
-		if (r)
-			goto out_err;
-	}
-	/* VS RESOURCE */
-	for (int j = 0, offset = 0x1600; j < 160; j++, offset += 0x20) {
-		r = evergreen_state_resource_init(ctx, offset);
-		if (r)
-			goto out_err;
-	}
-	/* FS RESOURCE */
-	for (int j = 0, offset = 0x7C00; j < 16; j++, offset += 0x20) {
-		r = evergreen_state_resource_init(ctx, offset);
-		if (r)
-			goto out_err;
-	}
+
+	ctx->num_ps_resources = 176;
+	ctx->num_vs_resources = 160;
+	ctx->num_fs_resources = 16;
+	r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 176, 0x20);
+	if (r)
+		goto out_err;
+	r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1600, 160, 0x20);
+	if (r)
+		goto out_err;
+	r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x7C00, 16, 0x20);
+	if (r)
+		goto out_err;
 
 	/* PS loop const */
 	evergreen_loop_const_init(ctx, 0);
@@ -1015,33 +1018,31 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 
 	LIST_INITHEAD(&ctx->fenced_bo);
 
-	/* init dirty list */
-	LIST_INITHEAD(&ctx->dirty);
 	return 0;
 out_err:
 	r600_context_fini(ctx);
 	return r;
 }
 
-void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
 {
-	unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x20 * rid;
+	struct r600_block *block = ctx->ps_resources.blocks[rid];
 
-	r600_context_pipe_state_set_resource(ctx, state, offset);
+	r600_context_pipe_state_set_resource(ctx, state, block);
 }
 
-void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
 {
-	unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x1600 + 0x20 * rid;
+	struct r600_block *block = ctx->vs_resources.blocks[rid];
 
-	r600_context_pipe_state_set_resource(ctx, state, offset);
+	r600_context_pipe_state_set_resource(ctx, state, block);
 }
 
-void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
 {
-	unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x7C00 + 0x20 * rid;
+	struct r600_block *block = ctx->fs_resources.blocks[rid];
 
-	r600_context_pipe_state_set_resource(ctx, state, offset);
+	r600_context_pipe_state_set_resource(ctx, state, block);
 }
 
 static inline void evergreen_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
@@ -1056,6 +1057,7 @@ static inline void evergreen_context_pipe_state_set_sampler(struct r600_context
 	if (state == NULL) {
 		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
 		LIST_DELINIT(&block->list);
+		LIST_DELINIT(&block->enable_list);
 		return;
 	}
 	dirty = block->status & R600_BLOCK_STATUS_DIRTY;
@@ -1066,8 +1068,8 @@ static inline void evergreen_context_pipe_state_set_sampler(struct r600_context
 			block->reg[i] = state->regs[i].value;
 		}
 	}
-
-	r600_context_dirty_block(ctx, block, dirty, 2);
+	if (dirty)
+		r600_context_dirty_block(ctx, block, dirty, 2);
 }
 
 static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx)
@@ -1094,6 +1096,7 @@ static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_c
 	if (state == NULL) {
 		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
 		LIST_DELINIT(&block->list);
+		LIST_DELINIT(&block->enable_list);
 		return;
 	}
 	if (state->nregs <= 3) {
@@ -1119,7 +1122,8 @@ static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_c
 	if (dirty & R600_BLOCK_STATUS_DIRTY)
 		evergreen_context_ps_partial_flush(ctx);
 
-	r600_context_dirty_block(ctx, block, dirty, 4);
+	if (dirty)
+		r600_context_dirty_block(ctx, block, dirty, 4);
 }
 
 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
@@ -1146,6 +1150,7 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr
 	unsigned ndwords = 7;
 	struct r600_block *dirty_block = NULL;
 	struct r600_block *next_block;
+	uint32_t *pm4;
 
 	if (draw->indices) {
 		ndwords = 11;
@@ -1186,25 +1191,31 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr
 		r600_context_block_emit_dirty(ctx, dirty_block);
 	}
 
+	LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->resource_dirty,list) {
+		r600_context_block_resource_emit_dirty(ctx, dirty_block);
+	}
+
 	/* draw packet */
-	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
-	ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
-	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
-	ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
+	pm4 = &ctx->pm4[ctx->pm4_cdwords];
+	pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
+	pm4[1] = draw->vgt_index_type;
+	pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
+	pm4[3] = draw->vgt_num_instances;
 	if (draw->indices) {
-	        ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
-		ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
-		ctx->pm4[ctx->pm4_cdwords++] = 0;
-		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
-		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
-		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
-		ctx->pm4[ctx->pm4_cdwords++] = 0;
-		r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices);
+	        pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
+		pm4[5] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
+		pm4[6] = 0;
+		pm4[7] = draw->vgt_num_indices;
+		pm4[8] = draw->vgt_draw_initiator;
+		pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
+		pm4[10] = 0;
+		r600_context_bo_reloc(ctx, &pm4[10], draw->indices);
 	} else {
-		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
-		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
-		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
+		pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
+		pm4[5] = draw->vgt_num_indices;
+		pm4[6] = draw->vgt_draw_initiator;
 	}
+	ctx->pm4_cdwords += ndwords;
 
 	ctx->flags |= (R600_CONTEXT_DRAW_PENDING | R600_CONTEXT_DST_CACHES_DIRTY);
 
diff --git a/src/gallium/winsys/r600/drm/r600_bo.c b/src/gallium/winsys/r600/drm/r600_bo.c
index 63d5f0bf9bb..d7e27e07e3b 100644
--- a/src/gallium/winsys/r600/drm/r600_bo.c
+++ b/src/gallium/winsys/r600/drm/r600_bo.c
@@ -193,16 +193,6 @@ void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo)
 	free(bo);
 }
 
-void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, struct r600_bo *src)
-{
-	struct r600_bo *old = *dst;
-
-	if (pipe_reference(&(*dst)->reference, &src->reference)) {
-		r600_bo_destroy(radeon, old);
-	}
-	*dst = src;
-}
-
 boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *bo,
 				unsigned stride, struct winsys_handle *whandle)
 {
diff --git a/src/gallium/winsys/r600/drm/r600_bomgr.c b/src/gallium/winsys/r600/drm/r600_bomgr.c
index 446ef0f9cfc..4918d5eb0b1 100644
--- a/src/gallium/winsys/r600/drm/r600_bomgr.c
+++ b/src/gallium/winsys/r600/drm/r600_bomgr.c
@@ -116,7 +116,7 @@ void r600_bomgr_bo_init(struct r600_bomgr *mgr, struct r600_bo *bo)
 	bo->manager_id = 1;
 }
 
-bool r600_bomgr_bo_destroy(struct r600_bomgr *mgr, struct r600_bo *bo)
+boolean r600_bomgr_bo_destroy(struct r600_bomgr *mgr, struct r600_bo *bo)
 {
 	bo->start = os_time_get();
 	bo->end = bo->start + mgr->usecs;
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index af80aa67a44..711ce18c6ca 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -79,6 +79,74 @@ static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsig
 	}
 }
 
+static void r600_init_block(struct r600_context *ctx,
+			    struct r600_block *block,
+			    const struct r600_reg *reg, int index, int nreg,
+			    unsigned opcode, unsigned offset_base)
+{
+	int i = index;
+	int j, n = nreg;
+
+	/* initialize block */
+	if (opcode == PKT3_SET_RESOURCE) {
+		block->flags = BLOCK_FLAG_RESOURCE;
+		block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */
+	} else {
+		block->flags = 0;
+		block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
+	}
+	block->start_offset = reg[i].offset;
+	block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
+	block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
+	block->reg = &block->pm4[block->pm4_ndwords];
+	block->pm4_ndwords += n;
+	block->nreg = n;
+	block->nreg_dirty = n;
+	LIST_INITHEAD(&block->list);
+	LIST_INITHEAD(&block->enable_list);
+
+	for (j = 0; j < n; j++) {
+		if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
+			block->flags |= REG_FLAG_DIRTY_ALWAYS;
+		}
+		if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
+			if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
+				block->status |= R600_BLOCK_STATUS_ENABLED;
+				LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
+				LIST_ADDTAIL(&block->list,&ctx->dirty);
+			}
+		}
+
+		if (reg[i+j].flags & REG_FLAG_NEED_BO) {
+			block->nbo++;
+			assert(block->nbo < R600_BLOCK_MAX_BO);
+			block->pm4_bo_index[j] = block->nbo;
+			block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
+			block->pm4[block->pm4_ndwords++] = 0x00000000;
+			if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
+				block->reloc[block->nbo].flush_flags = 0;
+				block->reloc[block->nbo].flush_mask = 0;
+			} else {
+				block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
+				block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
+			}
+			block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
+		}
+		if ((ctx->radeon->family > CHIP_R600) &&
+		    (ctx->radeon->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
+			block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
+			block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
+		}
+	}
+	for (j = 0; j < n; j++) {
+		if (reg[i+j].flush_flags) {
+			block->pm4_flush_ndwords += 7;
+		}
+	}
+	/* check that we stay in limit */
+	assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
+}
+
 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
 			   unsigned opcode, unsigned offset_base)
 {
@@ -87,8 +155,6 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
 	int offset;
 
 	for (unsigned i = 0, n = 0; i < nreg; i += n) {
-		u32 j;
-
 		/* ignore new block balise */
 		if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
 			n = 1;
@@ -131,50 +197,8 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
 			range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
 		}
 
-		/* initialize block */
-		block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
-		block->start_offset = reg[i].offset;
-		block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
-		block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
-		block->reg = &block->pm4[block->pm4_ndwords];
-		block->pm4_ndwords += n;
-		block->nreg = n;
-		block->nreg_dirty = n;
-		block->flags = 0;
-		LIST_INITHEAD(&block->list);
+		r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
 
-		for (j = 0; j < n; j++) {
-			if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
-				block->flags |= REG_FLAG_DIRTY_ALWAYS;
-			}
-			if (reg[i+j].flags & REG_FLAG_NEED_BO) {
-				block->nbo++;
-				assert(block->nbo < R600_BLOCK_MAX_BO);
-				block->pm4_bo_index[j] = block->nbo;
-				block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
-				block->pm4[block->pm4_ndwords++] = 0x00000000;
-				if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
-					block->reloc[block->nbo].flush_flags = 0;
-					block->reloc[block->nbo].flush_mask = 0;
-				} else {
-					block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
-					block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
-				}
-				block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
-			}
-			if ((ctx->radeon->family > CHIP_R600) &&
-			    (ctx->radeon->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
-				block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
-				block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
-			}
-		}
-		for (j = 0; j < n; j++) {
-			if (reg[i+j].flush_flags) {
-				block->pm4_flush_ndwords += 7;
-			}
-		}
-		/* check that we stay in limit */
-		assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
 	}
 	return 0;
 }
@@ -182,17 +206,17 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
 /* R600/R700 configuration */
 static const struct r600_reg r600_config_reg_list[] = {
 	{R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
-	{R_008C00_SQ_CONFIG, 0, 0, 0},
-	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
-	{R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
-	{R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
-	{R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
-	{R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
-	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
-	{R_009508_TA_CNTL_AUX, 0, 0, 0},
-	{R_009714_VC_ENHANCE, 0, 0, 0},
-	{R_009830_DB_DEBUG, 0, 0, 0},
-	{R_009838_DB_WATERMARKS, 0, 0, 0},
+	{R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS, 0, 0},
+	{R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS, 0, 0},
 };
 
 static const struct r600_reg r600_ctl_const_list[] = {
@@ -552,23 +576,44 @@ static const struct r600_reg r600_context_reg_list[] = {
 };
 
 /* SHADER RESOURCE R600/R700 */
-static int r600_state_resource_init(struct r600_context *ctx, u32 offset)
+int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base)
+{
+	int i;
+	struct r600_block *block;
+	range->blocks = calloc(nblocks, sizeof(struct r600_block *));
+	if (range->blocks == NULL)
+		return -ENOMEM;
+
+	reg[0].offset += offset;
+	for (i = 0; i < nblocks; i++) {
+		block = calloc(1, sizeof(struct r600_block));
+		if (block == NULL) {
+			return -ENOMEM;
+		}
+		ctx->nblocks++;
+		range->blocks[i] = block;
+		r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base);
+
+		reg[0].offset += stride;
+	}
+	return 0;
+}
+
+      
+static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
 {
 	struct r600_reg r600_shader_resource[] = {
-		{R_038000_RESOURCE0_WORD0, 0, 0, 0},
-		{R_038004_RESOURCE0_WORD1, 0, 0, 0},
-		{R_038008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
-		{R_03800C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
+		{R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
+		{R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
+		{R_038008_RESOURCE0_WORD2, 0, 0, 0},
+		{R_03800C_RESOURCE0_WORD3, 0, 0, 0},
 		{R_038010_RESOURCE0_WORD4, 0, 0, 0},
 		{R_038014_RESOURCE0_WORD5, 0, 0, 0},
 		{R_038018_RESOURCE0_WORD6, 0, 0, 0},
 	};
 	unsigned nreg = Elements(r600_shader_resource);
 
-	for (int i = 0; i < nreg; i++) {
-		r600_shader_resource[i].offset += offset;
-	}
-	return r600_context_add_block(ctx, r600_shader_resource, nreg, PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET);
+	return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET);
 }
 
 /* SHADER SAMPLER R600/R700 */
@@ -630,6 +675,22 @@ static void r600_context_clear_fenced_bo(struct r600_context *ctx)
 	}
 }
 
+static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks)
+{
+	struct r600_block *block;
+	int i;
+	for (i = 0; i < nblocks; i++) {
+		block = range->blocks[i];
+		if (block) {
+			for (int k = 1; k <= block->nbo; k++)
+				r600_bo_reference(ctx->radeon, &block->reloc[k].bo, NULL);
+			free(block);
+		}
+	}
+	free(range->blocks);
+
+}
+
 /* initialize */
 void r600_context_fini(struct r600_context *ctx)
 {
@@ -654,6 +715,9 @@ void r600_context_fini(struct r600_context *ctx)
 		}
 		free(ctx->range[i].blocks);
 	}
+	r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources);
+	r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources);
+	r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources);
 	free(ctx->range);
 	free(ctx->blocks);
 	free(ctx->reloc);
@@ -664,13 +728,26 @@ void r600_context_fini(struct r600_context *ctx)
 	memset(ctx, 0, sizeof(struct r600_context));
 }
 
+static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index)
+{
+	int c = *index;
+	for (int j = 0; j < num_blocks; j++) {
+		if (!range->blocks[j])
+			continue;
+
+		ctx->blocks[c++] = range->blocks[j];
+	}
+	*index = c;
+}
+
 int r600_setup_block_table(struct r600_context *ctx)
 {
 	/* setup block table */
+	int c = 0;
 	ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
 	if (!ctx->blocks)
 		return -ENOMEM;
-	for (int i = 0, c = 0; i < NUM_RANGES; i++) {
+	for (int i = 0; i < NUM_RANGES; i++) {
 		if (!ctx->range[i].blocks)
 			continue;
 		for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
@@ -691,6 +768,10 @@ int r600_setup_block_table(struct r600_context *ctx)
 			}
 		}
 	}
+
+	r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c);
+	r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c);
+	r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c);
 	return 0;
 }
 
@@ -702,6 +783,11 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
 	ctx->radeon = radeon;
 	LIST_INITHEAD(&ctx->query_list);
 
+	/* init dirty list */
+	LIST_INITHEAD(&ctx->dirty);
+	LIST_INITHEAD(&ctx->resource_dirty);
+	LIST_INITHEAD(&ctx->enable_list);
+
 	ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
 	if (!ctx->range) {
 		r = -ENOMEM;
@@ -747,24 +833,19 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
 		if (r)
 			goto out_err;
 	}
-	/* PS RESOURCE */
-	for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) {
-		r = r600_state_resource_init(ctx, offset);
-		if (r)
-			goto out_err;
-	}
-	/* VS RESOURCE */
-	for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) {
-		r = r600_state_resource_init(ctx, offset);
-		if (r)
-			goto out_err;
-	}
-	/* FS RESOURCE */
-	for (int j = 0, offset = 0x2300; j < 16; j++, offset += 0x1C) {
-		r = r600_state_resource_init(ctx, offset);
-		if (r)
-			goto out_err;
-	}
+
+	ctx->num_ps_resources = 160;
+	ctx->num_vs_resources = 160;
+	ctx->num_fs_resources = 16;
+	r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c);
+	if (r)
+		goto out_err;
+	r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c);
+	if (r)
+		goto out_err;
+	r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c);
+	if (r)
+		goto out_err;
 
 	/* PS loop const */
 	r600_loop_const_init(ctx, 0);
@@ -800,9 +881,6 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
 
 	LIST_INITHEAD(&ctx->fenced_bo);
 
-	/* init dirty list */
-	LIST_INITHEAD(&ctx->dirty);
-
 	ctx->max_db = 4;
 
 	return 0;
@@ -874,16 +952,9 @@ void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
 	bo->last_flush = (bo->last_flush | flush_flags) & flush_mask;
 }
 
-void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo)
+void r600_context_get_reloc(struct r600_context *ctx, struct r600_bo *rbo)
 {
-	struct radeon_bo *bo;
-
-	bo = rbo->bo;
-	assert(bo != NULL);
-	if (bo->reloc) {
-		*pm4 = bo->reloc_id;
-		return;
-	}
+	struct radeon_bo *bo = rbo->bo;
 	bo->reloc = &ctx->reloc[ctx->creloc];
 	bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
 	ctx->reloc[ctx->creloc].handle = bo->handle;
@@ -893,8 +964,6 @@ void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *r
 	radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
 	rbo->fence = ctx->radeon->fence;
 	ctx->creloc++;
-	/* set PKT3 to point to proper reloc */
-	*pm4 = bo->reloc_id;
 }
 
 void r600_context_reg(struct r600_context *ctx,
@@ -920,20 +989,24 @@ void r600_context_reg(struct r600_context *ctx,
 		dirty |= R600_BLOCK_STATUS_DIRTY;
 		block->reg[id] = new_val;
 	}
-	r600_context_dirty_block(ctx, block, dirty, id);
+	if (dirty)
+		r600_context_dirty_block(ctx, block, dirty, id);
 }
 
-void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block,
+void r600_context_dirty_block(struct r600_context *ctx,
+			      struct r600_block *block,
 			      int dirty, int index)
 {
-	if (dirty && (index + 1) > block->nreg_dirty)
+	if ((index + 1) > block->nreg_dirty)
 		block->nreg_dirty = index + 1;
 
 	if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
-
-		block->status |= R600_BLOCK_STATUS_ENABLED;
 		block->status |= R600_BLOCK_STATUS_DIRTY;
 		ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
+		if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
+			block->status |= R600_BLOCK_STATUS_ENABLED;
+			LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
+		}
 		LIST_ADDTAIL(&block->list,&ctx->dirty);
 	}
 }
@@ -970,103 +1043,121 @@ void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_stat
 			dirty |= R600_BLOCK_STATUS_DIRTY;
 		}
 
-		r600_context_dirty_block(ctx, block, dirty, id);
+		if (dirty)
+			r600_context_dirty_block(ctx, block, dirty, id);
 	}
 }
 
-void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+static void r600_context_dirty_resource_block(struct r600_context *ctx,
+					      struct r600_block *block,
+					      int dirty, int index)
+{
+	block->nreg_dirty = index + 1;
+
+	if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
+		block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
+		ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
+		if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
+			block->status |= R600_BLOCK_STATUS_ENABLED;
+			LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
+		}
+		LIST_ADDTAIL(&block->list,&ctx->resource_dirty);
+	}
+}
+
+void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block)
 {
-	struct r600_range *range;
-	struct r600_block *block;
-	int i;
 	int dirty;
 	int num_regs = ctx->radeon->chip_class >= EVERGREEN ? 8 : 7;
+	boolean is_vertex;
 
-	range = &ctx->range[CTX_RANGE_ID(offset)];
-	block = range->blocks[CTX_BLOCK_ID(offset)];
 	if (state == NULL) {
-		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY);
 		if (block->reloc[1].bo)
 			block->reloc[1].bo->bo->binding &= ~BO_BOUND_TEXTURE;
 
 		r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
-		r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+		r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
 		LIST_DELINIT(&block->list);
+		LIST_DELINIT(&block->enable_list);
 		return;
 	}
 
-	dirty = block->status & R600_BLOCK_STATUS_DIRTY;
+	is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
+	dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY;
 
-	for (i = 0; i < num_regs; i++) {
-		if (block->reg[i] != state->regs[i].value) {
-			dirty |= R600_BLOCK_STATUS_DIRTY;
-			block->reg[i] = state->regs[i].value;
-		}
+	if (memcmp(block->reg, state->val, num_regs*4)) {
+		memcpy(block->reg, state->val, num_regs * 4);
+		dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
 	}
 
 	/* if no BOs on block, force dirty */
 	if (!block->reloc[1].bo || !block->reloc[2].bo)
-		dirty |= R600_BLOCK_STATUS_DIRTY;
+		dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
 
 	if (!dirty) {
-		if (state->regs[0].bo) {
-			if ((block->reloc[1].bo->bo->handle != state->regs[0].bo->bo->handle) ||
-			    (block->reloc[2].bo->bo->handle != state->regs[0].bo->bo->handle))
-				dirty |= R600_BLOCK_STATUS_DIRTY;
+		if (is_vertex) {
+			if (block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle)
+				dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
 		} else {
-			if ((block->reloc[1].bo->bo->handle != state->regs[2].bo->bo->handle) ||
-			    (block->reloc[2].bo->bo->handle != state->regs[3].bo->bo->handle))
-				dirty |= R600_BLOCK_STATUS_DIRTY;
+			if ((block->reloc[1].bo->bo->handle != state->bo[0]->bo->handle) ||
+			    (block->reloc[2].bo->bo->handle != state->bo[1]->bo->handle))
+				dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
 		}
 	}
 	if (!dirty) {
-		if (state->regs[0].bo)
-			state->regs[0].bo->fence = ctx->radeon->fence;
+		if (is_vertex)
+			state->bo[0]->fence = ctx->radeon->fence;
 		else {
-			state->regs[2].bo->fence = ctx->radeon->fence;
-			state->regs[3].bo->fence = ctx->radeon->fence;
+			state->bo[0]->fence = ctx->radeon->fence;
+			state->bo[1]->fence = ctx->radeon->fence;
 		}
 	} else {
-		r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
-		r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
-		if (state->regs[0].bo) {
+		if (is_vertex) {
 			/* VERTEX RESOURCE, we preted there is 2 bo to relocate so
 			 * we have single case btw VERTEX & TEXTURE resource
 			 */
-			r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
-			r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
-			state->regs[0].bo->fence = ctx->radeon->fence;
+			r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
+			r600_bo_reference(ctx->radeon, &block->reloc[2].bo, NULL);
+			state->bo[0]->fence = ctx->radeon->fence;
 		} else {
 			/* TEXTURE RESOURCE */
-			r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
-			r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
-			state->regs[2].bo->fence = ctx->radeon->fence;
-			state->regs[3].bo->fence = ctx->radeon->fence;
-			state->regs[2].bo->bo->binding |= BO_BOUND_TEXTURE;
+			r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->bo[0]);
+			r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->bo[1]);
+			state->bo[0]->fence = ctx->radeon->fence;
+			state->bo[1]->fence = ctx->radeon->fence;
+			state->bo[0]->bo->binding |= BO_BOUND_TEXTURE;
 		}
 	}
-	r600_context_dirty_block(ctx, block, dirty, num_regs - 1);
+	if (dirty) {
+		if (is_vertex)
+			block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX;
+		else
+			block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX;
+	
+		r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1);
+	}
 }
 
-void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
 {
-	unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid;
+	struct r600_block *block = ctx->ps_resources.blocks[rid];
 
-	r600_context_pipe_state_set_resource(ctx, state, offset);
+	r600_context_pipe_state_set_resource(ctx, state, block);
 }
 
-void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
 {
-	unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid;
+	struct r600_block *block = ctx->vs_resources.blocks[rid];
 
-	r600_context_pipe_state_set_resource(ctx, state, offset);
+	r600_context_pipe_state_set_resource(ctx, state, block);
 }
 
-void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
 {
-	unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x2300 + 0x1C * rid;
+	struct r600_block *block = ctx->fs_resources.blocks[rid];
 
-	r600_context_pipe_state_set_resource(ctx, state, offset);
+	r600_context_pipe_state_set_resource(ctx, state, block);
 }
 
 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
@@ -1081,6 +1172,7 @@ static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx,
 	if (state == NULL) {
 		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
 		LIST_DELINIT(&block->list);
+		LIST_DELINIT(&block->enable_list);
 		return;
 	}
 	dirty = block->status & R600_BLOCK_STATUS_DIRTY;
@@ -1091,7 +1183,8 @@ static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx,
 		}
 	}
 
-	r600_context_dirty_block(ctx, block, dirty, 2);
+	if (dirty)
+		r600_context_dirty_block(ctx, block, dirty, 2);
 }
 
 static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
@@ -1117,6 +1210,7 @@ static inline void r600_context_pipe_state_set_sampler_border(struct r600_contex
 	if (state == NULL) {
 		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
 		LIST_DELINIT(&block->list);
+		LIST_DELINIT(&block->enable_list);
 		return;
 	}
 	if (state->nregs <= 3) {
@@ -1135,8 +1229,8 @@ static inline void r600_context_pipe_state_set_sampler_border(struct r600_contex
 	 * will end up using the new border color. */
 	if (dirty & R600_BLOCK_STATUS_DIRTY)
 		r600_context_ps_partial_flush(ctx);
-
-	r600_context_dirty_block(ctx, block, dirty, 3);
+	if (dirty)
+		r600_context_dirty_block(ctx, block, dirty, 3);
 }
 
 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
@@ -1179,33 +1273,39 @@ void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *
 {
 	int id;
 	int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
-	int cp_dwords = block->pm4_ndwords, start_dword;
-	int new_dwords;
+	int cp_dwords = block->pm4_ndwords, start_dword = 0;
+	int new_dwords = 0;
+	int nbo = block->nbo;
 
 	if (block->nreg_dirty == 0 && optional) {
 		goto out;
 	}
 
-	optional &= (block->nreg_dirty != block->nreg);
-
-	ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
-	for (int j = 0; j < block->nreg; j++) {
-		if (block->pm4_bo_index[j]) {
-			/* find relocation */
-			id = block->pm4_bo_index[j];
-			if (block->reloc[id].bo) {
-				r600_context_bo_reloc(ctx,
-						&block->pm4[block->reloc[id].bo_pm4_index],
-						block->reloc[id].bo);
-				r600_context_bo_flush(ctx,
-						block->reloc[id].flush_flags,
-						block->reloc[id].flush_mask,
-						block->reloc[id].bo);
+	if (nbo) {
+		ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
+
+		for (int j = 0; j < block->nreg; j++) {
+			if (block->pm4_bo_index[j]) {
+				/* find relocation */
+				id = block->pm4_bo_index[j];
+				if (block->reloc[id].bo) {
+					r600_context_bo_reloc(ctx,
+							      &block->pm4[block->reloc[id].bo_pm4_index],
+							      block->reloc[id].bo);
+					r600_context_bo_flush(ctx,
+							      block->reloc[id].flush_flags,
+							      block->reloc[id].flush_mask,
+							      block->reloc[id].bo);
+				}
+				nbo--;
+				if (nbo == 0)
+					break;
 			}
 		}
+		ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
 	}
-	ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
 
+	optional &= (block->nreg_dirty != block->nreg);
 	if (optional) {
 		new_dwords = block->nreg_dirty;
 		start_dword = ctx->pm4_cdwords;
@@ -1228,6 +1328,42 @@ out:
 	LIST_DELINIT(&block->list);
 }
 
+void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block)
+{
+	int id;
+	int cp_dwords = block->pm4_ndwords;
+	int nbo = block->nbo;
+
+	ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
+
+	if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) {
+		nbo = 1;
+		cp_dwords -= 2; /* don't copy the second NOP */
+	}
+
+	for (int j = 0; j < nbo; j++) {
+		if (block->pm4_bo_index[j]) {
+			/* find relocation */
+			id = block->pm4_bo_index[j];
+			r600_context_bo_reloc(ctx,
+					      &block->pm4[block->reloc[id].bo_pm4_index],
+					      block->reloc[id].bo);
+			r600_context_bo_flush(ctx,
+					      block->reloc[id].flush_flags,
+					      block->reloc[id].flush_mask,
+					      block->reloc[id].bo);
+		}
+	}
+	ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
+
+	memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
+	ctx->pm4_cdwords += cp_dwords;
+
+	block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY;
+	block->nreg_dirty = 0;
+	LIST_DELINIT(&block->list);
+}
+
 void r600_context_flush_dest_caches(struct r600_context *ctx)
 {
 	struct r600_bo *cb[8];
@@ -1270,6 +1406,7 @@ void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
 	unsigned ndwords = 7;
 	struct r600_block *dirty_block = NULL;
 	struct r600_block *next_block;
+	uint32_t *pm4;
 
 	if (draw->indices) {
 		ndwords = 11;
@@ -1311,25 +1448,32 @@ void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
 		r600_context_block_emit_dirty(ctx, dirty_block);
 	}
 
+	LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->resource_dirty, list) {
+		r600_context_block_resource_emit_dirty(ctx, dirty_block);
+	}
+
 	/* draw packet */
-	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
-	ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
-	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
-	ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
+	pm4 = &ctx->pm4[ctx->pm4_cdwords];
+
+	pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
+	pm4[1] = draw->vgt_index_type;
+	pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
+	pm4[3] = draw->vgt_num_instances;
 	if (draw->indices) {
-		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
-		ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
-		ctx->pm4[ctx->pm4_cdwords++] = 0;
-		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
-		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
-		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
-		ctx->pm4[ctx->pm4_cdwords++] = 0;
-		r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices);
+		pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
+		pm4[5] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
+		pm4[6] = 0;
+		pm4[7] = draw->vgt_num_indices;
+		pm4[8] = draw->vgt_draw_initiator;
+		pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
+		pm4[10] = 0;
+		r600_context_bo_reloc(ctx, &pm4[10], draw->indices);
 	} else {
-		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
-		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
-		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
+		pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
+		pm4[5] = draw->vgt_num_indices;
+		pm4[6] = draw->vgt_draw_initiator;
 	}
+	ctx->pm4_cdwords += ndwords;
 
 	ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING);
 
@@ -1344,6 +1488,7 @@ void r600_context_flush(struct r600_context *ctx)
 	uint64_t chunk_array[2];
 	unsigned fence;
 	int r;
+	struct r600_block *enable_block = NULL;
 
 	if (!ctx->pm4_cdwords)
 		return;
@@ -1417,15 +1562,21 @@ void r600_context_flush(struct r600_context *ctx)
 	/* set all valid group as dirty so they get reemited on
 	 * next draw command
 	 */
-	for (int i = 0; i < ctx->nblocks; i++) {
-		if (ctx->blocks[i]->status & R600_BLOCK_STATUS_ENABLED) {
-			if(!(ctx->blocks[i]->status & R600_BLOCK_STATUS_DIRTY)) {
-				LIST_ADDTAIL(&ctx->blocks[i]->list,&ctx->dirty);
+	LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
+		if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) {
+			if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
+				LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
+				enable_block->status |= R600_BLOCK_STATUS_DIRTY;
+			}
+		} else {
+			if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) {
+				LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty);
+				enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
 			}
-			ctx->pm4_dirty_cdwords += ctx->blocks[i]->pm4_ndwords + ctx->blocks[i]->pm4_flush_ndwords;
-			ctx->blocks[i]->status |= R600_BLOCK_STATUS_DIRTY;
-			ctx->blocks[i]->nreg_dirty = ctx->blocks[i]->nreg;
 		}
+		ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords + 
+			enable_block->pm4_flush_ndwords;
+		enable_block->nreg_dirty = enable_block->nreg;
 	}
 }
 
@@ -1548,7 +1699,8 @@ static boolean r600_query_result(struct r600_context *ctx, struct r600_query *qu
 	if (!results)
 		return FALSE;
 
-	size = query->num_results * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
+	/* query->num_results contains how many dwords were used for the query */
+	size = query->num_results;
 	for (i = 0; i < size; i += 4) {
 		start = (u64)results[i] | (u64)results[i + 1] << 32;
 		end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
@@ -1586,7 +1738,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
 	}
 
 	if (query->type == PIPE_QUERY_OCCLUSION_COUNTER &&
-	    num_backends > 0 && num_backends < ctx->max_db) {
+	    num_backends > 0) {
 		/* as per info on ZPASS the driver must set the unusued DB top bits */
 		u32 *results;
 		int i;
@@ -1594,7 +1746,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
 		results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_WRITE, NULL);
 		if (results) {
 			memset(results + (query->num_results * 4), 0, ctx->max_db * 4 * 4);
-			
+
 			for (i = num_backends; i < ctx->max_db; i++) {
 				results[(i * 4)+1] = 0x80000000;
 				results[(i * 4)+3] = 0x80000000;
@@ -1602,7 +1754,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
 			r600_bo_unmap(ctx->radeon, query->buffer);
 		}
 	}
-	
+
 	/* emit begin query */
 	if (query->type == PIPE_QUERY_TIME_ELAPSED) {
 		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
index 9be5c358f85..45bc64fcf9a 100644
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -62,10 +62,13 @@ struct radeon {
 	pipe_mutex bo_handles_mutex;
 };
 
+/* these flags are used in register flags and added into block flags */
 #define REG_FLAG_NEED_BO 1
 #define REG_FLAG_DIRTY_ALWAYS 2
 #define REG_FLAG_RV6XX_SBU 4
 #define REG_FLAG_NOT_R600 8
+#define REG_FLAG_ENABLE_ALWAYS 16
+#define BLOCK_FLAG_RESOURCE 32
 
 struct r600_reg {
 	unsigned			offset;
@@ -94,7 +97,8 @@ struct radeon_bo {
 };
 
 struct r600_bo {
-	struct pipe_reference		reference;
+	struct pipe_reference		reference; /* this must be the first member for the r600_bo_reference inline to work */
+	/* DO NOT MOVE THIS ^ */
 	unsigned			size;
 	unsigned			tiling_flags;
 	unsigned			kernel_pitch;
@@ -152,14 +156,15 @@ int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo);
  * r600_hw_context.c
  */
 int r600_context_init_fence(struct r600_context *ctx);
-void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo);
+void r600_context_get_reloc(struct r600_context *ctx, struct r600_bo *rbo);
 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
 				unsigned flush_mask, struct r600_bo *rbo);
 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset);
 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
 			   unsigned opcode, unsigned offset_base);
-void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset);
+void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block);
 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block);
+void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block);
 void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block,
 			      int dirty, int index);
 int r600_setup_block_table(struct r600_context *ctx);
@@ -167,6 +172,21 @@ void r600_context_reg(struct r600_context *ctx,
 		      unsigned offset, unsigned value,
 		      unsigned mask);
 void r600_init_cs(struct r600_context *ctx);
+int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base);
+
+static INLINE void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo)
+{
+	struct radeon_bo *bo = rbo->bo;
+
+	assert(bo != NULL);
+
+	if (!bo->reloc)
+		r600_context_get_reloc(ctx, rbo);
+
+	/* set PKT3 to point to proper reloc */
+	*pm4 = bo->reloc_id;
+}
+
 /*
  * r600_bo.c
  */
@@ -177,7 +197,7 @@ void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo);
  */
 struct r600_bomgr *r600_bomgr_create(struct radeon *radeon, unsigned usecs);
 void r600_bomgr_destroy(struct r600_bomgr *mgr);
-bool r600_bomgr_bo_destroy(struct r600_bomgr *mgr, struct r600_bo *bo);
+boolean r600_bomgr_bo_destroy(struct r600_bomgr *mgr, struct r600_bo *bo);
 void r600_bomgr_bo_init(struct r600_bomgr *mgr, struct r600_bo *bo);
 struct r600_bo *r600_bomgr_bo_create(struct r600_bomgr *mgr,
 					unsigned size,
@@ -210,7 +230,7 @@ static inline void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo)
 /*
  * fence
  */
-static inline bool fence_is_after(unsigned fence, unsigned ofence)
+static inline boolean fence_is_after(unsigned fence, unsigned ofence)
 {
 	/* handle wrap around */
 	if (fence < 0x80000000 && ofence > 0x80000000)
diff --git a/src/gallium/winsys/r600/drm/radeon_pciid.c b/src/gallium/winsys/r600/drm/radeon_pciid.c
index 5c41a10bdba..f54a7c8fe72 100644
--- a/src/gallium/winsys/r600/drm/radeon_pciid.c
+++ b/src/gallium/winsys/r600/drm/radeon_pciid.c
@@ -33,487 +33,8 @@ struct pci_id {
 };
 
 static const struct pci_id radeon_pci_id[] = {
-	{0x1002, 0x3150, CHIP_RV380},
-	{0x1002, 0x3152, CHIP_RV380},
-	{0x1002, 0x3154, CHIP_RV380},
-	{0x1002, 0x3E50, CHIP_RV380},
-	{0x1002, 0x3E54, CHIP_RV380},
-	{0x1002, 0x4136, CHIP_RS100},
-	{0x1002, 0x4137, CHIP_RS200},
-	{0x1002, 0x4144, CHIP_R300},
-	{0x1002, 0x4145, CHIP_R300},
-	{0x1002, 0x4146, CHIP_R300},
-	{0x1002, 0x4147, CHIP_R300},
-	{0x1002, 0x4148, CHIP_R350},
-	{0x1002, 0x4149, CHIP_R350},
-	{0x1002, 0x414A, CHIP_R350},
-	{0x1002, 0x414B, CHIP_R350},
-	{0x1002, 0x4150, CHIP_RV350},
-	{0x1002, 0x4151, CHIP_RV350},
-	{0x1002, 0x4152, CHIP_RV350},
-	{0x1002, 0x4153, CHIP_RV350},
-	{0x1002, 0x4154, CHIP_RV350},
-	{0x1002, 0x4155, CHIP_RV350},
-	{0x1002, 0x4156, CHIP_RV350},
-	{0x1002, 0x4237, CHIP_RS200},
-	{0x1002, 0x4242, CHIP_R200},
-	{0x1002, 0x4243, CHIP_R200},
-	{0x1002, 0x4336, CHIP_RS100},
-	{0x1002, 0x4337, CHIP_RS200},
-	{0x1002, 0x4437, CHIP_RS200},
-	{0x1002, 0x4966, CHIP_RV250},
-	{0x1002, 0x4967, CHIP_RV250},
-	{0x1002, 0x4A48, CHIP_R420},
-	{0x1002, 0x4A49, CHIP_R420},
-	{0x1002, 0x4A4A, CHIP_R420},
-	{0x1002, 0x4A4B, CHIP_R420},
-	{0x1002, 0x4A4C, CHIP_R420},
-	{0x1002, 0x4A4D, CHIP_R420},
-	{0x1002, 0x4A4E, CHIP_R420},
-	{0x1002, 0x4A4F, CHIP_R420},
-	{0x1002, 0x4A50, CHIP_R420},
-	{0x1002, 0x4A54, CHIP_R420},
-	{0x1002, 0x4B48, CHIP_R420},
-	{0x1002, 0x4B49, CHIP_R420},
-	{0x1002, 0x4B4A, CHIP_R420},
-	{0x1002, 0x4B4B, CHIP_R420},
-	{0x1002, 0x4B4C, CHIP_R420},
-	{0x1002, 0x4C57, CHIP_RV200},
-	{0x1002, 0x4C58, CHIP_RV200},
-	{0x1002, 0x4C59, CHIP_RV100},
-	{0x1002, 0x4C5A, CHIP_RV100},
-	{0x1002, 0x4C64, CHIP_RV250},
-	{0x1002, 0x4C66, CHIP_RV250},
-	{0x1002, 0x4C67, CHIP_RV250},
-	{0x1002, 0x4E44, CHIP_R300},
-	{0x1002, 0x4E45, CHIP_R300},
-	{0x1002, 0x4E46, CHIP_R300},
-	{0x1002, 0x4E47, CHIP_R300},
-	{0x1002, 0x4E48, CHIP_R350},
-	{0x1002, 0x4E49, CHIP_R350},
-	{0x1002, 0x4E4A, CHIP_R350},
-	{0x1002, 0x4E4B, CHIP_R350},
-	{0x1002, 0x4E50, CHIP_RV350},
-	{0x1002, 0x4E51, CHIP_RV350},
-	{0x1002, 0x4E52, CHIP_RV350},
-	{0x1002, 0x4E53, CHIP_RV350},
-	{0x1002, 0x4E54, CHIP_RV350},
-	{0x1002, 0x4E56, CHIP_RV350},
-	{0x1002, 0x5144, CHIP_R100},
-	{0x1002, 0x5145, CHIP_R100},
-	{0x1002, 0x5146, CHIP_R100},
-	{0x1002, 0x5147, CHIP_R100},
-	{0x1002, 0x5148, CHIP_R200},
-	{0x1002, 0x514C, CHIP_R200},
-	{0x1002, 0x514D, CHIP_R200},
-	{0x1002, 0x5157, CHIP_RV200},
-	{0x1002, 0x5158, CHIP_RV200},
-	{0x1002, 0x5159, CHIP_RV100},
-	{0x1002, 0x515A, CHIP_RV100},
-	{0x1002, 0x515E, CHIP_RV100},
-	{0x1002, 0x5460, CHIP_RV380},
-	{0x1002, 0x5462, CHIP_RV380},
-	{0x1002, 0x5464, CHIP_RV380},
-	{0x1002, 0x5657, CHIP_RV380},
-	{0x1002, 0x5548, CHIP_R423},
-	{0x1002, 0x5549, CHIP_R423},
-	{0x1002, 0x554A, CHIP_R423},
-	{0x1002, 0x554B, CHIP_R423},
-	{0x1002, 0x554C, CHIP_R423},
-	{0x1002, 0x554D, CHIP_R423},
-	{0x1002, 0x554E, CHIP_R423},
-	{0x1002, 0x554F, CHIP_R423},
-	{0x1002, 0x5550, CHIP_R423},
-	{0x1002, 0x5551, CHIP_R423},
-	{0x1002, 0x5552, CHIP_R423},
-	{0x1002, 0x5554, CHIP_R423},
-	{0x1002, 0x564A, CHIP_RV410},
-	{0x1002, 0x564B, CHIP_RV410},
-	{0x1002, 0x564F, CHIP_RV410},
-	{0x1002, 0x5652, CHIP_RV410},
-	{0x1002, 0x5653, CHIP_RV410},
-	{0x1002, 0x5834, CHIP_RS300},
-	{0x1002, 0x5835, CHIP_RS300},
-	{0x1002, 0x5954, CHIP_RS480},
-	{0x1002, 0x5955, CHIP_RS480},
-	{0x1002, 0x5974, CHIP_RS480},
-	{0x1002, 0x5975, CHIP_RS480},
-	{0x1002, 0x5960, CHIP_RV280},
-	{0x1002, 0x5961, CHIP_RV280},
-	{0x1002, 0x5962, CHIP_RV280},
-	{0x1002, 0x5964, CHIP_RV280},
-	{0x1002, 0x5965, CHIP_RV280},
-	{0x1002, 0x5969, CHIP_RV100},
-	{0x1002, 0x5a41, CHIP_RS400},
-	{0x1002, 0x5a42, CHIP_RS400},
-	{0x1002, 0x5a61, CHIP_RS400},
-	{0x1002, 0x5a62, CHIP_RS400},
-	{0x1002, 0x5b60, CHIP_RV380},
-	{0x1002, 0x5b62, CHIP_RV380},
-	{0x1002, 0x5b63, CHIP_RV380},
-	{0x1002, 0x5b64, CHIP_RV380},
-	{0x1002, 0x5b65, CHIP_RV380},
-	{0x1002, 0x5c61, CHIP_RV280},
-	{0x1002, 0x5c63, CHIP_RV280},
-	{0x1002, 0x5d48, CHIP_R423},
-	{0x1002, 0x5d49, CHIP_R423},
-	{0x1002, 0x5d4a, CHIP_R423},
-	{0x1002, 0x5d4c, CHIP_R423},
-	{0x1002, 0x5d4d, CHIP_R423},
-	{0x1002, 0x5d4e, CHIP_R423},
-	{0x1002, 0x5d4f, CHIP_R423},
-	{0x1002, 0x5d50, CHIP_R423},
-	{0x1002, 0x5d52, CHIP_R423},
-	{0x1002, 0x5d57, CHIP_R423},
-	{0x1002, 0x5e48, CHIP_RV410},
-	{0x1002, 0x5e4a, CHIP_RV410},
-	{0x1002, 0x5e4b, CHIP_RV410},
-	{0x1002, 0x5e4c, CHIP_RV410},
-	{0x1002, 0x5e4d, CHIP_RV410},
-	{0x1002, 0x5e4f, CHIP_RV410},
-	{0x1002, 0x6880, CHIP_CYPRESS},
-	{0x1002, 0x6888, CHIP_CYPRESS},
-	{0x1002, 0x6889, CHIP_CYPRESS},
-	{0x1002, 0x688A, CHIP_CYPRESS},
-	{0x1002, 0x6898, CHIP_CYPRESS},
-	{0x1002, 0x6899, CHIP_CYPRESS},
-	{0x1002, 0x689b, CHIP_CYPRESS},
-	{0x1002, 0x689c, CHIP_HEMLOCK},
-	{0x1002, 0x689d, CHIP_HEMLOCK},
-	{0x1002, 0x689e, CHIP_CYPRESS},
-	{0x1002, 0x68a0, CHIP_JUNIPER},
-	{0x1002, 0x68a1, CHIP_JUNIPER},
-	{0x1002, 0x68a8, CHIP_JUNIPER},
-	{0x1002, 0x68a9, CHIP_JUNIPER},
-	{0x1002, 0x68b0, CHIP_JUNIPER},
-	{0x1002, 0x68b8, CHIP_JUNIPER},
-	{0x1002, 0x68b9, CHIP_JUNIPER},
-	{0x1002, 0x68ba, CHIP_JUNIPER},
-	{0x1002, 0x68be, CHIP_JUNIPER},
-	{0x1002, 0x68bf, CHIP_JUNIPER},
-	{0x1002, 0x68c0, CHIP_REDWOOD},
-	{0x1002, 0x68c1, CHIP_REDWOOD},
-	{0x1002, 0x68c8, CHIP_REDWOOD},
-	{0x1002, 0x68c9, CHIP_REDWOOD},
-	{0x1002, 0x68d8, CHIP_REDWOOD},
-	{0x1002, 0x68d9, CHIP_REDWOOD},
-	{0x1002, 0x68da, CHIP_REDWOOD},
-	{0x1002, 0x68de, CHIP_REDWOOD},
-	{0x1002, 0x68e0, CHIP_CEDAR},
-	{0x1002, 0x68e1, CHIP_CEDAR},
-	{0x1002, 0x68e4, CHIP_CEDAR},
-	{0x1002, 0x68e5, CHIP_CEDAR},
-	{0x1002, 0x68e8, CHIP_CEDAR},
-	{0x1002, 0x68e9, CHIP_CEDAR},
-	{0x1002, 0x68f1, CHIP_CEDAR},
-	{0x1002, 0x68f2, CHIP_CEDAR},
-	{0x1002, 0x68f8, CHIP_CEDAR},
-	{0x1002, 0x68f9, CHIP_CEDAR},
-	{0x1002, 0x68fe, CHIP_CEDAR},
-	{0x1002, 0x7100, CHIP_R520},
-	{0x1002, 0x7101, CHIP_R520},
-	{0x1002, 0x7102, CHIP_R520},
-	{0x1002, 0x7103, CHIP_R520},
-	{0x1002, 0x7104, CHIP_R520},
-	{0x1002, 0x7105, CHIP_R520},
-	{0x1002, 0x7106, CHIP_R520},
-	{0x1002, 0x7108, CHIP_R520},
-	{0x1002, 0x7109, CHIP_R520},
-	{0x1002, 0x710A, CHIP_R520},
-	{0x1002, 0x710B, CHIP_R520},
-	{0x1002, 0x710C, CHIP_R520},
-	{0x1002, 0x710E, CHIP_R520},
-	{0x1002, 0x710F, CHIP_R520},
-	{0x1002, 0x7140, CHIP_RV515},
-	{0x1002, 0x7141, CHIP_RV515},
-	{0x1002, 0x7142, CHIP_RV515},
-	{0x1002, 0x7143, CHIP_RV515},
-	{0x1002, 0x7144, CHIP_RV515},
-	{0x1002, 0x7145, CHIP_RV515},
-	{0x1002, 0x7146, CHIP_RV515},
-	{0x1002, 0x7147, CHIP_RV515},
-	{0x1002, 0x7149, CHIP_RV515},
-	{0x1002, 0x714A, CHIP_RV515},
-	{0x1002, 0x714B, CHIP_RV515},
-	{0x1002, 0x714C, CHIP_RV515},
-	{0x1002, 0x714D, CHIP_RV515},
-	{0x1002, 0x714E, CHIP_RV515},
-	{0x1002, 0x714F, CHIP_RV515},
-	{0x1002, 0x7151, CHIP_RV515},
-	{0x1002, 0x7152, CHIP_RV515},
-	{0x1002, 0x7153, CHIP_RV515},
-	{0x1002, 0x715E, CHIP_RV515},
-	{0x1002, 0x715F, CHIP_RV515},
-	{0x1002, 0x7180, CHIP_RV515},
-	{0x1002, 0x7181, CHIP_RV515},
-	{0x1002, 0x7183, CHIP_RV515},
-	{0x1002, 0x7186, CHIP_RV515},
-	{0x1002, 0x7187, CHIP_RV515},
-	{0x1002, 0x7188, CHIP_RV515},
-	{0x1002, 0x718A, CHIP_RV515},
-	{0x1002, 0x718B, CHIP_RV515},
-	{0x1002, 0x718C, CHIP_RV515},
-	{0x1002, 0x718D, CHIP_RV515},
-	{0x1002, 0x718F, CHIP_RV515},
-	{0x1002, 0x7193, CHIP_RV515},
-	{0x1002, 0x7196, CHIP_RV515},
-	{0x1002, 0x719B, CHIP_RV515},
-	{0x1002, 0x719F, CHIP_RV515},
-	{0x1002, 0x71C0, CHIP_RV530},
-	{0x1002, 0x71C1, CHIP_RV530},
-	{0x1002, 0x71C2, CHIP_RV530},
-	{0x1002, 0x71C3, CHIP_RV530},
-	{0x1002, 0x71C4, CHIP_RV530},
-	{0x1002, 0x71C5, CHIP_RV530},
-	{0x1002, 0x71C6, CHIP_RV530},
-	{0x1002, 0x71C7, CHIP_RV530},
-	{0x1002, 0x71CD, CHIP_RV530},
-	{0x1002, 0x71CE, CHIP_RV530},
-	{0x1002, 0x71D2, CHIP_RV530},
-	{0x1002, 0x71D4, CHIP_RV530},
-	{0x1002, 0x71D5, CHIP_RV530},
-	{0x1002, 0x71D6, CHIP_RV530},
-	{0x1002, 0x71DA, CHIP_RV530},
-	{0x1002, 0x71DE, CHIP_RV530},
-	{0x1002, 0x7200, CHIP_RV515},
-	{0x1002, 0x7210, CHIP_RV515},
-	{0x1002, 0x7211, CHIP_RV515},
-	{0x1002, 0x7240, CHIP_R580},
-	{0x1002, 0x7243, CHIP_R580},
-	{0x1002, 0x7244, CHIP_R580},
-	{0x1002, 0x7245, CHIP_R580},
-	{0x1002, 0x7246, CHIP_R580},
-	{0x1002, 0x7247, CHIP_R580},
-	{0x1002, 0x7248, CHIP_R580},
-	{0x1002, 0x7249, CHIP_R580},
-	{0x1002, 0x724A, CHIP_R580},
-	{0x1002, 0x724B, CHIP_R580},
-	{0x1002, 0x724C, CHIP_R580},
-	{0x1002, 0x724D, CHIP_R580},
-	{0x1002, 0x724E, CHIP_R580},
-	{0x1002, 0x724F, CHIP_R580},
-	{0x1002, 0x7280, CHIP_RV570},
-	{0x1002, 0x7281, CHIP_RV560},
-	{0x1002, 0x7283, CHIP_RV560},
-	{0x1002, 0x7284, CHIP_R580},
-	{0x1002, 0x7287, CHIP_RV560},
-	{0x1002, 0x7288, CHIP_RV570},
-	{0x1002, 0x7289, CHIP_RV570},
-	{0x1002, 0x728B, CHIP_RV570},
-	{0x1002, 0x728C, CHIP_RV570},
-	{0x1002, 0x7290, CHIP_RV560},
-	{0x1002, 0x7291, CHIP_RV560},
-	{0x1002, 0x7293, CHIP_RV560},
-	{0x1002, 0x7297, CHIP_RV560},
-	{0x1002, 0x7834, CHIP_RS300},
-	{0x1002, 0x7835, CHIP_RS300},
-	{0x1002, 0x791e, CHIP_RS690},
-	{0x1002, 0x791f, CHIP_RS690},
-	{0x1002, 0x793f, CHIP_RS600},
-	{0x1002, 0x7941, CHIP_RS600},
-	{0x1002, 0x7942, CHIP_RS600},
-	{0x1002, 0x796c, CHIP_RS740},
-	{0x1002, 0x796d, CHIP_RS740},
-	{0x1002, 0x796e, CHIP_RS740},
-	{0x1002, 0x796f, CHIP_RS740},
-	{0x1002, 0x9400, CHIP_R600},
-	{0x1002, 0x9401, CHIP_R600},
-	{0x1002, 0x9402, CHIP_R600},
-	{0x1002, 0x9403, CHIP_R600},
-	{0x1002, 0x9405, CHIP_R600},
-	{0x1002, 0x940A, CHIP_R600},
-	{0x1002, 0x940B, CHIP_R600},
-	{0x1002, 0x940F, CHIP_R600},
-	{0x1002, 0x94A0, CHIP_RV740},
-	{0x1002, 0x94A1, CHIP_RV740},
-	{0x1002, 0x94A3, CHIP_RV740},
-	{0x1002, 0x94B1, CHIP_RV740},
-	{0x1002, 0x94B3, CHIP_RV740},
-	{0x1002, 0x94B4, CHIP_RV740},
-	{0x1002, 0x94B5, CHIP_RV740},
-	{0x1002, 0x94B9, CHIP_RV740},
-	{0x1002, 0x9440, CHIP_RV770},
-	{0x1002, 0x9441, CHIP_RV770},
-	{0x1002, 0x9442, CHIP_RV770},
-	{0x1002, 0x9443, CHIP_RV770},
-	{0x1002, 0x9444, CHIP_RV770},
-	{0x1002, 0x9446, CHIP_RV770},
-	{0x1002, 0x944A, CHIP_RV770},
-	{0x1002, 0x944B, CHIP_RV770},
-	{0x1002, 0x944C, CHIP_RV770},
-	{0x1002, 0x944E, CHIP_RV770},
-	{0x1002, 0x9450, CHIP_RV770},
-	{0x1002, 0x9452, CHIP_RV770},
-	{0x1002, 0x9456, CHIP_RV770},
-	{0x1002, 0x945A, CHIP_RV770},
-	{0x1002, 0x945B, CHIP_RV770},
-	{0x1002, 0x9460, CHIP_RV770},
-	{0x1002, 0x9462, CHIP_RV770},
-	{0x1002, 0x946A, CHIP_RV770},
-	{0x1002, 0x946B, CHIP_RV770},
-	{0x1002, 0x947A, CHIP_RV770},
-	{0x1002, 0x947B, CHIP_RV770},
-	{0x1002, 0x9480, CHIP_RV730},
-	{0x1002, 0x9487, CHIP_RV730},
-	{0x1002, 0x9488, CHIP_RV730},
-	{0x1002, 0x9489, CHIP_RV730},
-	{0x1002, 0x948F, CHIP_RV730},
-	{0x1002, 0x9490, CHIP_RV730},
-	{0x1002, 0x9491, CHIP_RV730},
-	{0x1002, 0x9495, CHIP_RV730},
-	{0x1002, 0x9498, CHIP_RV730},
-	{0x1002, 0x949C, CHIP_RV730},
-	{0x1002, 0x949E, CHIP_RV730},
-	{0x1002, 0x949F, CHIP_RV730},
-	{0x1002, 0x94C0, CHIP_RV610},
-	{0x1002, 0x94C1, CHIP_RV610},
-	{0x1002, 0x94C3, CHIP_RV610},
-	{0x1002, 0x94C4, CHIP_RV610},
-	{0x1002, 0x94C5, CHIP_RV610},
-	{0x1002, 0x94C6, CHIP_RV610},
-	{0x1002, 0x94C7, CHIP_RV610},
-	{0x1002, 0x94C8, CHIP_RV610},
-	{0x1002, 0x94C9, CHIP_RV610},
-	{0x1002, 0x94CB, CHIP_RV610},
-	{0x1002, 0x94CC, CHIP_RV610},
-	{0x1002, 0x94CD, CHIP_RV610},
-	{0x1002, 0x9500, CHIP_RV670},
-	{0x1002, 0x9501, CHIP_RV670},
-	{0x1002, 0x9504, CHIP_RV670},
-	{0x1002, 0x9505, CHIP_RV670},
-	{0x1002, 0x9506, CHIP_RV670},
-	{0x1002, 0x9507, CHIP_RV670},
-	{0x1002, 0x9508, CHIP_RV670},
-	{0x1002, 0x9509, CHIP_RV670},
-	{0x1002, 0x950F, CHIP_RV670},
-	{0x1002, 0x9511, CHIP_RV670},
-	{0x1002, 0x9515, CHIP_RV670},
-	{0x1002, 0x9517, CHIP_RV670},
-	{0x1002, 0x9519, CHIP_RV670},
-	{0x1002, 0x9540, CHIP_RV710},
-	{0x1002, 0x9541, CHIP_RV710},
-	{0x1002, 0x9542, CHIP_RV710},
-	{0x1002, 0x954E, CHIP_RV710},
-	{0x1002, 0x954F, CHIP_RV710},
-	{0x1002, 0x9552, CHIP_RV710},
-	{0x1002, 0x9553, CHIP_RV710},
-	{0x1002, 0x9555, CHIP_RV710},
-	{0x1002, 0x9557, CHIP_RV710},
-	{0x1002, 0x9580, CHIP_RV630},
-	{0x1002, 0x9581, CHIP_RV630},
-	{0x1002, 0x9583, CHIP_RV630},
-	{0x1002, 0x9586, CHIP_RV630},
-	{0x1002, 0x9587, CHIP_RV630},
-	{0x1002, 0x9588, CHIP_RV630},
-	{0x1002, 0x9589, CHIP_RV630},
-	{0x1002, 0x958A, CHIP_RV630},
-	{0x1002, 0x958B, CHIP_RV630},
-	{0x1002, 0x958C, CHIP_RV630},
-	{0x1002, 0x958D, CHIP_RV630},
-	{0x1002, 0x958E, CHIP_RV630},
-	{0x1002, 0x958F, CHIP_RV630},
-	{0x1002, 0x9590, CHIP_RV635},
-	{0x1002, 0x9591, CHIP_RV635},
-	{0x1002, 0x9593, CHIP_RV635},
-	{0x1002, 0x9595, CHIP_RV635},
-	{0x1002, 0x9596, CHIP_RV635},
-	{0x1002, 0x9597, CHIP_RV635},
-	{0x1002, 0x9598, CHIP_RV635},
-	{0x1002, 0x9599, CHIP_RV635},
-	{0x1002, 0x959B, CHIP_RV635},
-	{0x1002, 0x95C0, CHIP_RV620},
-	{0x1002, 0x95C2, CHIP_RV620},
-	{0x1002, 0x95C4, CHIP_RV620},
-	{0x1002, 0x95C5, CHIP_RV620},
-	{0x1002, 0x95C6, CHIP_RV620},
-	{0x1002, 0x95C7, CHIP_RV620},
-	{0x1002, 0x95C9, CHIP_RV620},
-	{0x1002, 0x95CC, CHIP_RV620},
-	{0x1002, 0x95CD, CHIP_RV620},
-	{0x1002, 0x95CE, CHIP_RV620},
-	{0x1002, 0x95CF, CHIP_RV620},
-	{0x1002, 0x9610, CHIP_RS780},
-	{0x1002, 0x9611, CHIP_RS780},
-	{0x1002, 0x9612, CHIP_RS780},
-	{0x1002, 0x9613, CHIP_RS780},
-	{0x1002, 0x9614, CHIP_RS780},
-	{0x1002, 0x9615, CHIP_RS780},
-	{0x1002, 0x9616, CHIP_RS780},
-	{0x1002, 0x9640, CHIP_SUMO},
-	{0x1002, 0x9641, CHIP_SUMO},
-	{0x1002, 0x9642, CHIP_SUMO2},
-	{0x1002, 0x9643, CHIP_SUMO2},
-	{0x1002, 0x9644, CHIP_SUMO2},
-	{0x1002, 0x9645, CHIP_SUMO2},
-	{0x1002, 0x9647, CHIP_SUMO},
-	{0x1002, 0x9648, CHIP_SUMO},
-	{0x1002, 0x964a, CHIP_SUMO},
-	{0x1002, 0x964e, CHIP_SUMO},
-	{0x1002, 0x964f, CHIP_SUMO},
-	{0x1002, 0x9710, CHIP_RS880},
-	{0x1002, 0x9711, CHIP_RS880},
-	{0x1002, 0x9712, CHIP_RS880},
-	{0x1002, 0x9713, CHIP_RS880},
-	{0x1002, 0x9714, CHIP_RS880},
-	{0x1002, 0x9715, CHIP_RS880},
-	{0x1002, 0x9802, CHIP_PALM},
-	{0x1002, 0x9803, CHIP_PALM},
-	{0x1002, 0x9804, CHIP_PALM},
-	{0x1002, 0x9805, CHIP_PALM},
-	{0x1002, 0x9806, CHIP_PALM},
-	{0x1002, 0x9807, CHIP_PALM},
-	{0x1002, 0x6700, CHIP_CAYMAN},
-	{0x1002, 0x6701, CHIP_CAYMAN},
-	{0x1002, 0x6702, CHIP_CAYMAN},
-	{0x1002, 0x6703, CHIP_CAYMAN},
-	{0x1002, 0x6704, CHIP_CAYMAN},
-	{0x1002, 0x6705, CHIP_CAYMAN},
-	{0x1002, 0x6706, CHIP_CAYMAN},
-	{0x1002, 0x6707, CHIP_CAYMAN},
-	{0x1002, 0x6708, CHIP_CAYMAN},
-	{0x1002, 0x6709, CHIP_CAYMAN},
-	{0x1002, 0x6718, CHIP_CAYMAN},
-	{0x1002, 0x6719, CHIP_CAYMAN},
-	{0x1002, 0x671C, CHIP_CAYMAN},
-	{0x1002, 0x671D, CHIP_CAYMAN},
-	{0x1002, 0x671F, CHIP_CAYMAN},
-	{0x1002, 0x6720, CHIP_BARTS},
-	{0x1002, 0x6721, CHIP_BARTS},
-	{0x1002, 0x6722, CHIP_BARTS},
-	{0x1002, 0x6723, CHIP_BARTS},
-	{0x1002, 0x6724, CHIP_BARTS},
-	{0x1002, 0x6725, CHIP_BARTS},
-	{0x1002, 0x6726, CHIP_BARTS},
-	{0x1002, 0x6727, CHIP_BARTS},
-	{0x1002, 0x6728, CHIP_BARTS},
-	{0x1002, 0x6729, CHIP_BARTS},
-	{0x1002, 0x6738, CHIP_BARTS},
-	{0x1002, 0x6739, CHIP_BARTS},
-	{0x1002, 0x673e, CHIP_BARTS},
-	{0x1002, 0x6740, CHIP_TURKS},
-	{0x1002, 0x6741, CHIP_TURKS},
-	{0x1002, 0x6742, CHIP_TURKS},
-	{0x1002, 0x6743, CHIP_TURKS},
-	{0x1002, 0x6744, CHIP_TURKS},
-	{0x1002, 0x6745, CHIP_TURKS},
-	{0x1002, 0x6746, CHIP_TURKS},
-	{0x1002, 0x6747, CHIP_TURKS},
-	{0x1002, 0x6748, CHIP_TURKS},
-	{0x1002, 0x6749, CHIP_TURKS},
-	{0x1002, 0x6750, CHIP_TURKS},
-	{0x1002, 0x6758, CHIP_TURKS},
-	{0x1002, 0x6759, CHIP_TURKS},
-	{0x1002, 0x6760, CHIP_CAICOS},
-	{0x1002, 0x6761, CHIP_CAICOS},
-	{0x1002, 0x6762, CHIP_CAICOS},
-	{0x1002, 0x6763, CHIP_CAICOS},
-	{0x1002, 0x6764, CHIP_CAICOS},
-	{0x1002, 0x6765, CHIP_CAICOS},
-	{0x1002, 0x6766, CHIP_CAICOS},
-	{0x1002, 0x6767, CHIP_CAICOS},
-	{0x1002, 0x6768, CHIP_CAICOS},
-	{0x1002, 0x6770, CHIP_CAICOS},
-	{0x1002, 0x6779, CHIP_CAICOS},
+#define CHIPSET(chip, name, family) { 0x1002, chip, CHIP_##family },
+#include "pci_ids/r600_pci_ids.h"
 	{0, 0},
 };
 
diff --git a/src/gallium/winsys/radeon/drm/Makefile b/src/gallium/winsys/radeon/drm/Makefile
index d44b7c14250..913e6ad186a 100644
--- a/src/gallium/winsys/radeon/drm/Makefile
+++ b/src/gallium/winsys/radeon/drm/Makefile
@@ -9,7 +9,8 @@ C_SOURCES = \
 	radeon_drm_cs.c \
 	radeon_drm_winsys.c
 
-LIBRARY_INCLUDES = $(shell pkg-config libdrm --cflags-only-I)
+LIBRARY_INCLUDES = -I$(TOP)/include \
+		   $(shell pkg-config libdrm --cflags-only-I)
 
 include ../../../Makefile.template
 
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_public.h b/src/gallium/winsys/radeon/drm/radeon_drm_public.h
index 76d9dda422d..4fc62f1a400 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_public.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_public.h
@@ -7,216 +7,4 @@ struct radeon_winsys;
 
 struct radeon_winsys *radeon_drm_winsys_create(int fd);
 
-static INLINE boolean is_r3xx(int pciid)
-{
-      switch (pciid) {
-      case 0x4144: /* PCI_CHIP_R300_AD */
-      case 0x4145: /* PCI_CHIP_R300_AE */
-      case 0x4146: /* PCI_CHIP_R300_AF */
-      case 0x4147: /* PCI_CHIP_R300_AG */
-      case 0x4E44: /* PCI_CHIP_R300_ND */
-      case 0x4E45: /* PCI_CHIP_R300_NE */
-      case 0x4E46: /* PCI_CHIP_R300_NF */
-      case 0x4E47: /* PCI_CHIP_R300_NG */
-      case 0x4E48: /* PCI_CHIP_R350_NH */
-      case 0x4E49: /* PCI_CHIP_R350_NI */
-      case 0x4E4B: /* PCI_CHIP_R350_NK */
-      case 0x4148: /* PCI_CHIP_R350_AH */
-      case 0x4149: /* PCI_CHIP_R350_AI */
-      case 0x414A: /* PCI_CHIP_R350_AJ */
-      case 0x414B: /* PCI_CHIP_R350_AK */
-      case 0x4E4A: /* PCI_CHIP_R360_NJ */
-      case 0x4150: /* PCI_CHIP_RV350_AP */
-      case 0x4151: /* PCI_CHIP_RV350_AQ */
-      case 0x4152: /* PCI_CHIP_RV350_AR */
-      case 0x4153: /* PCI_CHIP_RV350_AS */
-      case 0x4154: /* PCI_CHIP_RV350_AT */
-      case 0x4155: /* PCI_CHIP_RV350_AU */
-      case 0x4156: /* PCI_CHIP_RV350_AV */
-      case 0x4E50: /* PCI_CHIP_RV350_NP */
-      case 0x4E51: /* PCI_CHIP_RV350_NQ */
-      case 0x4E52: /* PCI_CHIP_RV350_NR */
-      case 0x4E53: /* PCI_CHIP_RV350_NS */
-      case 0x4E54: /* PCI_CHIP_RV350_NT */
-      case 0x4E56: /* PCI_CHIP_RV350_NV */
-      case 0x5460: /* PCI_CHIP_RV370_5460 */
-      case 0x5462: /* PCI_CHIP_RV370_5462 */
-      case 0x5464: /* PCI_CHIP_RV370_5464 */
-      case 0x5B60: /* PCI_CHIP_RV370_5B60 */
-      case 0x5B62: /* PCI_CHIP_RV370_5B62 */
-      case 0x5B63: /* PCI_CHIP_RV370_5B63 */
-      case 0x5B64: /* PCI_CHIP_RV370_5B64 */
-      case 0x5B65: /* PCI_CHIP_RV370_5B65 */
-      case 0x3150: /* PCI_CHIP_RV380_3150 */
-      case 0x3152: /* PCI_CHIP_RV380_3152 */
-      case 0x3154: /* PCI_CHIP_RV380_3154 */
-      case 0x3155: /* PCI_CHIP_RV380_3155 */
-      case 0x3E50: /* PCI_CHIP_RV380_3E50 */
-      case 0x3E54: /* PCI_CHIP_RV380_3E54 */
-      case 0x4A48: /* PCI_CHIP_R420_JH */
-      case 0x4A49: /* PCI_CHIP_R420_JI */
-      case 0x4A4A: /* PCI_CHIP_R420_JJ */
-      case 0x4A4B: /* PCI_CHIP_R420_JK */
-      case 0x4A4C: /* PCI_CHIP_R420_JL */
-      case 0x4A4D: /* PCI_CHIP_R420_JM */
-      case 0x4A4E: /* PCI_CHIP_R420_JN */
-      case 0x4A4F: /* PCI_CHIP_R420_JO */
-      case 0x4A50: /* PCI_CHIP_R420_JP */
-      case 0x4A54: /* PCI_CHIP_R420_JT */
-      case 0x5548: /* PCI_CHIP_R423_UH */
-      case 0x5549: /* PCI_CHIP_R423_UI */
-      case 0x554A: /* PCI_CHIP_R423_UJ */
-      case 0x554B: /* PCI_CHIP_R423_UK */
-      case 0x5550: /* PCI_CHIP_R423_5550 */
-      case 0x5551: /* PCI_CHIP_R423_UQ */
-      case 0x5552: /* PCI_CHIP_R423_UR */
-      case 0x5554: /* PCI_CHIP_R423_UT */
-      case 0x5D57: /* PCI_CHIP_R423_5D57 */
-      case 0x554C: /* PCI_CHIP_R430_554C */
-      case 0x554D: /* PCI_CHIP_R430_554D */
-      case 0x554E: /* PCI_CHIP_R430_554E */
-      case 0x554F: /* PCI_CHIP_R430_554F */
-      case 0x5D48: /* PCI_CHIP_R430_5D48 */
-      case 0x5D49: /* PCI_CHIP_R430_5D49 */
-      case 0x5D4A: /* PCI_CHIP_R430_5D4A */
-      case 0x5D4C: /* PCI_CHIP_R480_5D4C */
-      case 0x5D4D: /* PCI_CHIP_R480_5D4D */
-      case 0x5D4E: /* PCI_CHIP_R480_5D4E */
-      case 0x5D4F: /* PCI_CHIP_R480_5D4F */
-      case 0x5D50: /* PCI_CHIP_R480_5D50 */
-      case 0x5D52: /* PCI_CHIP_R480_5D52 */
-      case 0x4B49: /* PCI_CHIP_R481_4B49 */
-      case 0x4B4A: /* PCI_CHIP_R481_4B4A */
-      case 0x4B4B: /* PCI_CHIP_R481_4B4B */
-      case 0x4B4C: /* PCI_CHIP_R481_4B4C */
-      case 0x564A: /* PCI_CHIP_RV410_564A */
-      case 0x564B: /* PCI_CHIP_RV410_564B */
-      case 0x564F: /* PCI_CHIP_RV410_564F */
-      case 0x5652: /* PCI_CHIP_RV410_5652 */
-      case 0x5653: /* PCI_CHIP_RV410_5653 */
-      case 0x5657: /* PCI_CHIP_RV410_5657 */
-      case 0x5E48: /* PCI_CHIP_RV410_5E48 */
-      case 0x5E4A: /* PCI_CHIP_RV410_5E4A */
-      case 0x5E4B: /* PCI_CHIP_RV410_5E4B */
-      case 0x5E4C: /* PCI_CHIP_RV410_5E4C */
-      case 0x5E4D: /* PCI_CHIP_RV410_5E4D */
-      case 0x5E4F: /* PCI_CHIP_RV410_5E4F */
-      case 0x5A41: /* PCI_CHIP_RS400_5A41 */
-      case 0x5A42: /* PCI_CHIP_RS400_5A42 */
-      case 0x5A61: /* PCI_CHIP_RC410_5A61 */
-      case 0x5A62: /* PCI_CHIP_RC410_5A62 */
-      case 0x5954: /* PCI_CHIP_RS480_5954 */
-      case 0x5955: /* PCI_CHIP_RS480_5955 */
-      case 0x5974: /* PCI_CHIP_RS482_5974 */
-      case 0x5975: /* PCI_CHIP_RS482_5975 */
-      case 0x7100: /* PCI_CHIP_R520_7100 */
-      case 0x7101: /* PCI_CHIP_R520_7101 */
-      case 0x7102: /* PCI_CHIP_R520_7102 */
-      case 0x7103: /* PCI_CHIP_R520_7103 */
-      case 0x7104: /* PCI_CHIP_R520_7104 */
-      case 0x7105: /* PCI_CHIP_R520_7105 */
-      case 0x7106: /* PCI_CHIP_R520_7106 */
-      case 0x7108: /* PCI_CHIP_R520_7108 */
-      case 0x7109: /* PCI_CHIP_R520_7109 */
-      case 0x710A: /* PCI_CHIP_R520_710A */
-      case 0x710B: /* PCI_CHIP_R520_710B */
-      case 0x710C: /* PCI_CHIP_R520_710C */
-      case 0x710E: /* PCI_CHIP_R520_710E */
-      case 0x710F: /* PCI_CHIP_R520_710F */
-      case 0x7140: /* PCI_CHIP_RV515_7140 */
-      case 0x7141: /* PCI_CHIP_RV515_7141 */
-      case 0x7142: /* PCI_CHIP_RV515_7142 */
-      case 0x7143: /* PCI_CHIP_RV515_7143 */
-      case 0x7144: /* PCI_CHIP_RV515_7144 */
-      case 0x7145: /* PCI_CHIP_RV515_7145 */
-      case 0x7146: /* PCI_CHIP_RV515_7146 */
-      case 0x7147: /* PCI_CHIP_RV515_7147 */
-      case 0x7149: /* PCI_CHIP_RV515_7149 */
-      case 0x714A: /* PCI_CHIP_RV515_714A */
-      case 0x714B: /* PCI_CHIP_RV515_714B */
-      case 0x714C: /* PCI_CHIP_RV515_714C */
-      case 0x714D: /* PCI_CHIP_RV515_714D */
-      case 0x714E: /* PCI_CHIP_RV515_714E */
-      case 0x714F: /* PCI_CHIP_RV515_714F */
-      case 0x7151: /* PCI_CHIP_RV515_7151 */
-      case 0x7152: /* PCI_CHIP_RV515_7152 */
-      case 0x7153: /* PCI_CHIP_RV515_7153 */
-      case 0x715E: /* PCI_CHIP_RV515_715E */
-      case 0x715F: /* PCI_CHIP_RV515_715F */
-      case 0x7180: /* PCI_CHIP_RV515_7180 */
-      case 0x7181: /* PCI_CHIP_RV515_7181 */
-      case 0x7183: /* PCI_CHIP_RV515_7183 */
-      case 0x7186: /* PCI_CHIP_RV515_7186 */
-      case 0x7187: /* PCI_CHIP_RV515_7187 */
-      case 0x7188: /* PCI_CHIP_RV515_7188 */
-      case 0x718A: /* PCI_CHIP_RV515_718A */
-      case 0x718B: /* PCI_CHIP_RV515_718B */
-      case 0x718C: /* PCI_CHIP_RV515_718C */
-      case 0x718D: /* PCI_CHIP_RV515_718D */
-      case 0x718F: /* PCI_CHIP_RV515_718F */
-      case 0x7193: /* PCI_CHIP_RV515_7193 */
-      case 0x7196: /* PCI_CHIP_RV515_7196 */
-      case 0x719B: /* PCI_CHIP_RV515_719B */
-      case 0x719F: /* PCI_CHIP_RV515_719F */
-      case 0x7200: /* PCI_CHIP_RV515_7200 */
-      case 0x7210: /* PCI_CHIP_RV515_7210 */
-      case 0x7211: /* PCI_CHIP_RV515_7211 */
-      case 0x71C0: /* PCI_CHIP_RV530_71C0 */
-      case 0x71C1: /* PCI_CHIP_RV530_71C1 */
-      case 0x71C2: /* PCI_CHIP_RV530_71C2 */
-      case 0x71C3: /* PCI_CHIP_RV530_71C3 */
-      case 0x71C4: /* PCI_CHIP_RV530_71C4 */
-      case 0x71C5: /* PCI_CHIP_RV530_71C5 */
-      case 0x71C6: /* PCI_CHIP_RV530_71C6 */
-      case 0x71C7: /* PCI_CHIP_RV530_71C7 */
-      case 0x71CD: /* PCI_CHIP_RV530_71CD */
-      case 0x71CE: /* PCI_CHIP_RV530_71CE */
-      case 0x71D2: /* PCI_CHIP_RV530_71D2 */
-      case 0x71D4: /* PCI_CHIP_RV530_71D4 */
-      case 0x71D5: /* PCI_CHIP_RV530_71D5 */
-      case 0x71D6: /* PCI_CHIP_RV530_71D6 */
-      case 0x71DA: /* PCI_CHIP_RV530_71DA */
-      case 0x71DE: /* PCI_CHIP_RV530_71DE */
-      case 0x7281: /* PCI_CHIP_RV560_7281 */
-      case 0x7283: /* PCI_CHIP_RV560_7283 */
-      case 0x7287: /* PCI_CHIP_RV560_7287 */
-      case 0x7290: /* PCI_CHIP_RV560_7290 */
-      case 0x7291: /* PCI_CHIP_RV560_7291 */
-      case 0x7293: /* PCI_CHIP_RV560_7293 */
-      case 0x7297: /* PCI_CHIP_RV560_7297 */
-      case 0x7280: /* PCI_CHIP_RV570_7280 */
-      case 0x7288: /* PCI_CHIP_RV570_7288 */
-      case 0x7289: /* PCI_CHIP_RV570_7289 */
-      case 0x728B: /* PCI_CHIP_RV570_728B */
-      case 0x728C: /* PCI_CHIP_RV570_728C */
-      case 0x7240: /* PCI_CHIP_R580_7240 */
-      case 0x7243: /* PCI_CHIP_R580_7243 */
-      case 0x7244: /* PCI_CHIP_R580_7244 */
-      case 0x7245: /* PCI_CHIP_R580_7245 */
-      case 0x7246: /* PCI_CHIP_R580_7246 */
-      case 0x7247: /* PCI_CHIP_R580_7247 */
-      case 0x7248: /* PCI_CHIP_R580_7248 */
-      case 0x7249: /* PCI_CHIP_R580_7249 */
-      case 0x724A: /* PCI_CHIP_R580_724A */
-      case 0x724B: /* PCI_CHIP_R580_724B */
-      case 0x724C: /* PCI_CHIP_R580_724C */
-      case 0x724D: /* PCI_CHIP_R580_724D */
-      case 0x724E: /* PCI_CHIP_R580_724E */
-      case 0x724F: /* PCI_CHIP_R580_724F */
-      case 0x7284: /* PCI_CHIP_R580_7284 */
-      case 0x793F: /* PCI_CHIP_RS600_793F */
-      case 0x7941: /* PCI_CHIP_RS600_7941 */
-      case 0x7942: /* PCI_CHIP_RS600_7942 */
-      case 0x791E: /* PCI_CHIP_RS690_791E */
-      case 0x791F: /* PCI_CHIP_RS690_791F */
-      case 0x796C: /* PCI_CHIP_RS740_796C */
-      case 0x796D: /* PCI_CHIP_RS740_796D */
-      case 0x796E: /* PCI_CHIP_RS740_796E */
-      case 0x796F: /* PCI_CHIP_RS740_796F */
-	      return TRUE;
-      default:
-	      return FALSE;
-      }
-}
-
 #endif
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 3ac57d25b5e..0474b381ade 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -270,8 +270,13 @@ struct radeon_winsys *radeon_drm_winsys_create(int fd)
     ws->fd = fd;
     do_ioctls(ws);
 
-    if (!is_r3xx(ws->pci_id)) {
-        goto fail;
+    switch (ws->pci_id) {
+#define CHIPSET(pci_id, name, family) case pci_id:
+#include "pci_ids/r300_pci_ids.h"
+#undef CHIPSET
+       break;
+    default:
+       goto fail;
     }
 
     /* Create managers. */