r600g: evergreen fix for new design

Signed-off-by: Jerome Glisse <[email protected]>

3 files changed, 23 insertions, 40 deletions

diff --git a/src/gallium/winsys/r600/drm/evergreen_state.c b/src/gallium/winsys/r600/drm/evergreen_state.c
index d3831942113..5781d448ede 100644
--- a/src/gallium/winsys/r600/drm/evergreen_state.c
+++ b/src/gallium/winsys/r600/drm/evergreen_state.c
@@ -329,7 +329,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_028C64_CB_COLOR0_PITCH},
 	{0, 0, R_028C68_CB_COLOR0_SLICE},
 	{0, 0, R_028C6C_CB_COLOR0_VIEW},
-	{1, 0, R_028C70_CB_COLOR0_INFO},
+	{0, 0, R_028C70_CB_COLOR0_INFO},
 	{0, 0, R_028C74_CB_COLOR0_ATTRIB},
 	{0, 0, R_028C78_CB_COLOR0_DIM},
 	{0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -337,7 +337,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_028CA0_CB_COLOR1_PITCH},
 	{0, 0, R_028CA4_CB_COLOR1_SLICE},
 	{0, 0, R_028CA8_CB_COLOR1_VIEW},
-	{1, 0, R_028CAC_CB_COLOR1_INFO},
+	{0, 0, R_028CAC_CB_COLOR1_INFO},
 	{0, 0, R_028CB0_CB_COLOR1_ATTRIB},
 	{0, 0, R_028CB8_CB_COLOR1_DIM},
 	{0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -345,7 +345,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_028CDC_CB_COLOR2_PITCH},
 	{0, 0, R_028CE0_CB_COLOR2_SLICE},
 	{0, 0, R_028CE4_CB_COLOR2_VIEW},
-	{1, 0, R_028CE8_CB_COLOR2_INFO},
+	{0, 0, R_028CE8_CB_COLOR2_INFO},
 	{0, 0, R_028CEC_CB_COLOR2_ATTRIB},
 	{0, 0, R_028CF0_CB_COLOR2_DIM},
 	{0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -353,7 +353,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_028D18_CB_COLOR3_PITCH},
 	{0, 0, R_028D1C_CB_COLOR3_SLICE},
 	{0, 0, R_028D20_CB_COLOR3_VIEW},
-	{1, 0, R_028D24_CB_COLOR3_INFO},
+	{0, 0, R_028D24_CB_COLOR3_INFO},
 	{0, 0, R_028D28_CB_COLOR3_ATTRIB},
 	{0, 0, R_028D2C_CB_COLOR3_DIM},
 	{0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -361,7 +361,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_028D54_CB_COLOR4_PITCH},
 	{0, 0, R_028D58_CB_COLOR4_SLICE},
 	{0, 0, R_028D5C_CB_COLOR4_VIEW},
-	{1, 0, R_028D60_CB_COLOR4_INFO},
+	{0, 0, R_028D60_CB_COLOR4_INFO},
 	{0, 0, R_028D64_CB_COLOR4_ATTRIB},
 	{0, 0, R_028D68_CB_COLOR4_DIM},
 	{0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -369,7 +369,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_028D90_CB_COLOR5_PITCH},
 	{0, 0, R_028D94_CB_COLOR5_SLICE},
 	{0, 0, R_028D98_CB_COLOR5_VIEW},
-	{1, 0, R_028D9C_CB_COLOR5_INFO},
+	{0, 0, R_028D9C_CB_COLOR5_INFO},
 	{0, 0, R_028DA0_CB_COLOR5_ATTRIB},
 	{0, 0, R_028DA4_CB_COLOR5_DIM},
 	{0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -377,7 +377,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_028DCC_CB_COLOR6_PITCH},
 	{0, 0, R_028DD0_CB_COLOR6_SLICE},
 	{0, 0, R_028DD4_CB_COLOR6_VIEW},
-	{1, 0, R_028DD8_CB_COLOR6_INFO},
+	{0, 0, R_028DD8_CB_COLOR6_INFO},
 	{0, 0, R_028DDC_CB_COLOR6_ATTRIB},
 	{0, 0, R_028DE0_CB_COLOR6_DIM},
 	{0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -385,7 +385,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_028E08_CB_COLOR7_PITCH},
 	{0, 0, R_028E0C_CB_COLOR7_SLICE},
 	{0, 0, R_028E10_CB_COLOR7_VIEW},
-	{1, 0, R_028E14_CB_COLOR7_INFO},
+	{0, 0, R_028E14_CB_COLOR7_INFO},
 	{0, 0, R_028E18_CB_COLOR7_ATTRIB},
 	{0, 0, R_028E1C_CB_COLOR7_DIM},
 	{0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -393,7 +393,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_028E44_CB_COLOR8_PITCH},
 	{0, 0, R_028E48_CB_COLOR8_SLICE},
 	{0, 0, R_028E4C_CB_COLOR8_VIEW},
-	{1, 0, R_028E50_CB_COLOR8_INFO},
+	{0, 0, R_028E50_CB_COLOR8_INFO},
 	{0, 0, R_028E54_CB_COLOR8_ATTRIB},
 	{0, 0, R_028E58_CB_COLOR8_DIM},
 	{0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -401,7 +401,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_028E60_CB_COLOR9_PITCH},
 	{0, 0, R_028E64_CB_COLOR9_SLICE},
 	{0, 0, R_028E68_CB_COLOR9_VIEW},
-	{1, 0, R_028E6C_CB_COLOR9_INFO},
+	{0, 0, R_028E6C_CB_COLOR9_INFO},
 	{0, 0, R_028E70_CB_COLOR9_ATTRIB},
 	{0, 0, R_028E74_CB_COLOR9_DIM},
 	{0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -409,7 +409,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_028E7C_CB_COLOR10_PITCH},
 	{0, 0, R_028E80_CB_COLOR10_SLICE},
 	{0, 0, R_028E84_CB_COLOR10_VIEW},
-	{1, 0, R_028E88_CB_COLOR10_INFO},
+	{0, 0, R_028E88_CB_COLOR10_INFO},
 	{0, 0, R_028E8C_CB_COLOR10_ATTRIB},
 	{0, 0, R_028E90_CB_COLOR10_DIM},
 	{0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -417,7 +417,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_028E98_CB_COLOR11_PITCH},
 	{0, 0, R_028E9C_CB_COLOR11_SLICE},
 	{0, 0, R_028EA0_CB_COLOR11_VIEW},
-	{1, 0, R_028EA4_CB_COLOR11_INFO},
+	{0, 0, R_028EA4_CB_COLOR11_INFO},
 	{0, 0, R_028EA8_CB_COLOR11_ATTRIB},
 	{0, 0, R_028EAC_CB_COLOR11_DIM},
 };
@@ -464,6 +464,7 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 	int r;
 
 	memset(ctx, 0, sizeof(struct r600_context));
+	radeon->use_mem_constant = TRUE;
 	ctx->radeon = radeon;
 	LIST_INITHEAD(&ctx->query_list);
 	/* initialize groups */
@@ -511,13 +512,13 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 			goto out_err;
 	}
 	/* PS RESOURCE */
-	for (int j = 0, offset = 0; j < 176; j++, offset += 0x1C) {
+	for (int j = 0, offset = 0; j < 176; j++, offset += 0x20) {
 		r = evergreen_state_resource_init(ctx, offset);
 		if (r)
 			goto out_err;
 	}
 	/* VS RESOURCE */
-	for (int j = 0, offset = 0x1600; j < 176; j++, offset += 0x1C) {
+	for (int j = 0, offset = 0x1600; j < 176; j++, offset += 0x20) {
 		r = evergreen_state_resource_init(ctx, offset);
 		if (r)
 			goto out_err;
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
index 6023f215bb6..92b2eb1dff1 100644
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -39,6 +39,7 @@ struct radeon {
 	unsigned			device;
 	unsigned			family;
 	enum chip_class			chip_class;
+	boolean				use_mem_constant; /* true for evergreen */
 };
 
 struct radeon *r600_new(int fd, unsigned device);
diff --git a/src/gallium/winsys/r600/drm/r600_state2.c b/src/gallium/winsys/r600/drm/r600_state2.c
index 16950bd72d0..c29616c9cbc 100644
--- a/src/gallium/winsys/r600/drm/r600_state2.c
+++ b/src/gallium/winsys/r600/drm/r600_state2.c
@@ -65,31 +65,12 @@ unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *pb_bo);
 static void r600_context_queries_suspend(struct r600_context *ctx);
 static void r600_context_queries_resume(struct r600_context *ctx);
 
-static int r600_group_id_register_offset(unsigned offset)
+static int r600_group_id_register_offset(struct r600_context *ctx, unsigned offset)
 {
-	if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
-		return R600_GROUP_CONFIG;
-	}
-	if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) {
-		return R600_GROUP_CONTEXT;
-	}
-	if (offset >= R600_ALU_CONST_OFFSET && offset < R600_ALU_CONST_END) {
-		return R600_GROUP_ALU_CONST;
-	}
-	if (offset >= R600_RESOURCE_OFFSET && offset < R600_RESOURCE_END) {
-		return R600_GROUP_RESOURCE;
-	}
-	if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) {
-		return R600_GROUP_SAMPLER;
-	}
-	if (offset >= R600_CTL_CONST_OFFSET && offset < R600_CTL_CONST_END) {
-		return R600_GROUP_CTL_CONST;
-	}
-	if (offset >= R600_LOOP_CONST_OFFSET && offset < R600_LOOP_CONST_END) {
-		return R600_GROUP_LOOP_CONST;
-	}
-	if (offset >= R600_BOOL_CONST_OFFSET && offset < R600_BOOL_CONST_END) {
-		return R600_GROUP_BOOL_CONST;
+	for (int i = 0; i < ctx->ngroups; i++) {
+		if (offset >= ctx->groups[i].start_offset && offset <= ctx->groups[i].end_offset) {
+			return i;
+		}
 	}
 	return -1;
 }
@@ -119,7 +100,7 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
 			continue;
 
 		/* find into which group this block is */
-		group_id = r600_group_id_register_offset(reg[i].offset);
+		group_id = r600_group_id_register_offset(ctx, reg[i].offset);
 		assert(group_id >= 0);
 		group = &ctx->groups[group_id];
 
@@ -1005,7 +986,7 @@ void r600_context_flush(struct r600_context *ctx)
 	/* suspend queries */
 	r600_context_queries_suspend(ctx);
 
-#if 1
+#if 0
 	/* emit cs */
 	drmib.num_chunks = 2;
 	drmib.chunks = (uint64_t)(uintptr_t)chunk_array;