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authorJerome Glisse <[email protected]>2013-01-04 16:34:52 -0500
committerJerome Glisse <[email protected]>2013-01-07 11:06:07 -0500
commitca474f98f2cda5cb333e9f851c7e0e31c9a6f823 (patch)
tree8e046880ece999573bb7dae4b471156c96a06fcf /src/gallium/winsys/radeon
parentd499ff98cd69c9ec6c43ad8ececa4c3b61889ab9 (diff)
radeon/winsys: move radeon family/class identification to winsys
Upcoming async dma support rely on winsys knowing about GPU families. Signed-off-by: Jerome Glisse <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium/winsys/radeon')
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.c96
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.h6
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_winsys.h112
3 files changed, 176 insertions, 38 deletions
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 91710fc1b20..bcfb448db5d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -228,29 +228,97 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
/* Check PCI ID. */
switch (ws->info.pci_id) {
-#define CHIPSET(pci_id, name, family) case pci_id:
+#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
#include "pci_ids/r300_pci_ids.h"
#undef CHIPSET
- ws->gen = R300;
- break;
-#define CHIPSET(pci_id, name, family) case pci_id:
+#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
#include "pci_ids/r600_pci_ids.h"
#undef CHIPSET
- ws->gen = R600;
- break;
-#define CHIPSET(pci_id, name, family) case pci_id:
+#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
#include "pci_ids/radeonsi_pci_ids.h"
#undef CHIPSET
- ws->gen = SI;
- break;
default:
fprintf(stderr, "radeon: Invalid PCI ID.\n");
return FALSE;
}
+ switch (ws->info.family) {
+ default:
+ case CHIP_UNKNOWN:
+ fprintf(stderr, "radeon: Unknown family.\n");
+ return FALSE;
+ case CHIP_R300:
+ case CHIP_R350:
+ case CHIP_RV350:
+ case CHIP_RV370:
+ case CHIP_RV380:
+ case CHIP_RS400:
+ case CHIP_RC410:
+ case CHIP_RS480:
+ ws->info.chip_class = R300;
+ break;
+ case CHIP_R420: /* R4xx-based cores. */
+ case CHIP_R423:
+ case CHIP_R430:
+ case CHIP_R480:
+ case CHIP_R481:
+ case CHIP_RV410:
+ case CHIP_RS600:
+ case CHIP_RS690:
+ case CHIP_RS740:
+ ws->info.chip_class = R400;
+ break;
+ case CHIP_RV515: /* R5xx-based cores. */
+ case CHIP_R520:
+ case CHIP_RV530:
+ case CHIP_R580:
+ case CHIP_RV560:
+ case CHIP_RV570:
+ ws->info.chip_class = R500;
+ break;
+ case CHIP_R600:
+ case CHIP_RV610:
+ case CHIP_RV630:
+ case CHIP_RV670:
+ case CHIP_RV620:
+ case CHIP_RV635:
+ case CHIP_RS780:
+ case CHIP_RS880:
+ ws->info.chip_class = R600;
+ break;
+ case CHIP_RV770:
+ case CHIP_RV730:
+ case CHIP_RV710:
+ case CHIP_RV740:
+ ws->info.chip_class = R700;
+ break;
+ case CHIP_CEDAR:
+ case CHIP_REDWOOD:
+ case CHIP_JUNIPER:
+ case CHIP_CYPRESS:
+ case CHIP_HEMLOCK:
+ case CHIP_PALM:
+ case CHIP_SUMO:
+ case CHIP_SUMO2:
+ case CHIP_BARTS:
+ case CHIP_TURKS:
+ case CHIP_CAICOS:
+ ws->info.chip_class = EVERGREEN;
+ break;
+ case CHIP_CAYMAN:
+ case CHIP_ARUBA:
+ ws->info.chip_class = CAYMAN;
+ break;
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ ws->info.chip_class = TAHITI;
+ break;
+ }
+
/* Get GEM info. */
retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
&gem_info, sizeof(gem_info));
@@ -265,7 +333,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
/* Generation-specific queries. */
- if (ws->gen == R300) {
+ if (ws->gen == DRV_R300) {
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
"GB pipe count",
&ws->info.r300_num_gb_pipes))
@@ -276,7 +344,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
&ws->info.r300_num_z_pipes))
return FALSE;
}
- else if (ws->gen >= R600) {
+ else if (ws->gen >= DRV_R600) {
if (ws->info.drm_minor >= 9 &&
!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
"num backends",
@@ -333,7 +401,7 @@ static void radeon_winsys_destroy(struct radeon_winsys *rws)
ws->cman->destroy(ws->cman);
ws->kman->destroy(ws->kman);
- if (ws->gen >= R600) {
+ if (ws->gen >= DRV_R600) {
radeon_surface_manager_free(ws->surf_man);
}
if (fd_tab) {
@@ -394,7 +462,7 @@ static uint64_t radeon_query_timestamp(struct radeon_winsys *rws)
uint64_t ts = 0;
if (ws->info.drm_minor < 20 ||
- ws->gen < R600) {
+ ws->gen < DRV_R600) {
assert(0);
return 0;
}
@@ -446,7 +514,7 @@ struct radeon_winsys *radeon_drm_winsys_create(int fd)
if (!ws->cman)
goto fail;
- if (ws->gen >= R600) {
+ if (ws->gen >= DRV_R600) {
ws->surf_man = radeon_surface_manager_new(fd);
if (!ws->surf_man)
goto fail;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
index 22983072fbb..e714127730f 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
@@ -34,9 +34,9 @@
#include "os/os_thread.h"
enum radeon_generation {
- R300,
- R600,
- SI
+ DRV_R300,
+ DRV_R600,
+ DRV_SI
};
struct radeon_drm_winsys {
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 5bcbf8d16cd..d0c48224cc5 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -70,6 +70,74 @@ enum radeon_bo_usage { /* bitfield */
RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
};
+enum radeon_family {
+ CHIP_UNKNOWN = 0,
+ CHIP_R300, /* R3xx-based cores. */
+ CHIP_R350,
+ CHIP_RV350,
+ CHIP_RV370,
+ CHIP_RV380,
+ CHIP_RS400,
+ CHIP_RC410,
+ CHIP_RS480,
+ CHIP_R420, /* R4xx-based cores. */
+ CHIP_R423,
+ CHIP_R430,
+ CHIP_R480,
+ CHIP_R481,
+ CHIP_RV410,
+ CHIP_RS600,
+ CHIP_RS690,
+ CHIP_RS740,
+ CHIP_RV515, /* R5xx-based cores. */
+ CHIP_R520,
+ CHIP_RV530,
+ CHIP_R580,
+ CHIP_RV560,
+ CHIP_RV570,
+ CHIP_R600,
+ CHIP_RV610,
+ CHIP_RV630,
+ CHIP_RV670,
+ CHIP_RV620,
+ CHIP_RV635,
+ CHIP_RS780,
+ CHIP_RS880,
+ CHIP_RV770,
+ CHIP_RV730,
+ CHIP_RV710,
+ CHIP_RV740,
+ CHIP_CEDAR,
+ CHIP_REDWOOD,
+ CHIP_JUNIPER,
+ CHIP_CYPRESS,
+ CHIP_HEMLOCK,
+ CHIP_PALM,
+ CHIP_SUMO,
+ CHIP_SUMO2,
+ CHIP_BARTS,
+ CHIP_TURKS,
+ CHIP_CAICOS,
+ CHIP_CAYMAN,
+ CHIP_ARUBA,
+ CHIP_TAHITI,
+ CHIP_PITCAIRN,
+ CHIP_VERDE,
+ CHIP_LAST,
+};
+
+enum chip_class {
+ CLASS_UNKNOWN = 0,
+ R300,
+ R400,
+ R500,
+ R600,
+ R700,
+ EVERGREEN,
+ CAYMAN,
+ TAHITI,
+};
+
struct winsys_handle;
struct radeon_winsys_cs_handle;
@@ -79,27 +147,29 @@ struct radeon_winsys_cs {
};
struct radeon_info {
- uint32_t pci_id;
- uint32_t gart_size;
- uint32_t vram_size;
-
- uint32_t drm_major; /* version */
- uint32_t drm_minor;
- uint32_t drm_patchlevel;
-
- uint32_t r300_num_gb_pipes;
- uint32_t r300_num_z_pipes;
-
- uint32_t r600_num_backends;
- uint32_t r600_clock_crystal_freq;
- uint32_t r600_tiling_config;
- uint32_t r600_num_tile_pipes;
- uint32_t r600_backend_map;
- boolean r600_backend_map_valid;
- boolean r600_virtual_address;
- uint32_t r600_va_start;
- uint32_t r600_ib_vm_max_size;
- uint32_t r600_max_pipes;
+ uint32_t pci_id;
+ enum radeon_family family;
+ enum chip_class chip_class;
+ uint32_t gart_size;
+ uint32_t vram_size;
+
+ uint32_t drm_major; /* version */
+ uint32_t drm_minor;
+ uint32_t drm_patchlevel;
+
+ uint32_t r300_num_gb_pipes;
+ uint32_t r300_num_z_pipes;
+
+ uint32_t r600_num_backends;
+ uint32_t r600_clock_crystal_freq;
+ uint32_t r600_tiling_config;
+ uint32_t r600_num_tile_pipes;
+ uint32_t r600_backend_map;
+ uint32_t r600_va_start;
+ uint32_t r600_ib_vm_max_size;
+ uint32_t r600_max_pipes;
+ boolean r600_backend_map_valid;
+ boolean r600_virtual_address;
};
enum radeon_feature_id {