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authorMarek Olšák <[email protected]>2011-08-04 03:01:44 +0200
committerMarek Olšák <[email protected]>2011-08-16 09:15:11 +0200
commit1b542aca6e998e544a90ccff310f74b2811b8db0 (patch)
tree6e90cd0f855feec715f606abeeee3f9f071bb51c /src/gallium/winsys/radeon
parent03b25ad8ffd72f1f88b6c80a2ebfe3cf6e8a6390 (diff)
r600g: move more DRM queries into winsys/radeon
Reviewed-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src/gallium/winsys/radeon')
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.c19
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_winsys.h3
2 files changed, 21 insertions, 1 deletions
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 3be6e34f6f0..1f3bd6dd7bd 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -58,7 +58,15 @@
#endif
#ifndef RADEON_INFO_NUM_BACKENDS
-#define RADEON_INFO_NUM_BACKENDS 10
+#define RADEON_INFO_NUM_BACKENDS 0xa
+#endif
+
+#ifndef RADEON_INFO_NUM_TILE_PIPES
+#define RADEON_INFO_NUM_TILE_PIPES 0xb
+#endif
+
+#ifndef RADEON_INFO_BACKEND_MAP
+#define RADEON_INFO_BACKEND_MAP 0xd
#endif
/* Enable/disable feature access for one command stream.
@@ -240,6 +248,15 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
&ws->info.r600_tiling_config);
+
+ if (ws->info.drm_minor >= 11) {
+ radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
+ &ws->info.r600_num_tile_pipes);
+
+ if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
+ &ws->info.r600_backend_map))
+ ws->info.r600_backend_map_valid = TRUE;
+ }
}
return TRUE;
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 6360d6a8401..dcb3f587a6e 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -85,6 +85,9 @@ struct radeon_info {
uint32_t r600_num_backends;
uint32_t r600_clock_crystal_freq;
uint32_t r600_tiling_config;
+ uint32_t r600_num_tile_pipes;
+ uint32_t r600_backend_map;
+ boolean r600_backend_map_valid;
};
enum radeon_feature_id {