diff options
| author | Marek Olšák <[email protected]> | 2018-05-02 18:39:04 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-05-10 18:39:54 -0400 |
| commit | 09f1bab483cc8011a6299e2aca805b6ad06aab82 (patch) | |
| tree | ae424cb9f01a649e49c04bc491568e3aa60928bb /src/gallium/winsys/radeon/drm | |
| parent | 8b58a14ef76f6d6e6c71fff2cb5c8fa6662a1882 (diff) | |
ac/gpu_info: add si_TA_CS_BC_BASE_ADDR_allowed
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/winsys/radeon/drm')
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 21579fd9563..6040134c2da 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -532,6 +532,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) /* HTILE is broken with 1D tiling on old kernels and CIK. */ ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK || ws->info.drm_minor >= 38; + ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48; ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; |