diff options
| author | Marek Olšák <[email protected]> | 2015-04-16 19:41:33 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2015-08-14 15:02:28 +0200 |
| commit | e7fc664b91a5d886c2709d05a498f6a1dfbaf136 (patch) | |
| tree | 1f0939533c7d083a0ce671ea9c7ea9e316410961 /src/gallium/winsys/radeon/drm | |
| parent | 2eb067db0febcd71b4182153155e3e43f215624c (diff) | |
winsys/amdgpu: add addrlib - texture addressing and alignment calculator
This is an internal project that Catalyst uses and now open source will do
too.
v2: squashed these commits in:
- winsys/amdgpu: fix warnings in addrlib
- winsys/amdgpu: set PIPE_CONFIG and NUM_BANKS in tiling_flags
Diffstat (limited to 'src/gallium/winsys/radeon/drm')
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index ecaeb3bc29c..3a9ac445b24 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -774,10 +774,11 @@ static void radeon_bo_set_tiling(struct pb_buffer *_buf, struct radeon_winsys_cs *rcs, enum radeon_bo_layout microtiled, enum radeon_bo_layout macrotiled, + unsigned pipe_config, unsigned bankw, unsigned bankh, unsigned tile_split, unsigned stencil_tile_split, - unsigned mtilea, + unsigned mtilea, unsigned num_banks, uint32_t pitch, bool scanout) { |