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authorJerome Glisse <[email protected]>2010-12-07 15:15:58 -0500
committerJerome Glisse <[email protected]>2010-12-07 17:54:56 -0500
commitb7617346dcff50a66a10c61b95c33682cf629c9e (patch)
tree1099f55e8ed95483169aa3e10ac1bc20d916f131 /src/gallium/winsys/r600
parent69251fc4cd5f71be403e08398bc43d19052a640d (diff)
r600g: fix userspace fence against lastest kernel
R6XX GPU doesn't like to have two partial flush writting back to memory in row without a prior flush of the pipeline. Add PS_PARTIAL_FLUSH to flush all work between the CP and the ES, GS, VS, PS shaders. Thanks a lot to Alban Browaeys (prahal on irc) for investigating this issue. Signed-off-by: Alban Browaeys <[email protected]> Signed-off-by: Jerome Glisse <[email protected]>
Diffstat (limited to 'src/gallium/winsys/r600')
-rw-r--r--src/gallium/winsys/r600/drm/r600_hw_context.c2
-rw-r--r--src/gallium/winsys/r600/drm/r600d.h1
2 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index b2da7bf9909..0f2724f61ce 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -1112,6 +1112,8 @@ void r600_context_flush(struct r600_context *ctx)
r600_context_queries_suspend(ctx);
/* emit fence */
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0);
+ ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4);
ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
ctx->pm4[ctx->pm4_cdwords++] = 0;
diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
index 4a08d504aab..1c1ac76fe69 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -91,6 +91,7 @@
#define PKT3_SET_CTL_CONST 0x6F
#define PKT3_SURFACE_BASE_UPDATE 0x73
+#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
#define EVENT_TYPE_ZPASS_DONE 0x15
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16