Merge branch 'master' into pipe-video

Conflicts:
	configs/linux-dri
	configure.ac
	src/gallium/drivers/nvfx/Makefile
	src/gallium/include/pipe/p_defines.h
	src/gallium/include/pipe/p_screen.h
	src/gallium/include/state_tracker/dri1_api.h
	src/gallium/include/state_tracker/drm_api.h
	src/gallium/tests/python/samples/tri.py
	src/gallium/tests/trivial/Makefile
	src/gallium/tests/unit/Makefile
	src/gallium/tests/unit/SConscript
	src/gallium/tests/unit/u_format_test.c
	src/gallium/winsys/nouveau/drm/nouveau_drm_api.c

15 files changed, 6750 insertions, 0 deletions

diff --git a/src/gallium/winsys/r600/drm/Makefile b/src/gallium/winsys/r600/drm/Makefile
new file mode 100644
index 00000000000..a396205f897
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/Makefile
@@ -0,0 +1,23 @@
+
+TOP = ../../../../..
+include $(TOP)/configs/current
+
+LIBNAME = r600winsys
+
+C_SOURCES = \
+	bof.c \
+	evergreen_hw_context.c \
+	radeon_bo.c \
+	radeon_bo_pb.c \
+	radeon_pciid.c \
+	r600.c \
+	r600_bo.c \
+	r600_drm.c \
+	r600_hw_context.c
+
+LIBRARY_INCLUDES = -I$(TOP)/src/gallium/drivers/r600 \
+		   $(shell pkg-config libdrm --cflags-only-I)
+
+include ../../../Makefile.template
+
+symlinks:
diff --git a/src/gallium/winsys/r600/drm/SConscript b/src/gallium/winsys/r600/drm/SConscript
new file mode 100644
index 00000000000..cc053c06dd0
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/SConscript
@@ -0,0 +1,25 @@
+Import('*')
+
+env = env.Clone()
+
+r600_sources = [
+    'bof.c',
+    'evergreen_hw_context.c',
+    'radeon_bo.c',
+    'radeon_bo_pb.c',
+    'radeon_pciid.c',
+    'r600.c',
+    'r600_bo.c',
+    'r600_drm.c',
+    'r600_hw_context.c',
+]
+
+env.ParseConfig('pkg-config --cflags libdrm_radeon')
+env.Append(CPPPATH = '#/src/gallium/drivers/r600')
+
+r600winsys = env.ConvenienceLibrary(
+    target ='r600winsys',
+    source = r600_sources,
+)
+
+Export('r600winsys')
diff --git a/src/gallium/winsys/r600/drm/bof.c b/src/gallium/winsys/r600/drm/bof.c
new file mode 100644
index 00000000000..0598cc6bc0f
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/bof.c
@@ -0,0 +1,477 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <errno.h>
+#include <stdlib.h>
+#include <string.h>
+#include "bof.h"
+
+/*
+ * helpers
+ */
+static int bof_entry_grow(bof_t *bof)
+{
+	bof_t **array;
+
+	if (bof->array_size < bof->nentry)
+		return 0;
+	array = realloc(bof->array, (bof->nentry + 16) * sizeof(void*));
+	if (array == NULL)
+		return -ENOMEM;
+	bof->array = array;
+	bof->nentry += 16;
+	return 0;
+}
+
+/*
+ * object 
+ */
+bof_t *bof_object(void)
+{
+	bof_t *object;
+
+	object = calloc(1, sizeof(bof_t));
+	if (object == NULL)
+		return NULL;
+	object->refcount = 1;
+	object->type = BOF_TYPE_OBJECT;
+	object->size = 12;
+	return object;
+}
+
+bof_t *bof_object_get(bof_t *object, const char *keyname)
+{
+	unsigned i;
+
+	for (i = 0; i < object->array_size; i += 2) {
+		if (!strcmp(object->array[i]->value, keyname)) {
+			return object->array[i + 1];
+		}
+	}
+	return NULL;
+}
+
+int bof_object_set(bof_t *object, const char *keyname, bof_t *value)
+{
+	bof_t *key;
+	int r;
+
+	if (object->type != BOF_TYPE_OBJECT)
+		return -EINVAL;
+	r = bof_entry_grow(object);
+	if (r)
+		return r;
+	key = bof_string(keyname);
+	if (key == NULL)
+		return -ENOMEM;
+	object->array[object->array_size++] = key;
+	object->array[object->array_size++] = value;
+	object->size += value->size;
+	object->size += key->size;
+	bof_incref(value);
+	return 0;
+}
+
+/*
+ * array
+ */
+bof_t *bof_array(void)
+{
+	bof_t *array = bof_object();
+
+	if (array == NULL)
+		return NULL;
+	array->type = BOF_TYPE_ARRAY;
+	array->size = 12;
+	return array;
+}
+
+int bof_array_append(bof_t *array, bof_t *value)
+{
+	int r;
+	if (array->type != BOF_TYPE_ARRAY)
+		return -EINVAL;
+	r = bof_entry_grow(array);
+	if (r)
+		return r;
+	array->array[array->array_size++] = value;
+	array->size += value->size;
+	bof_incref(value);
+	return 0;
+}
+
+bof_t *bof_array_get(bof_t *bof, unsigned i)
+{
+	if (!bof_is_array(bof) || i >= bof->array_size)
+		return NULL;
+	return bof->array[i];
+}
+
+unsigned bof_array_size(bof_t *bof)
+{
+	if (!bof_is_array(bof))
+		return 0;
+	return bof->array_size;
+}
+
+/*
+ * blob
+ */
+bof_t *bof_blob(unsigned size, void *value)
+{
+	bof_t *blob = bof_object();
+
+	if (blob == NULL)
+		return NULL;
+	blob->type = BOF_TYPE_BLOB;
+	blob->value = calloc(1, size);
+	if (blob->value == NULL) {
+		bof_decref(blob);
+		return NULL;
+	}
+	blob->size = size;
+	memcpy(blob->value, value, size);
+	blob->size += 12;
+	return blob;
+}
+
+unsigned bof_blob_size(bof_t *bof)
+{
+	if (!bof_is_blob(bof))
+		return 0;
+	return bof->size - 12;
+}
+
+void *bof_blob_value(bof_t *bof)
+{
+	if (!bof_is_blob(bof))
+		return NULL;
+	return bof->value;
+}
+
+/*
+ * string
+ */
+bof_t *bof_string(const char *value)
+{
+	bof_t *string = bof_object();
+
+	if (string == NULL)
+		return NULL;
+	string->type = BOF_TYPE_STRING;
+	string->size = strlen(value) + 1;
+	string->value = calloc(1, string->size);
+	if (string->value == NULL) {
+		bof_decref(string);
+		return NULL;
+	}
+	strcpy(string->value, value);
+	string->size += 12;
+	return string;
+}
+
+/*
+ *  int32
+ */
+bof_t *bof_int32(int32_t value)
+{
+	bof_t *int32 = bof_object();
+
+	if (int32 == NULL)
+		return NULL;
+	int32->type = BOF_TYPE_INT32;
+	int32->size = 4;
+	int32->value = calloc(1, int32->size);
+	if (int32->value == NULL) {
+		bof_decref(int32);
+		return NULL;
+	}
+	memcpy(int32->value, &value, 4);
+	int32->size += 12;
+	return int32;
+}
+
+int32_t bof_int32_value(bof_t *bof)
+{
+	return *((uint32_t*)bof->value);
+}
+
+/*
+ *  common
+ */
+static void bof_indent(int level)
+{
+	int i;
+
+	for (i = 0; i < level; i++)
+		fprintf(stderr, " ");
+}
+
+static void bof_print_bof(bof_t *bof, int level, int entry)
+{
+	bof_indent(level);
+	if (bof == NULL) {
+		fprintf(stderr, "--NULL-- for entry %d\n", entry);
+		return;
+	}
+	switch (bof->type) {
+	case BOF_TYPE_STRING:
+		fprintf(stderr, "%p string [%s %d]\n", bof, (char*)bof->value, bof->size);
+		break;
+	case BOF_TYPE_INT32:
+		fprintf(stderr, "%p int32 [%d %d]\n", bof, *(int*)bof->value, bof->size);
+		break;
+	case BOF_TYPE_BLOB:
+		fprintf(stderr, "%p blob [%d]\n", bof, bof->size);
+		break;
+	case BOF_TYPE_NULL:
+		fprintf(stderr, "%p null [%d]\n", bof, bof->size);
+		break;
+	case BOF_TYPE_OBJECT:
+		fprintf(stderr, "%p object [%d %d]\n", bof, bof->array_size / 2, bof->size);
+		break;
+	case BOF_TYPE_ARRAY:
+		fprintf(stderr, "%p array [%d %d]\n", bof, bof->array_size, bof->size);
+		break;
+	default:
+		fprintf(stderr, "%p unknown [%d]\n", bof, bof->type);
+		return;
+	}
+}
+
+static void bof_print_rec(bof_t *bof, int level, int entry)
+{
+	unsigned i;
+
+	bof_print_bof(bof, level, entry);
+	for (i = 0; i < bof->array_size; i++) {
+		bof_print_rec(bof->array[i], level + 2, i);
+	}
+}
+
+void bof_print(bof_t *bof)
+{
+	bof_print_rec(bof, 0, 0);
+}
+
+static int bof_read(bof_t *root, FILE *file, long end, int level)
+{
+	bof_t *bof = NULL;
+	int r;
+
+	if (ftell(file) >= end) {
+		return 0;
+	}
+	r = bof_entry_grow(root);
+	if (r)
+		return r;
+	bof = bof_object();
+	if (bof == NULL)
+		return -ENOMEM;
+	bof->offset = ftell(file);
+	r = fread(&bof->type, 4, 1, file);
+	if (r != 1)
+		goto out_err;
+	r = fread(&bof->size, 4, 1, file);
+	if (r != 1)
+		goto out_err;
+	r = fread(&bof->array_size, 4, 1, file);
+	if (r != 1)
+		goto out_err;
+	switch (bof->type) {
+	case BOF_TYPE_STRING:
+	case BOF_TYPE_INT32:
+	case BOF_TYPE_BLOB:
+		bof->value = calloc(1, bof->size - 12);
+		if (bof->value == NULL) {
+			goto out_err;
+		}
+		r = fread(bof->value, bof->size - 12, 1, file);
+		if (r != 1) {
+			fprintf(stderr, "error reading %d\n", bof->size - 12);
+			goto out_err;
+		}
+		break;
+	case BOF_TYPE_NULL:
+		return 0;
+	case BOF_TYPE_OBJECT:
+	case BOF_TYPE_ARRAY:
+		r = bof_read(bof, file, bof->offset + bof->size, level + 2);
+		if (r)
+			goto out_err;
+		break;
+	default:
+		fprintf(stderr, "invalid type %d\n", bof->type);
+		goto out_err;
+	}
+	root->array[root->centry++] = bof;
+	return bof_read(root, file, end, level);
+out_err:
+	bof_decref(bof);
+	return -EINVAL;
+}
+
+bof_t *bof_load_file(const char *filename)
+{
+	bof_t *root = bof_object();
+	int r;
+
+	if (root == NULL) {
+		fprintf(stderr, "%s failed to create root object\n", __func__);
+		return NULL;
+	}
+	root->file = fopen(filename, "r");
+	if (root->file == NULL)
+		goto out_err;
+	r = fseek(root->file, 0L, SEEK_SET);
+	if (r) {
+		fprintf(stderr, "%s failed to seek into file %s\n", __func__, filename);
+		goto out_err;
+	}
+	root->offset = ftell(root->file);
+	r = fread(&root->type, 4, 1, root->file);
+	if (r != 1)
+		goto out_err;
+	r = fread(&root->size, 4, 1, root->file);
+	if (r != 1)
+		goto out_err;
+	r = fread(&root->array_size, 4, 1, root->file);
+	if (r != 1)
+		goto out_err;
+	r = bof_read(root, root->file, root->offset + root->size, 2);
+	if (r)
+		goto out_err;
+	return root;
+out_err:
+	bof_decref(root);
+	return NULL;
+}
+
+void bof_incref(bof_t *bof)
+{
+	bof->refcount++;
+}
+
+void bof_decref(bof_t *bof)
+{
+	unsigned i;
+
+	if (bof == NULL)
+		return;
+	if (--bof->refcount > 0)
+		return;
+	for (i = 0; i < bof->array_size; i++) {
+		bof_decref(bof->array[i]);
+		bof->array[i] = NULL;
+	}
+	bof->array_size = 0;
+	if (bof->file) {
+		fclose(bof->file);
+		bof->file = NULL;
+	}
+	free(bof->array);
+	free(bof->value);
+	free(bof);
+}
+
+static int bof_file_write(bof_t *bof, FILE *file)
+{
+	unsigned i;
+	int r;
+
+	r = fwrite(&bof->type, 4, 1, file);
+	if (r != 1)
+		return -EINVAL;
+	r = fwrite(&bof->size, 4, 1, file);
+	if (r != 1)
+		return -EINVAL;
+	r = fwrite(&bof->array_size, 4, 1, file);
+	if (r != 1)
+		return -EINVAL;
+	switch (bof->type) {
+	case BOF_TYPE_NULL:
+		if (bof->size)
+			return -EINVAL;
+		break;
+	case BOF_TYPE_STRING:
+	case BOF_TYPE_INT32:
+	case BOF_TYPE_BLOB:
+		r = fwrite(bof->value, bof->size - 12, 1, file);
+		if (r != 1)
+			return -EINVAL;
+		break;
+	case BOF_TYPE_OBJECT:
+	case BOF_TYPE_ARRAY:
+		for (i = 0; i < bof->array_size; i++) {
+			r = bof_file_write(bof->array[i], file);
+			if (r)
+				return r;
+		}
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+int bof_dump_file(bof_t *bof, const char *filename)
+{
+	unsigned i;
+	int r = 0;
+
+	if (bof->file) {
+		fclose(bof->file);
+		bof->file = NULL;
+	}
+	bof->file = fopen(filename, "w");
+	if (bof->file == NULL) {
+		fprintf(stderr, "%s failed to open file %s\n", __func__, filename);
+		r = -EINVAL;
+		goto out_err;
+	}
+	r = fseek(bof->file, 0L, SEEK_SET);
+	if (r) {
+		fprintf(stderr, "%s failed to seek into file %s\n", __func__, filename);
+		goto out_err;
+	}
+	r = fwrite(&bof->type, 4, 1, bof->file);
+	if (r != 1)
+		goto out_err;
+	r = fwrite(&bof->size, 4, 1, bof->file);
+	if (r != 1)
+		goto out_err;
+	r = fwrite(&bof->array_size, 4, 1, bof->file);
+	if (r != 1)
+		goto out_err;
+	for (i = 0; i < bof->array_size; i++) {
+		r = bof_file_write(bof->array[i], bof->file);
+		if (r)
+			return r;
+	}
+out_err:
+	fclose(bof->file);
+	bof->file = NULL;
+	return r;
+}
diff --git a/src/gallium/winsys/r600/drm/bof.h b/src/gallium/winsys/r600/drm/bof.h
new file mode 100644
index 00000000000..014affb74f1
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/bof.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef BOF_H
+#define BOF_H
+
+#include <stdio.h>
+#include <stdint.h>
+
+#define BOF_TYPE_STRING		0
+#define BOF_TYPE_NULL		1
+#define BOF_TYPE_BLOB		2
+#define BOF_TYPE_OBJECT		3
+#define BOF_TYPE_ARRAY		4
+#define BOF_TYPE_INT32		5
+
+struct bof;
+
+typedef struct bof {
+	struct bof	**array;
+	unsigned	centry;
+	unsigned	nentry;
+	unsigned	refcount;
+	FILE		*file;
+	uint32_t	type;
+	uint32_t	size;
+	uint32_t	array_size;
+	void		*value;
+	long		offset;
+} bof_t;
+
+extern int bof_file_flush(bof_t *root);
+extern bof_t *bof_file_new(const char *filename);
+extern int bof_object_dump(bof_t *object, const char *filename);
+
+/* object */
+extern bof_t *bof_object(void);
+extern bof_t *bof_object_get(bof_t *object, const char *keyname);
+extern int bof_object_set(bof_t *object, const char *keyname, bof_t *value);
+/* array */
+extern bof_t *bof_array(void);
+extern int bof_array_append(bof_t *array, bof_t *value);
+extern bof_t *bof_array_get(bof_t *bof, unsigned i);
+extern unsigned bof_array_size(bof_t *bof);
+/* blob */
+extern bof_t *bof_blob(unsigned size, void *value);
+extern unsigned bof_blob_size(bof_t *bof);
+extern void *bof_blob_value(bof_t *bof);
+/* string */
+extern bof_t *bof_string(const char *value);
+/* int32 */
+extern bof_t *bof_int32(int32_t value);
+extern int32_t bof_int32_value(bof_t *bof);
+/* common functions */
+extern void bof_decref(bof_t *bof);
+extern void bof_incref(bof_t *bof);
+extern bof_t *bof_load_file(const char *filename);
+extern int bof_dump_file(bof_t *bof, const char *filename);
+extern void bof_print(bof_t *bof);
+
+static inline int bof_is_object(bof_t *bof){return (bof->type == BOF_TYPE_OBJECT);}
+static inline int bof_is_blob(bof_t *bof){return (bof->type == BOF_TYPE_BLOB);}
+static inline int bof_is_null(bof_t *bof){return (bof->type == BOF_TYPE_NULL);}
+static inline int bof_is_int32(bof_t *bof){return (bof->type == BOF_TYPE_INT32);}
+static inline int bof_is_array(bof_t *bof){return (bof->type == BOF_TYPE_ARRAY);}
+static inline int bof_is_string(bof_t *bof){return (bof->type == BOF_TYPE_STRING);}
+
+#endif
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
new file mode 100644
index 00000000000..e51725abb8a
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -0,0 +1,912 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "xf86drm.h"
+#include "r600.h"
+#include "evergreend.h"
+#include "radeon_drm.h"
+#include "bof.h"
+#include "pipe/p_compiler.h"
+#include "util/u_inlines.h"
+#include "util/u_memory.h"
+#include <pipebuffer/pb_bufmgr.h>
+#include "r600_priv.h"
+
+#define GROUP_FORCE_NEW_BLOCK	0
+
+static const struct r600_reg evergreen_config_reg_list[] = {
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008A14_PA_CL_ENHANCE, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C20_SQ_STACK_RESOURCE_MGMT_1, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C24_SQ_STACK_RESOURCE_MGMT_2, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C28_SQ_STACK_RESOURCE_MGMT_3, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_009100_SPI_CONFIG_CNTL, 0, 0},
+	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_00913C_SPI_CONFIG_CNTL_1, 0, 0},
+};
+
+static const struct r600_reg evergreen_ctl_const_list[] = {
+	{PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0},
+	{PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
+};
+
+static const struct r600_reg evergreen_context_reg_list[] = {
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028000_DB_RENDER_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028004_DB_COUNT_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028008_DB_DEPTH_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02800C_DB_RENDER_OVERRIDE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028010_DB_RENDER_OVERRIDE2, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028014_DB_HTILE_DATA_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028040_DB_Z_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028044_DB_STENCIL_INFO, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028048_DB_Z_READ_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02804C_DB_STENCIL_READ_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028050_DB_Z_WRITE_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028054_DB_STENCIL_WRITE_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028058_DB_DEPTH_SIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02805C_DB_DEPTH_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285BC_PA_CL_UCP0_X, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C0_PA_CL_UCP0_Y, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C4_PA_CL_UCP0_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C8_PA_CL_UCP0_W, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285CC_PA_CL_UCP1_X, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D0_PA_CL_UCP1_Y, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D4_PA_CL_UCP1_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D8_PA_CL_UCP1_W, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285DC_PA_CL_UCP2_X, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E0_PA_CL_UCP2_Y, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E4_PA_CL_UCP2_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E8_PA_CL_UCP2_W, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285EC_PA_CL_UCP3_X, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F0_PA_CL_UCP3_Y, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F4_PA_CL_UCP3_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F8_PA_CL_UCP3_W, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285FC_PA_CL_UCP4_X, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028600_PA_CL_UCP4_Y, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028604_PA_CL_UCP4_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028608_PA_CL_UCP4_W, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02860C_PA_CL_UCP5_X, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028610_PA_CL_UCP5_Y, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028614_PA_CL_UCP5_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028618_PA_CL_UCP5_W, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_2, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_3, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_4, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_5, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_6, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_7, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02863C_SPI_VS_OUT_ID_8, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028640_SPI_VS_OUT_ID_9, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E0_SPI_BARYC_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, 1, S_0085F0_SH_ACTION_ENA(1)},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02884C_SQ_PGM_EXPORTS_PS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02885C_SQ_PGM_START_VS, 1, S_0085F0_SH_ACTION_ENA(1)},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028860_SQ_PGM_RESOURCES_VS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_START_FS, 1, S_0085F0_SH_ACTION_ENA(1)},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, 1, S_0085F0_SH_ACTION_ENA(1)},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, 1, S_0085F0_SH_ACTION_ENA(1)},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL_1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028ABC_DB_HTILE_SURFACE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B54_VGT_SHADER_STAGES_EN, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B70_DB_ALPHA_TO_MASK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B94_VGT_STRMOUT_CONFIG, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C3C_PA_SC_AA_MASK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C60_CB_COLOR0_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C64_CB_COLOR0_PITCH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C68_CB_COLOR0_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C6C_CB_COLOR0_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C70_CB_COLOR0_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C74_CB_COLOR0_ATTRIB, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C78_CB_COLOR0_DIM, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C9C_CB_COLOR1_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA0_CB_COLOR1_PITCH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA4_CB_COLOR1_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA8_CB_COLOR1_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CAC_CB_COLOR1_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CB0_CB_COLOR1_ATTRIB, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CB4_CB_COLOR1_DIM, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CD8_CB_COLOR2_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CDC_CB_COLOR2_PITCH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE0_CB_COLOR2_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE4_CB_COLOR2_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE8_CB_COLOR2_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CEC_CB_COLOR2_ATTRIB, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CF0_CB_COLOR2_DIM, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D14_CB_COLOR3_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D18_CB_COLOR3_PITCH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D1C_CB_COLOR3_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D20_CB_COLOR3_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D24_CB_COLOR3_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D28_CB_COLOR3_ATTRIB, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D2C_CB_COLOR3_DIM, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D50_CB_COLOR4_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D54_CB_COLOR4_PITCH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D58_CB_COLOR4_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D5C_CB_COLOR4_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D60_CB_COLOR4_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D64_CB_COLOR4_ATTRIB, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D68_CB_COLOR4_DIM, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D8C_CB_COLOR5_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D90_CB_COLOR5_PITCH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D94_CB_COLOR5_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D98_CB_COLOR5_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D9C_CB_COLOR5_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DA0_CB_COLOR5_ATTRIB, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DA4_CB_COLOR5_DIM, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DC8_CB_COLOR6_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DCC_CB_COLOR6_PITCH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD0_CB_COLOR6_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD4_CB_COLOR6_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD8_CB_COLOR6_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DDC_CB_COLOR6_ATTRIB, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DE0_CB_COLOR6_DIM, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E04_CB_COLOR7_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E08_CB_COLOR7_PITCH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E0C_CB_COLOR7_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E10_CB_COLOR7_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E14_CB_COLOR7_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E18_CB_COLOR7_ATTRIB, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E1C_CB_COLOR7_DIM, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E40_CB_COLOR8_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E44_CB_COLOR8_PITCH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E48_CB_COLOR8_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E4C_CB_COLOR8_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E50_CB_COLOR8_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E54_CB_COLOR8_ATTRIB, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E58_CB_COLOR8_DIM, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E5C_CB_COLOR9_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E60_CB_COLOR9_PITCH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E64_CB_COLOR9_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E68_CB_COLOR9_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E6C_CB_COLOR9_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E70_CB_COLOR9_ATTRIB, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E74_CB_COLOR9_DIM, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E78_CB_COLOR10_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E7C_CB_COLOR10_PITCH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E80_CB_COLOR10_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E84_CB_COLOR10_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E88_CB_COLOR10_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E8C_CB_COLOR10_ATTRIB, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E90_CB_COLOR10_DIM, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E94_CB_COLOR11_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E98_CB_COLOR11_PITCH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E9C_CB_COLOR11_SLICE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA0_CB_COLOR11_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA4_CB_COLOR11_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA8_CB_COLOR11_ATTRIB, 1, 0},
+	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EAC_CB_COLOR11_DIM, 0, 0},
+};
+
+/* SHADER RESOURCE R600/R700 */
+static int evergreen_state_resource_init(struct r600_context *ctx, u32 offset)
+{
+	struct r600_reg r600_shader_resource[] = {
+		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030000_RESOURCE0_WORD0, 0, 0},
+		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030004_RESOURCE0_WORD1, 0, 0},
+		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030008_RESOURCE0_WORD2, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1)},
+		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_03000C_RESOURCE0_WORD3, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1)},
+		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030010_RESOURCE0_WORD4, 0, 0},
+		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030014_RESOURCE0_WORD5, 0, 0},
+		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030018_RESOURCE0_WORD6, 0, 0},
+		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_03001C_RESOURCE0_WORD7, 0, 0},
+	};
+	unsigned nreg = Elements(r600_shader_resource);
+
+	for (int i = 0; i < nreg; i++) {
+		r600_shader_resource[i].offset += offset;
+	}
+	return r600_context_add_block(ctx, r600_shader_resource, nreg);
+}
+
+/* SHADER SAMPLER R600/R700 */
+static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
+{
+	struct r600_reg r600_shader_sampler[] = {
+		{PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0},
+		{PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0},
+		{PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0},
+	};
+	unsigned nreg = Elements(r600_shader_sampler);
+
+	for (int i = 0; i < nreg; i++) {
+		r600_shader_sampler[i].offset += offset;
+	}
+	return r600_context_add_block(ctx, r600_shader_sampler, nreg);
+}
+
+/* SHADER SAMPLER BORDER R600/R700 */
+static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 offset, unsigned id)
+{
+	struct r600_reg r600_shader_sampler_border[] = {
+		{PKT3_SET_CONFIG_REG, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0},
+		{PKT3_SET_CONFIG_REG, 0, R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
+		{PKT3_SET_CONFIG_REG, 0, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
+		{PKT3_SET_CONFIG_REG, 0, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
+		{PKT3_SET_CONFIG_REG, 0, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
+	};
+	unsigned nreg = Elements(r600_shader_sampler_border);
+	unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
+	struct r600_range *range;
+	struct r600_block *block;
+	int r;
+
+	for (int i = 0; i < nreg; i++) {
+		r600_shader_sampler_border[i].offset -= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX;
+		r600_shader_sampler_border[i].offset += fake_offset;
+	}
+	r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg);
+	if (r) {
+		return r;
+	}
+	/* set proper offset */
+	range = &ctx->range[CTX_RANGE_ID(ctx, r600_shader_sampler_border[0].offset)];
+	block = range->blocks[CTX_BLOCK_ID(ctx, r600_shader_sampler_border[0].offset)];
+	block->pm4[1] = (offset - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
+	return 0;
+}
+
+static int evergreen_loop_const_init(struct r600_context *ctx, u32 offset)
+{
+	unsigned nreg = 32;
+	struct r600_reg r600_loop_consts[32];
+	int i;
+
+	for (i = 0; i < nreg; i++) {
+		r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST;
+		r600_loop_consts[i].offset_base = EVERGREEN_LOOP_CONST_OFFSET;
+		r600_loop_consts[i].offset = EVERGREEN_LOOP_CONST_OFFSET + ((offset + i) * 4);
+		r600_loop_consts[i].need_bo = 0;
+		r600_loop_consts[i].flush_flags = 0;
+	}
+	return r600_context_add_block(ctx, r600_loop_consts, nreg);
+}
+
+int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
+{
+	int r;
+
+	memset(ctx, 0, sizeof(struct r600_context));
+	ctx->radeon = radeon;
+	LIST_INITHEAD(&ctx->query_list);
+
+	/* initialize hash */
+	ctx->hash_size = 19;
+	ctx->hash_shift = 11;
+	for (int i = 0; i < 256; i++) {
+		ctx->range[i].start_offset = i << ctx->hash_shift;
+		ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1;
+		ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*));
+		if (ctx->range[i].blocks == NULL) {
+			return -ENOMEM;
+		}
+	}
+
+	/* add blocks */
+	r = r600_context_add_block(ctx, evergreen_config_reg_list,
+				   Elements(evergreen_config_reg_list));
+	if (r)
+		goto out_err;
+	r = r600_context_add_block(ctx, evergreen_context_reg_list,
+				   Elements(evergreen_context_reg_list));
+	if (r)
+		goto out_err;
+	r = r600_context_add_block(ctx, evergreen_ctl_const_list,
+				   Elements(evergreen_ctl_const_list));
+	if (r)
+		goto out_err;
+
+
+	/* PS SAMPLER */
+	for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
+		r = r600_state_sampler_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* VS SAMPLER */
+	for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
+		r = r600_state_sampler_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* PS SAMPLER BORDER */
+	for (int j = 0; j < 18; j++) {
+		r = evergreen_state_sampler_border_init(ctx, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, j);
+		if (r)
+			goto out_err;
+	}
+	/* VS SAMPLER BORDER */
+	for (int j = 0; j < 18; j++) {
+		r = evergreen_state_sampler_border_init(ctx, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, j);
+		if (r)
+			goto out_err;
+	}
+	/* PS RESOURCE */
+	for (int j = 0, offset = 0; j < 176; j++, offset += 0x20) {
+		r = evergreen_state_resource_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* VS RESOURCE */
+	for (int j = 0, offset = 0x1600; j < 160; j++, offset += 0x20) {
+		r = evergreen_state_resource_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+
+	/* PS loop const */
+	evergreen_loop_const_init(ctx, 0);
+	/* VS loop const */
+	evergreen_loop_const_init(ctx, 32);
+
+	/* setup block table */
+	ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
+	for (int i = 0, c = 0; i < 256; i++) {
+		for (int j = 0; j < (1 << ctx->hash_shift); j++) {
+			if (ctx->range[i].blocks[j]) {
+				assert(c < ctx->nblocks);
+				ctx->blocks[c++] = ctx->range[i].blocks[j];
+				j += (ctx->range[i].blocks[j]->nreg << 2) - 1;
+			}
+		}
+	}
+
+	/* allocate cs variables */
+	ctx->nreloc = RADEON_CTX_MAX_PM4;
+	ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
+	if (ctx->reloc == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	ctx->bo = calloc(ctx->nreloc, sizeof(void *));
+	if (ctx->bo == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
+	ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
+	if (ctx->pm4 == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	return 0;
+out_err:
+	r600_context_fini(ctx);
+	return r;
+}
+
+static inline void evergreen_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+	struct r600_range *range;
+	struct r600_block *block;
+
+	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
+	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	if (state == NULL) {
+		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+		r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+		r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+		return;
+	}
+	block->reg[0] = state->regs[0].value;
+	block->reg[1] = state->regs[1].value;
+	block->reg[2] = state->regs[2].value;
+	block->reg[3] = state->regs[3].value;
+	block->reg[4] = state->regs[4].value;
+	block->reg[5] = state->regs[5].value;
+	block->reg[6] = state->regs[6].value;
+	block->reg[7] = state->regs[7].value;
+	r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+	r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+	if (state->regs[0].bo) {
+		/* VERTEX RESOURCE, we preted there is 2 bo to relocate so
+		 * we have single case btw VERTEX & TEXTURE resource
+		 */
+		r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
+		r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
+	} else {
+		/* TEXTURE RESOURCE */
+		r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
+		r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
+	}
+	if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
+		block->status |= R600_BLOCK_STATUS_ENABLED;
+		block->status |= R600_BLOCK_STATUS_DIRTY;
+		ctx->pm4_dirty_cdwords += block->pm4_ndwords;
+	}
+}
+
+void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+	unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x20 * rid;
+
+	evergreen_context_pipe_state_set_resource(ctx, state, offset);
+}
+
+void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+	unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x1600 + 0x20 * rid;
+
+	evergreen_context_pipe_state_set_resource(ctx, state, offset);
+}
+
+static inline void evergreen_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+	struct r600_range *range;
+	struct r600_block *block;
+
+	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
+	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	if (state == NULL) {
+		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+		return;
+	}
+	block->reg[0] = state->regs[0].value;
+	block->reg[1] = state->regs[1].value;
+	block->reg[2] = state->regs[2].value;
+	if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
+		block->status |= R600_BLOCK_STATUS_ENABLED;
+		block->status |= R600_BLOCK_STATUS_DIRTY;
+		ctx->pm4_dirty_cdwords += block->pm4_ndwords;
+	}
+}
+
+static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset, unsigned id)
+{
+	unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
+	struct r600_range *range;
+	struct r600_block *block;
+
+	range = &ctx->range[CTX_RANGE_ID(ctx, fake_offset)];
+	block = range->blocks[CTX_BLOCK_ID(ctx, fake_offset)];
+	if (state == NULL) {
+		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+		return;
+	}
+	if (state->nregs <= 3) {
+		return;
+	}
+	block->reg[0] = id;
+	block->reg[1] = state->regs[3].value;
+	block->reg[2] = state->regs[4].value;
+	block->reg[3] = state->regs[5].value;
+	block->reg[4] = state->regs[6].value;
+	if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
+		block->status |= R600_BLOCK_STATUS_ENABLED;
+		block->status |= R600_BLOCK_STATUS_DIRTY;
+		ctx->pm4_dirty_cdwords += block->pm4_ndwords;
+	}
+}
+
+void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
+{
+	unsigned offset;
+
+	offset = 0x0003C000 + id * 0xc;
+	evergreen_context_pipe_state_set_sampler(ctx, state, offset);
+	evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, id);
+}
+
+void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
+{
+	unsigned offset;
+
+	offset = 0x0003C0D8 + id * 0xc;
+	evergreen_context_pipe_state_set_sampler(ctx, state, offset);
+	evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, id);
+}
+
+
+void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
+{
+	struct r600_bo *cb[12];
+	struct r600_bo *db;
+	unsigned ndwords = 9;
+
+	if (draw->indices) {
+		ndwords = 13;
+		/* make sure there is enough relocation space before scheduling draw */
+		if (ctx->creloc >= (ctx->nreloc - 1)) {
+			r600_context_flush(ctx);
+		}
+	}
+
+	/* find number of color buffer */
+	db = r600_context_reg_bo(ctx, R_028048_DB_Z_READ_BASE);
+	cb[0] = r600_context_reg_bo(ctx, R_028C60_CB_COLOR0_BASE);
+	cb[1] = r600_context_reg_bo(ctx, R_028C9C_CB_COLOR1_BASE);
+	cb[2] = r600_context_reg_bo(ctx, R_028CD8_CB_COLOR2_BASE);
+	cb[3] = r600_context_reg_bo(ctx, R_028D14_CB_COLOR3_BASE);
+	cb[4] = r600_context_reg_bo(ctx, R_028D50_CB_COLOR4_BASE);
+	cb[5] = r600_context_reg_bo(ctx, R_028D8C_CB_COLOR5_BASE);
+	cb[6] = r600_context_reg_bo(ctx, R_028DC8_CB_COLOR6_BASE);
+	cb[7] = r600_context_reg_bo(ctx, R_028E04_CB_COLOR7_BASE);
+	cb[8] = r600_context_reg_bo(ctx, R_028E40_CB_COLOR8_BASE);
+	cb[9] = r600_context_reg_bo(ctx, R_028E5C_CB_COLOR9_BASE);
+	cb[10] = r600_context_reg_bo(ctx, R_028E78_CB_COLOR10_BASE);
+	cb[11] = r600_context_reg_bo(ctx, R_028E94_CB_COLOR11_BASE);
+	for (int i = 0; i < 12; i++) {
+		if (cb[i]) {
+			ndwords += 7;
+		}
+	}
+	if (db)
+		ndwords += 7;
+
+	/* queries need some special values */
+	if (ctx->num_query_running) {
+		r600_context_reg(ctx,
+				R_028004_DB_COUNT_CONTROL,
+				S_028004_PERFECT_ZPASS_COUNTS(1),
+				S_028004_PERFECT_ZPASS_COUNTS(1));
+		r600_context_reg(ctx,
+				R_02800C_DB_RENDER_OVERRIDE,
+				S_02800C_NOOP_CULL_DISABLE(1),
+				S_02800C_NOOP_CULL_DISABLE(1));
+	}
+
+	if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
+		/* need to flush */
+		r600_context_flush(ctx);
+	}
+	/* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
+	if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
+		R600_ERR("context is too big to be scheduled\n");
+		return;
+	}
+
+	/* enough room to copy packet */
+	for (int i = 0; i < ctx->nblocks; i++) {
+		if (ctx->blocks[i]->status & R600_BLOCK_STATUS_DIRTY) {
+			r600_context_block_emit_dirty(ctx, ctx->blocks[i]);
+		}
+	}
+
+	/* draw packet */
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
+	if (draw->indices) {
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3);
+		ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
+		ctx->pm4[ctx->pm4_cdwords++] = 0;
+		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
+		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
+		ctx->pm4[ctx->pm4_cdwords++] = 0;
+		r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices);
+	} else {
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
+		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
+		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
+	}
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
+
+	/* flush color buffer */
+	for (int i = 0; i < 12; i++) {
+		if (cb[i]) {
+			ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
+			if (i > 7)
+				ctx->pm4[ctx->pm4_cdwords++] = (S_0085F0_CB8_DEST_BASE_ENA(1) << (i - 8)) |
+					S_0085F0_CB_ACTION_ENA(1);
+			else
+				ctx->pm4[ctx->pm4_cdwords++] = (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
+					S_0085F0_CB_ACTION_ENA(1);
+			ctx->pm4[ctx->pm4_cdwords++] = (cb[i]->size + 255) >> 8;
+			ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
+			ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
+			ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
+			ctx->pm4[ctx->pm4_cdwords++] = 0;
+			r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], cb[i]);
+		}
+	}
+	if (db) {
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
+		ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_DB_DEST_BASE_ENA(1) |
+			S_0085F0_DB_ACTION_ENA(1);
+		ctx->pm4[ctx->pm4_cdwords++] = (db->size + 255) >> 8;
+		ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
+		ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
+		ctx->pm4[ctx->pm4_cdwords++] = 0;
+		r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], db);
+	}
+
+	/* all dirty state have been scheduled in current cs */
+	ctx->pm4_dirty_cdwords = 0;
+}
+
+static inline void evergreen_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+	struct r600_range *range;
+	struct r600_block *block;
+
+	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
+	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	block->reg[0] = state->regs[0].value;
+	block->reg[1] = state->regs[1].value;
+	block->reg[2] = state->regs[2].value;
+	block->reg[3] = state->regs[3].value;
+	block->reg[4] = state->regs[4].value;
+	block->reg[5] = state->regs[5].value;
+	block->reg[6] = state->regs[6].value;
+	block->reg[7] = state->regs[7].value;
+	r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+	r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+	if (state->regs[0].bo) {
+		/* VERTEX RESOURCE, we preted there is 2 bo to relocate so
+		 * we have single case btw VERTEX & TEXTURE resource
+		 */
+		r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
+		r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
+	} else {
+		/* TEXTURE RESOURCE */
+		r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
+		r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
+	}
+	if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
+		block->status |= R600_BLOCK_STATUS_ENABLED;
+		block->status |= R600_BLOCK_STATUS_DIRTY;
+		ctx->pm4_dirty_cdwords += block->pm4_ndwords;
+	}
+}
+
+void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+	unsigned offset = R_030000_RESOURCE0_WORD0 + 0x20 * rid;
+
+	evergreen_resource_set(ctx, state, offset);
+}
+
+void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+	unsigned offset = R_030000_RESOURCE0_WORD0 + 0x1600 + 0x20 * rid;
+
+	evergreen_resource_set(ctx, state, offset);
+}
diff --git a/src/gallium/winsys/r600/drm/r600.c b/src/gallium/winsys/r600/drm/r600.c
new file mode 100644
index 00000000000..496547ca994
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/r600.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include "xf86drm.h"
+#include "radeon_drm.h"
+#include "pipe/p_compiler.h"
+#include "util/u_inlines.h"
+#include <pipebuffer/pb_bufmgr.h>
+#include "r600_priv.h"
+
+enum radeon_family r600_get_family(struct radeon *r600)
+{
+	return r600->family;
+}
+
+enum chip_class r600_get_family_class(struct radeon *radeon)
+{
+	return radeon->chip_class;
+}
+
+static int r600_get_device(struct radeon *r600)
+{
+	struct drm_radeon_info info;
+
+	r600->device = 0;
+	info.request = RADEON_INFO_DEVICE_ID;
+	info.value = (uintptr_t)&r600->device;
+	return drmCommandWriteRead(r600->fd, DRM_RADEON_INFO, &info, sizeof(struct drm_radeon_info));
+}
+
+struct radeon *r600_new(int fd, unsigned device)
+{
+	struct radeon *r600;
+	int r;
+
+	r600 = calloc(1, sizeof(*r600));
+	if (r600 == NULL) {
+		return NULL;
+	}
+	r600->fd = fd;
+	r600->device = device;
+	if (fd >= 0) {
+		r = r600_get_device(r600);
+		if (r) {
+			R600_ERR("Failed to get device id\n");
+			r600_delete(r600);
+			return NULL;
+		}
+	}
+	r600->family = radeon_family_from_device(r600->device);
+	if (r600->family == CHIP_UNKNOWN) {
+		R600_ERR("Unknown chipset 0x%04X\n", r600->device);
+		r600_delete(r600);
+		return NULL;
+	}
+	switch (r600->family) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		break;
+	case CHIP_R100:
+	case CHIP_RV100:
+	case CHIP_RS100:
+	case CHIP_RV200:
+	case CHIP_RS200:
+	case CHIP_R200:
+	case CHIP_RV250:
+	case CHIP_RS300:
+	case CHIP_RV280:
+	case CHIP_R300:
+	case CHIP_R350:
+	case CHIP_RV350:
+	case CHIP_RV380:
+	case CHIP_R420:
+	case CHIP_R423:
+	case CHIP_RV410:
+	case CHIP_RS400:
+	case CHIP_RS480:
+	case CHIP_RS600:
+	case CHIP_RS690:
+	case CHIP_RS740:
+	case CHIP_RV515:
+	case CHIP_R520:
+	case CHIP_RV530:
+	case CHIP_RV560:
+	case CHIP_RV570:
+	case CHIP_R580:
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+	default:
+		R600_ERR("unknown or unsupported chipset 0x%04X\n", r600->device);
+		break;
+	}
+
+	/* setup class */
+	switch (r600->family) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+		r600->chip_class = R600;
+		break;
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		r600->chip_class = R700;
+		break;
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+		r600->chip_class = EVERGREEN;
+		break;
+	default:
+		R600_ERR("unknown or unsupported chipset 0x%04X\n", r600->device);
+		break;
+	}
+
+	return r600;
+}
+
+void r600_delete(struct radeon *r600)
+{
+	if (r600 == NULL)
+		return;
+	drmClose(r600->fd);
+	free(r600);
+}
diff --git a/src/gallium/winsys/r600/drm/r600_bo.c b/src/gallium/winsys/r600/drm/r600_bo.c
new file mode 100644
index 00000000000..9498f3a82ea
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/r600_bo.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2010 Dave Airlie
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Dave Airlie
+ */
+#include <pipe/p_compiler.h>
+#include <pipe/p_screen.h>
+#include <pipebuffer/pb_bufmgr.h>
+#include "r600_priv.h"
+
+struct r600_bo *r600_bo(struct radeon *radeon,
+				  unsigned size, unsigned alignment, unsigned usage)
+{
+	struct r600_bo *ws_bo = calloc(1, sizeof(struct r600_bo));
+	struct pb_desc desc;
+	struct pb_manager *man;
+
+	desc.alignment = alignment;
+	desc.usage = usage;
+	ws_bo->size = size;
+
+	if (usage & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
+		man = radeon->cman;
+	else
+		man = radeon->kman;
+
+	ws_bo->pb = man->create_buffer(man, size, &desc);
+	if (ws_bo->pb == NULL) {
+		free(ws_bo);
+		return NULL;
+	}
+
+	pipe_reference_init(&ws_bo->reference, 1);
+	return ws_bo;
+}
+
+struct r600_bo *r600_bo_handle(struct radeon *radeon,
+					 unsigned handle)
+{
+	struct r600_bo *ws_bo = calloc(1, sizeof(struct r600_bo));
+	struct radeon_bo *bo;
+
+	ws_bo->pb = radeon_bo_pb_create_buffer_from_handle(radeon->kman, handle);
+	if (!ws_bo->pb) {
+		free(ws_bo);
+		return NULL;
+	}
+	bo = radeon_bo_pb_get_bo(ws_bo->pb);
+	ws_bo->size = bo->size;
+	pipe_reference_init(&ws_bo->reference, 1);
+	return ws_bo;
+}
+
+void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx)
+{
+	return pb_map(bo->pb, usage, ctx);
+}
+
+void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo)
+{
+	pb_unmap(bo->pb);
+}
+
+static void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo)
+{
+	if (bo->pb)
+		pb_reference(&bo->pb, NULL);
+	free(bo);
+}
+
+void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst,
+			    struct r600_bo *src)
+{
+	struct r600_bo *old = *dst;
+ 		
+	if (pipe_reference(&(*dst)->reference, &src->reference)) {
+		r600_bo_destroy(radeon, old);
+	}
+	*dst = src;
+}
+
+unsigned r600_bo_get_handle(struct r600_bo *pb_bo)
+{
+	struct radeon_bo *bo;
+
+	bo = radeon_bo_pb_get_bo(pb_bo->pb);
+	if (!bo)
+		return 0;
+
+	return bo->handle;
+}
+
+unsigned r600_bo_get_size(struct r600_bo *pb_bo)
+{
+	struct radeon_bo *bo;
+
+	bo = radeon_bo_pb_get_bo(pb_bo->pb);
+	if (!bo)
+		return 0;
+
+	return bo->size;
+}
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
new file mode 100644
index 00000000000..5f175a4df98
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ *      Corbin Simpson <[email protected]>
+ *      Joakim Sindholt <[email protected]>
+ */
+#include <stdio.h>
+#include <errno.h>
+#include <sys/ioctl.h>
+#include "util/u_inlines.h"
+#include "util/u_debug.h"
+#include <pipebuffer/pb_bufmgr.h>
+#include "r600.h"
+#include "r600_priv.h"
+#include "r600_drm_public.h"
+#include "xf86drm.h"
+#include "radeon_drm.h"
+
+static int radeon_get_device(struct radeon *radeon)
+{
+	struct drm_radeon_info info;
+	int r;
+
+	radeon->device = 0;
+	info.request = RADEON_INFO_DEVICE_ID;
+	info.value = (uintptr_t)&radeon->device;
+	r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
+			sizeof(struct drm_radeon_info));
+	return r;
+}
+
+struct radeon *radeon_new(int fd, unsigned device)
+{
+	struct radeon *radeon;
+	int r;
+
+	radeon = calloc(1, sizeof(*radeon));
+	if (radeon == NULL) {
+		return NULL;
+	}
+	radeon->fd = fd;
+	radeon->device = device;
+	radeon->refcount = 1;
+	if (fd >= 0) {
+		r = radeon_get_device(radeon);
+		if (r) {
+			fprintf(stderr, "Failed to get device id\n");
+			return radeon_decref(radeon);
+		}
+	}
+	radeon->family = radeon_family_from_device(radeon->device);
+	if (radeon->family == CHIP_UNKNOWN) {
+		fprintf(stderr, "Unknown chipset 0x%04X\n", radeon->device);
+		return radeon_decref(radeon);
+	}
+	switch (radeon->family) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+		break;
+	case CHIP_R100:
+	case CHIP_RV100:
+	case CHIP_RS100:
+	case CHIP_RV200:
+	case CHIP_RS200:
+	case CHIP_R200:
+	case CHIP_RV250:
+	case CHIP_RS300:
+	case CHIP_RV280:
+	case CHIP_R300:
+	case CHIP_R350:
+	case CHIP_RV350:
+	case CHIP_RV380:
+	case CHIP_R420:
+	case CHIP_R423:
+	case CHIP_RV410:
+	case CHIP_RS400:
+	case CHIP_RS480:
+	case CHIP_RS600:
+	case CHIP_RS690:
+	case CHIP_RS740:
+	case CHIP_RV515:
+	case CHIP_R520:
+	case CHIP_RV530:
+	case CHIP_RV560:
+	case CHIP_RV570:
+	case CHIP_R580:
+	default:
+		fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
+			__func__, radeon->device);
+		break;
+	}
+
+	/* setup class */
+	switch (radeon->family) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+		radeon->chip_class = R600;
+		break;
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		radeon->chip_class = R700;
+		break;
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+		radeon->chip_class = EVERGREEN;
+		break;
+	default:
+		fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
+			__func__, radeon->device);
+		break;
+	}
+
+	radeon->kman = radeon_bo_pbmgr_create(radeon);
+	if (!radeon->kman)
+		return NULL;
+	radeon->cman = pb_cache_manager_create(radeon->kman, 100000);
+	if (!radeon->cman)
+		return NULL;
+	return radeon;
+}
+
+struct radeon *r600_drm_winsys_create(int drmfd)
+{
+	return radeon_new(drmfd, 0);
+}
+
+struct radeon *radeon_decref(struct radeon *radeon)
+{
+	if (radeon == NULL)
+		return NULL;
+	if (--radeon->refcount > 0) {
+		return NULL;
+	}
+
+	radeon->cman->destroy(radeon->cman);
+	radeon->kman->destroy(radeon->kman);
+	drmClose(radeon->fd);
+	free(radeon);
+	return NULL;
+}
diff --git a/src/gallium/winsys/r600/drm/r600_drm_public.h b/src/gallium/winsys/r600/drm/r600_drm_public.h
new file mode 100644
index 00000000000..cfce8df9c2c
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/r600_drm_public.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600_DRM_PUBLIC_H
+#define R600_DRM_PUBLIC_H
+
+struct radeon;
+
+struct radeon *r600_drm_winsys_create(int drmFD);
+
+#endif
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
new file mode 100644
index 00000000000..bee0446d58b
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -0,0 +1,1282 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "xf86drm.h"
+#include "r600.h"
+#include "r600d.h"
+#include "radeon_drm.h"
+#include "bof.h"
+#include "pipe/p_compiler.h"
+#include "util/u_inlines.h"
+#include "util/u_memory.h"
+#include <pipebuffer/pb_bufmgr.h>
+#include "r600_priv.h"
+
+#define GROUP_FORCE_NEW_BLOCK	0
+
+int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
+{
+	struct r600_block *block;
+	struct r600_range *range;
+	int offset;
+
+	for (unsigned i = 0, n = 0; i < nreg; i += n) {
+		u32 j;
+
+		/* ignore new block balise */
+		if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
+			n = 1;
+			continue;
+		}
+
+		/* register that need relocation are in their own group */
+		/* find number of consecutive registers */
+		n = 0;
+		offset = reg[i].offset;
+		while (reg[i + n].offset == offset) {
+			n++;
+			offset += 4;
+			if ((n + i) >= nreg)
+				break;
+			if (n >= (R600_BLOCK_MAX_REG - 2))
+				break;
+		}
+
+		/* allocate new block */
+		block = calloc(1, sizeof(struct r600_block));
+		if (block == NULL) {
+			return -ENOMEM;
+		}
+		ctx->nblocks++;
+		for (int j = 0; j < n; j++) {
+			range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)];
+			range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block;
+		}
+
+		/* initialize block */
+		block->start_offset = reg[i].offset;
+		block->pm4[block->pm4_ndwords++] = PKT3(reg[i].opcode, n);
+		block->pm4[block->pm4_ndwords++] = (block->start_offset - reg[i].offset_base) >> 2;
+		block->reg = &block->pm4[block->pm4_ndwords];
+		block->pm4_ndwords += n;
+		block->nreg = n;
+		for (j = 0; j < n; j++) {
+			if (reg[i+j].need_bo) {
+				block->nbo++;
+				assert(block->nbo < R600_BLOCK_MAX_BO);
+				block->pm4_bo_index[j] = block->nbo;
+				block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0);
+				block->pm4[block->pm4_ndwords++] = 0x00000000;
+				block->reloc[block->nbo].bo_pm4_index[block->reloc[block->nbo].nreloc++] = block->pm4_ndwords - 1;
+			}
+		}
+		for (j = 0; j < n; j++) {
+			if (reg[i+j].flush_flags) {
+				unsigned id;
+
+				block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
+				block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
+				block->pm4[block->pm4_ndwords++] = 0xFFFFFFFF;
+				block->pm4[block->pm4_ndwords++] = 0x00000000;
+				block->pm4[block->pm4_ndwords++] = 0x0000000A;
+				block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0);
+				block->pm4[block->pm4_ndwords++] = 0x00000000;
+				id = block->pm4_bo_index[j];
+				block->reloc[id].bo_pm4_index[block->reloc[id].nreloc++] = block->pm4_ndwords - 1;
+			}
+		}
+		/* check that we stay in limit */
+		assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
+	}
+	return 0;
+}
+
+/* R600/R700 configuration */
+static const struct r600_reg r600_config_reg_list[] = {
+	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
+	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0},
+	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0},
+	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0},
+	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0},
+	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0},
+	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0},
+	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0},
+	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009508_TA_CNTL_AUX, 0, 0},
+	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009714_VC_ENHANCE, 0, 0},
+	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009830_DB_DEBUG, 0, 0},
+	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0},
+};
+
+static const struct r600_reg r600_ctl_const_list[] = {
+	{PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0},
+	{PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
+};
+
+static const struct r600_reg r600_context_reg_list[] = {
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB0_VGT_STRMOUT_EN, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028040_CB_COLOR0_BASE, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028060_CB_COLOR0_SIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028080_CB_COLOR0_VIEW, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E0_CB_COLOR0_FRAG, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C0_CB_COLOR0_TILE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028100_CB_COLOR0_MASK, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028044_CB_COLOR1_BASE, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028064_CB_COLOR1_SIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028084_CB_COLOR1_VIEW, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E4_CB_COLOR1_FRAG, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C4_CB_COLOR1_TILE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028104_CB_COLOR1_MASK, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028048_CB_COLOR2_BASE, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028068_CB_COLOR2_SIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028088_CB_COLOR2_VIEW, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E8_CB_COLOR2_FRAG, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C8_CB_COLOR2_TILE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028108_CB_COLOR2_MASK, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02804C_CB_COLOR3_BASE, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02806C_CB_COLOR3_SIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02808C_CB_COLOR3_VIEW, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280EC_CB_COLOR3_FRAG, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280CC_CB_COLOR3_TILE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02810C_CB_COLOR3_MASK, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028050_CB_COLOR4_BASE, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028070_CB_COLOR4_SIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028090_CB_COLOR4_VIEW, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F0_CB_COLOR4_FRAG, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D0_CB_COLOR4_TILE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028110_CB_COLOR4_MASK, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028054_CB_COLOR5_BASE, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028074_CB_COLOR5_SIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028094_CB_COLOR5_VIEW, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F4_CB_COLOR5_FRAG, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D4_CB_COLOR5_TILE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028114_CB_COLOR5_MASK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028058_CB_COLOR6_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028078_CB_COLOR6_SIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028098_CB_COLOR6_VIEW, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F8_CB_COLOR6_FRAG, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D8_CB_COLOR6_TILE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028118_CB_COLOR6_MASK, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02805C_CB_COLOR7_BASE, 1, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02807C_CB_COLOR7_SIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02809C_CB_COLOR7_VIEW, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280FC_CB_COLOR7_FRAG, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280DC_CB_COLOR7_TILE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02811C_CB_COLOR7_MASK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028120_CB_CLEAR_RED, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028124_CB_CLEAR_GREEN, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028128_CB_CLEAR_BLUE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02812C_CB_CLEAR_ALPHA, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, 1, S_0085F0_SH_ACTION_ENA(1)},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, 1, S_0085F0_SH_ACTION_ENA(1)},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028424_CB_FOG_RED, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028428_CB_FOG_GREEN, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02842C_CB_FOG_BLUE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0287A0_CB_SHADER_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028804_CB_BLEND_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C30_CB_CLRCMP_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C34_CB_CLRCMP_SRC, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C38_CB_CLRCMP_DST, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C3C_CB_CLRCMP_MSK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C48_PA_SC_AA_MASK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D44_DB_ALPHA_TO_MASK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02800C_DB_DEPTH_BASE, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028000_DB_DEPTH_SIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028004_DB_DEPTH_VIEW, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028010_DB_DEPTH_INFO, 1, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D0C_DB_RENDER_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D10_DB_RENDER_OVERRIDE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D24_DB_HTILE_SURFACE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D30_DB_PRELOAD_CONTROL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D34_DB_PREFETCH_LIMIT, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E20_PA_CL_UCP0_X, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E24_PA_CL_UCP0_Y, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E28_PA_CL_UCP0_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E2C_PA_CL_UCP0_W, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E30_PA_CL_UCP1_X, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E34_PA_CL_UCP1_Y, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E38_PA_CL_UCP1_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E3C_PA_CL_UCP1_W, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E40_PA_CL_UCP2_X, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E44_PA_CL_UCP2_Y, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E48_PA_CL_UCP2_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E4C_PA_CL_UCP2_W, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E50_PA_CL_UCP3_X, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E54_PA_CL_UCP3_Y, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E58_PA_CL_UCP3_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E5C_PA_CL_UCP3_W, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E60_PA_CL_UCP4_X, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E64_PA_CL_UCP4_Y, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E68_PA_CL_UCP4_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E6C_PA_CL_UCP4_W, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E70_PA_CL_UCP5_X, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E74_PA_CL_UCP5_Y, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E78_PA_CL_UCP5_Z, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E7C_PA_CL_UCP5_W, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028614_SPI_VS_OUT_ID_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028618_SPI_VS_OUT_ID_1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_2, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_3, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_4, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_5, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_6, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_7, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_8, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_9, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028858_SQ_PGM_START_VS, 1, S_0085F0_SH_ACTION_ENA(1)},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028868_SQ_PGM_RESOURCES_VS, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028894_SQ_PGM_START_FS, 1, S_0085F0_SH_ACTION_ENA(1)},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, 1, S_0085F0_SH_ACTION_ENA(1)},
+	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A84_VGT_PRIMITIVEID_EN, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0},
+};
+
+/* SHADER RESOURCE R600/R700 */
+static int r600_state_resource_init(struct r600_context *ctx, u32 offset)
+{
+	struct r600_reg r600_shader_resource[] = {
+		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038000_RESOURCE0_WORD0, 0, 0},
+		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038004_RESOURCE0_WORD1, 0, 0},
+		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038008_RESOURCE0_WORD2, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1)},
+		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_03800C_RESOURCE0_WORD3, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1)},
+		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038010_RESOURCE0_WORD4, 0, 0},
+		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038014_RESOURCE0_WORD5, 0, 0},
+		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038018_RESOURCE0_WORD6, 0, 0},
+	};
+	unsigned nreg = Elements(r600_shader_resource);
+
+	for (int i = 0; i < nreg; i++) {
+		r600_shader_resource[i].offset += offset;
+	}
+	return r600_context_add_block(ctx, r600_shader_resource, nreg);
+}
+
+/* SHADER SAMPLER R600/R700 */
+static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
+{
+	struct r600_reg r600_shader_sampler[] = {
+		{PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0},
+		{PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0},
+		{PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0},
+	};
+	unsigned nreg = Elements(r600_shader_sampler);
+
+	for (int i = 0; i < nreg; i++) {
+		r600_shader_sampler[i].offset += offset;
+	}
+	return r600_context_add_block(ctx, r600_shader_sampler, nreg);
+}
+
+/* SHADER SAMPLER BORDER R600/R700 */
+static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
+{
+	struct r600_reg r600_shader_sampler_border[] = {
+		{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
+		{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
+		{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
+		{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
+	};
+	unsigned nreg = Elements(r600_shader_sampler_border);
+
+	for (int i = 0; i < nreg; i++) {
+		r600_shader_sampler_border[i].offset += offset;
+	}
+	return r600_context_add_block(ctx, r600_shader_sampler_border, nreg);
+}
+
+static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
+{
+	unsigned nreg = 32;
+	struct r600_reg r600_loop_consts[32];
+	int i;
+
+	for (i = 0; i < nreg; i++) {
+		r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST;
+		r600_loop_consts[i].offset_base = R600_LOOP_CONST_OFFSET;
+		r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
+		r600_loop_consts[i].need_bo = 0;
+		r600_loop_consts[i].flush_flags = 0;
+	}
+	return r600_context_add_block(ctx, r600_loop_consts, nreg);
+}
+
+/* initialize */
+void r600_context_fini(struct r600_context *ctx)
+{
+	struct r600_block *block;
+	struct r600_range *range;
+
+	for (int i = 0; i < 256; i++) {
+		for (int j = 0; j < (1 << ctx->hash_shift); j++) {
+			block = ctx->range[i].blocks[j];
+			if (block) {
+				for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
+					range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
+					range->blocks[CTX_BLOCK_ID(ctx, offset)] = NULL;
+				}
+				free(block);
+			}
+		}
+		free(ctx->range[i].blocks);
+	}
+	free(ctx->reloc);
+	free(ctx->pm4);
+	memset(ctx, 0, sizeof(struct r600_context));
+}
+
+int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
+{
+	int r;
+
+	memset(ctx, 0, sizeof(struct r600_context));
+	ctx->radeon = radeon;
+	LIST_INITHEAD(&ctx->query_list);
+
+	/* initialize hash */
+	ctx->hash_size = 19;
+	ctx->hash_shift = 11;
+	for (int i = 0; i < 256; i++) {
+		ctx->range[i].start_offset = i << ctx->hash_shift;
+		ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1;
+		ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*));
+		if (ctx->range[i].blocks == NULL) {
+			return -ENOMEM;
+		}
+	}
+
+	/* add blocks */
+	r = r600_context_add_block(ctx, r600_config_reg_list,
+				   Elements(r600_config_reg_list));
+	if (r)
+		goto out_err;
+	r = r600_context_add_block(ctx, r600_context_reg_list,
+				   Elements(r600_context_reg_list));
+	if (r)
+		goto out_err;
+	r = r600_context_add_block(ctx, r600_ctl_const_list,
+				   Elements(r600_ctl_const_list));
+	if (r)
+		goto out_err;
+
+	/* PS SAMPLER BORDER */
+	for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
+		r = r600_state_sampler_border_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+
+	/* VS SAMPLER BORDER */
+	for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
+		r = r600_state_sampler_border_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* PS SAMPLER */
+	for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
+		r = r600_state_sampler_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* VS SAMPLER */
+	for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
+		r = r600_state_sampler_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* PS RESOURCE */
+	for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) {
+		r = r600_state_resource_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* VS RESOURCE */
+	for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) {
+		r = r600_state_resource_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+
+	/* PS loop const */
+	r600_loop_const_init(ctx, 0);
+	/* VS loop const */
+	r600_loop_const_init(ctx, 32);
+
+	/* setup block table */
+	ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
+	for (int i = 0, c = 0; i < 256; i++) {
+		for (int j = 0, add; j < (1 << ctx->hash_shift); j++) {
+			if (ctx->range[i].blocks[j]) {
+				add = 1;
+				for (int k = 0; k < c; k++) {
+					if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
+						add = 0;
+						break;
+					}
+				}
+				if (add) {
+					assert(c < ctx->nblocks);
+					ctx->blocks[c++] = ctx->range[i].blocks[j];
+					j += (ctx->range[i].blocks[j]->nreg << 2) - 1;
+				}
+			}
+		}
+	}
+
+	/* allocate cs variables */
+	ctx->nreloc = RADEON_CTX_MAX_PM4;
+	ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
+	if (ctx->reloc == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	ctx->bo = calloc(ctx->nreloc, sizeof(void *));
+	if (ctx->bo == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
+	ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
+	if (ctx->pm4 == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	return 0;
+out_err:
+	r600_context_fini(ctx);
+	return r;
+}
+
+void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo)
+{
+	struct radeon_bo *bo;
+	int i, reloc_id;
+
+	bo = r600_bo_get_bo(rbo);
+	assert(bo != NULL);
+	for (i = 0, reloc_id = -1; i < ctx->creloc; i++) {
+		if (ctx->reloc[i].handle == bo->handle) {
+			reloc_id = i * sizeof(struct r600_reloc) / 4;
+			/* set PKT3 to point to proper reloc */
+			*pm4 = reloc_id;
+			break;
+		}
+	}
+	if (reloc_id == -1) {
+		/* add new relocation */
+		if (ctx->creloc >= ctx->nreloc) {
+			r600_context_flush(ctx);
+		}
+		reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
+		ctx->reloc[ctx->creloc].handle = bo->handle;
+		ctx->reloc[ctx->creloc].read_domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
+		ctx->reloc[ctx->creloc].write_domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
+		ctx->reloc[ctx->creloc].flags = 0;
+		radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
+		ctx->creloc++;
+		/* set PKT3 to point to proper reloc */
+		*pm4 = reloc_id;
+	}
+}
+
+void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
+{
+	struct r600_range *range;
+	struct r600_block *block;
+
+	for (int i = 0; i < state->nregs; i++) {
+		unsigned id;
+
+		range = &ctx->range[CTX_RANGE_ID(ctx, state->regs[i].offset)];
+		block = range->blocks[CTX_BLOCK_ID(ctx, state->regs[i].offset)];
+		id = (state->regs[i].offset - block->start_offset) >> 2;
+		block->reg[id] &= ~state->regs[i].mask;
+		block->reg[id] |= state->regs[i].value;
+		if (block->pm4_bo_index[id]) {
+			/* find relocation */
+			id = block->pm4_bo_index[id];
+			r600_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo);
+		}
+		if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
+			block->status |= R600_BLOCK_STATUS_ENABLED;
+			block->status |= R600_BLOCK_STATUS_DIRTY;
+			ctx->pm4_dirty_cdwords += block->pm4_ndwords;
+		}
+	}
+}
+
+static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+	struct r600_range *range;
+	struct r600_block *block;
+
+	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
+	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	if (state == NULL) {
+		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+		r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+		r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+		return;
+	}
+	block->reg[0] = state->regs[0].value;
+	block->reg[1] = state->regs[1].value;
+	block->reg[2] = state->regs[2].value;
+	block->reg[3] = state->regs[3].value;
+	block->reg[4] = state->regs[4].value;
+	block->reg[5] = state->regs[5].value;
+	block->reg[6] = state->regs[6].value;
+	r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
+	r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
+	if (state->regs[0].bo) {
+		/* VERTEX RESOURCE, we preted there is 2 bo to relocate so
+		 * we have single case btw VERTEX & TEXTURE resource
+		 */
+		r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
+		r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
+	} else {
+		/* TEXTURE RESOURCE */
+		r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
+		r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
+	}
+	if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
+		block->status |= R600_BLOCK_STATUS_ENABLED;
+		block->status |= R600_BLOCK_STATUS_DIRTY;
+		ctx->pm4_dirty_cdwords += block->pm4_ndwords;
+	}
+}
+
+void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+	unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid;
+
+	r600_context_pipe_state_set_resource(ctx, state, offset);
+}
+
+void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+	unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid;
+
+	r600_context_pipe_state_set_resource(ctx, state, offset);
+}
+
+static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+	struct r600_range *range;
+	struct r600_block *block;
+
+	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
+	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	if (state == NULL) {
+		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+		return;
+	}
+	block->reg[0] = state->regs[0].value;
+	block->reg[1] = state->regs[1].value;
+	block->reg[2] = state->regs[2].value;
+	if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
+		block->status |= R600_BLOCK_STATUS_ENABLED;
+		block->status |= R600_BLOCK_STATUS_DIRTY;
+		ctx->pm4_dirty_cdwords += block->pm4_ndwords;
+	}
+}
+
+static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+	struct r600_range *range;
+	struct r600_block *block;
+
+	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
+	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	if (state == NULL) {
+		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+		return;
+	}
+	if (state->nregs <= 3) {
+		return;
+	}
+	block->reg[0] = state->regs[3].value;
+	block->reg[1] = state->regs[4].value;
+	block->reg[2] = state->regs[5].value;
+	block->reg[3] = state->regs[6].value;
+	if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
+		block->status |= R600_BLOCK_STATUS_ENABLED;
+		block->status |= R600_BLOCK_STATUS_DIRTY;
+		ctx->pm4_dirty_cdwords += block->pm4_ndwords;
+	}
+}
+
+void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
+{
+	unsigned offset;
+
+	offset = 0x0003C000 + id * 0xc;
+	r600_context_pipe_state_set_sampler(ctx, state, offset);
+	offset = 0x0000A400 + id * 0x10;
+	r600_context_pipe_state_set_sampler_border(ctx, state, offset);
+}
+
+void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
+{
+	unsigned offset;
+
+	offset = 0x0003C0D8 + id * 0xc;
+	r600_context_pipe_state_set_sampler(ctx, state, offset);
+	offset = 0x0000A600 + id * 0x10;
+	r600_context_pipe_state_set_sampler_border(ctx, state, offset);
+}
+
+struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
+{
+	struct r600_range *range;
+	struct r600_block *block;
+	unsigned id;
+
+	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
+	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	offset -= block->start_offset;
+	id = block->pm4_bo_index[offset >> 2];
+	if (block->reloc[id].bo) {
+		return block->reloc[id].bo;
+	}
+	return NULL;
+}
+
+void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
+{
+	struct r600_bo *cb[8];
+	struct r600_bo *db;
+	unsigned ndwords = 9;
+
+	if (draw->indices) {
+		ndwords = 13;
+		/* make sure there is enough relocation space before scheduling draw */
+		if (ctx->creloc >= (ctx->nreloc - 1)) {
+			r600_context_flush(ctx);
+		}
+	}
+
+	/* find number of color buffer */
+	db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
+	cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
+	cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
+	cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
+	cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
+	cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
+	cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
+	cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
+	cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
+	for (int i = 0; i < 8; i++) {
+		if (cb[i]) {
+			ndwords += 7;
+		}
+	}
+	if (db)
+		ndwords += 7;
+
+	/* queries need some special values */
+	if (ctx->num_query_running) {
+		if (ctx->radeon->family >= CHIP_RV770) {
+			r600_context_reg(ctx,
+					R_028D0C_DB_RENDER_CONTROL,
+					S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
+					S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
+		}
+		r600_context_reg(ctx,
+				R_028D10_DB_RENDER_OVERRIDE,
+				S_028D10_NOOP_CULL_DISABLE(1),
+				S_028D10_NOOP_CULL_DISABLE(1));
+	}
+
+	if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
+		/* need to flush */
+		r600_context_flush(ctx);
+	}
+	/* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
+	if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
+		R600_ERR("context is too big to be scheduled\n");
+		return;
+	}
+
+	/* enough room to copy packet */
+	for (int i = 0; i < ctx->nblocks; i++) {
+		if (ctx->blocks[i]->status & R600_BLOCK_STATUS_DIRTY) {
+			r600_context_block_emit_dirty(ctx, ctx->blocks[i]);
+		}
+	}
+
+	/* draw packet */
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
+	if (draw->indices) {
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3);
+		ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices);
+		ctx->pm4[ctx->pm4_cdwords++] = 0;
+		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
+		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
+		ctx->pm4[ctx->pm4_cdwords++] = 0;
+		r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices);
+	} else {
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
+		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
+		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
+	}
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
+
+	/* flush color buffer */
+	for (int i = 0; i < 8; i++) {
+		if (cb[i]) {
+			ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
+			ctx->pm4[ctx->pm4_cdwords++] = (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
+							S_0085F0_CB_ACTION_ENA(1);
+			ctx->pm4[ctx->pm4_cdwords++] = (cb[i]->size + 255) >> 8;
+			ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
+			ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
+			ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
+			ctx->pm4[ctx->pm4_cdwords++] = 0;
+			r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], cb[i]);
+		}
+	}
+	if (db) {
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
+		ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_DB_DEST_BASE_ENA(1) |
+			S_0085F0_DB_ACTION_ENA(1);
+		ctx->pm4[ctx->pm4_cdwords++] = (db->size + 255) >> 8;
+		ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
+		ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
+		ctx->pm4[ctx->pm4_cdwords++] = 0;
+		r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], db);
+	}
+
+	/* all dirty state have been scheduled in current cs */
+	ctx->pm4_dirty_cdwords = 0;
+}
+
+void r600_context_flush(struct r600_context *ctx)
+{
+	struct drm_radeon_cs drmib;
+	struct drm_radeon_cs_chunk chunks[2];
+	uint64_t chunk_array[2];
+	int r;
+
+	if (!ctx->pm4_cdwords)
+		return;
+
+	/* suspend queries */
+	r600_context_queries_suspend(ctx);
+
+	radeon_bo_pbmgr_flush_maps(ctx->radeon->kman);
+#if 1
+	/* emit cs */
+	drmib.num_chunks = 2;
+	drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
+	chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
+	chunks[0].length_dw = ctx->pm4_cdwords;
+	chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
+	chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
+	chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
+	chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
+	chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
+	chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
+	r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
+				sizeof(struct drm_radeon_cs));
+#endif
+	/* restart */
+	radeon_bo_fencelist(ctx->radeon, ctx->bo, ctx->creloc);
+	for (int i = 0; i < ctx->creloc; i++) {
+		radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
+	}
+	ctx->creloc = 0;
+	ctx->pm4_dirty_cdwords = 0;
+	ctx->pm4_cdwords = 0;
+
+	/* resume queries */
+	r600_context_queries_resume(ctx);
+
+	/* set all valid group as dirty so they get reemited on
+	 * next draw command
+	 */
+	for (int i = 0; i < ctx->nblocks; i++) {
+		if (ctx->blocks[i]->status & R600_BLOCK_STATUS_ENABLED) {
+			ctx->pm4_dirty_cdwords += ctx->blocks[i]->pm4_ndwords;
+			ctx->blocks[i]->status |= R600_BLOCK_STATUS_DIRTY;
+		}
+	}
+}
+
+void r600_context_dump_bof(struct r600_context *ctx, const char *file)
+{
+	bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
+	unsigned i;
+
+	root = device_id = bcs = blob = array = bo = size = handle = NULL;
+	root = bof_object();
+	if (root == NULL)
+		goto out_err;
+	device_id = bof_int32(ctx->radeon->device);
+	if (device_id == NULL)
+		goto out_err;
+	if (bof_object_set(root, "device_id", device_id))
+		goto out_err;
+	bof_decref(device_id);
+	device_id = NULL;
+	/* dump relocs */
+	blob = bof_blob(ctx->creloc * 16, ctx->reloc);
+	if (blob == NULL)
+		goto out_err;
+	if (bof_object_set(root, "reloc", blob))
+		goto out_err;
+	bof_decref(blob);
+	blob = NULL;
+	/* dump cs */
+	blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4);
+	if (blob == NULL)
+		goto out_err;
+	if (bof_object_set(root, "pm4", blob))
+		goto out_err;
+	bof_decref(blob);
+	blob = NULL;
+	/* dump bo */
+	array = bof_array();
+	if (array == NULL)
+		goto out_err;
+	for (i = 0; i < ctx->creloc; i++) {
+		struct radeon_bo *rbo = ctx->bo[i];
+		bo = bof_object();
+		if (bo == NULL)
+			goto out_err;
+		size = bof_int32(rbo->size);
+		if (size == NULL)
+			goto out_err;
+		if (bof_object_set(bo, "size", size))
+			goto out_err;
+		bof_decref(size);
+		size = NULL;
+		handle = bof_int32(rbo->handle);
+		if (handle == NULL)
+			goto out_err;
+		if (bof_object_set(bo, "handle", handle))
+			goto out_err;
+		bof_decref(handle);
+		handle = NULL;
+		radeon_bo_map(ctx->radeon, rbo);
+		blob = bof_blob(rbo->size, rbo->data);
+		radeon_bo_unmap(ctx->radeon, rbo);
+		if (blob == NULL)
+			goto out_err;
+		if (bof_object_set(bo, "data", blob))
+			goto out_err;
+		bof_decref(blob);
+		blob = NULL;
+		if (bof_array_append(array, bo))
+			goto out_err;
+		bof_decref(bo);
+		bo = NULL;
+	}
+	if (bof_object_set(root, "bo", array))
+		goto out_err;
+	bof_dump_file(root, file);
+out_err:
+	bof_decref(blob);
+	bof_decref(array);
+	bof_decref(bo);
+	bof_decref(size);
+	bof_decref(handle);
+	bof_decref(device_id);
+	bof_decref(root);
+}
+
+static void r600_query_result(struct r600_context *ctx, struct r600_query *query)
+{
+	u64 start, end;
+	u32 *results;
+	int i;
+
+	results = r600_bo_map(ctx->radeon, query->buffer, 0, NULL);
+	for (i = 0; i < query->num_results; i += 4) {
+		start = (u64)results[i] | (u64)results[i + 1] << 32;
+		end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
+		if ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL)) {
+			query->result += end - start;
+		}
+	}
+	r600_bo_unmap(ctx->radeon, query->buffer);
+	query->num_results = 0;
+}
+
+void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
+{
+	/* query request needs 6 dwords for begin + 6 dwords for end */
+	if ((12 + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
+		/* need to flush */
+		r600_context_flush(ctx);
+	}
+
+	/* if query buffer is full force a flush */
+	if (query->num_results >= ((query->buffer_size >> 2) - 2)) {
+		r600_context_flush(ctx);
+		r600_query_result(ctx, query);
+	}
+
+	/* emit begin query */
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2);
+	ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE;
+	ctx->pm4[ctx->pm4_cdwords++] = query->num_results + r600_bo_offset(query->buffer);
+	ctx->pm4[ctx->pm4_cdwords++] = 0;
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = 0;
+	r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
+
+	query->state |= R600_QUERY_STATE_STARTED;
+	query->state ^= R600_QUERY_STATE_ENDED;
+	ctx->num_query_running++;
+}
+
+void r600_query_end(struct r600_context *ctx, struct r600_query *query)
+{
+	/* emit begin query */
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2);
+	ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE;
+	ctx->pm4[ctx->pm4_cdwords++] = query->num_results + 8 + r600_bo_offset(query->buffer);
+	ctx->pm4[ctx->pm4_cdwords++] = 0;
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = 0;
+	r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer);
+
+	query->num_results += 16;
+	query->state ^= R600_QUERY_STATE_STARTED;
+	query->state |= R600_QUERY_STATE_ENDED;
+	ctx->num_query_running--;
+}
+
+struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
+{
+	struct r600_query *query;
+
+	if (query_type != PIPE_QUERY_OCCLUSION_COUNTER)
+		return NULL;
+
+	query = calloc(1, sizeof(struct r600_query));
+	if (query == NULL)
+		return NULL;
+
+	query->type = query_type;
+	query->buffer_size = 4096;
+
+	query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0);
+	if (!query->buffer) {
+		free(query);
+		return NULL;
+	}
+
+	LIST_ADDTAIL(&query->list, &ctx->query_list);
+
+	return query;
+}
+
+void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
+{
+	r600_bo_reference(ctx->radeon, &query->buffer, NULL);
+	LIST_DEL(&query->list);
+	free(query);
+}
+
+boolean r600_context_query_result(struct r600_context *ctx,
+				struct r600_query *query,
+				boolean wait, void *vresult)
+{
+	uint64_t *result = (uint64_t*)vresult;
+
+	if (query->num_results) {
+		r600_context_flush(ctx);
+	}
+	r600_query_result(ctx, query);
+	*result = query->result;
+	query->result = 0;
+	return TRUE;
+}
+
+void r600_context_queries_suspend(struct r600_context *ctx)
+{
+	struct r600_query *query;
+
+	LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
+		if (query->state & R600_QUERY_STATE_STARTED) {
+			r600_query_end(ctx, query);
+			query->state |= R600_QUERY_STATE_SUSPENDED;
+		}
+	}
+}
+
+void r600_context_queries_resume(struct r600_context *ctx)
+{
+	struct r600_query *query;
+
+	LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) {
+		if (query->state & R600_QUERY_STATE_SUSPENDED) {
+			r600_query_begin(ctx, query);
+			query->state ^= R600_QUERY_STATE_SUSPENDED;
+		}
+	}
+}
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
new file mode 100644
index 00000000000..ee48754625a
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600_PRIV_H
+#define R600_PRIV_H
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <pipebuffer/pb_bufmgr.h>
+#include "util/u_double_list.h"
+#include "r600.h"
+
+struct radeon {
+	int				fd;
+	int				refcount;
+	unsigned			device;
+	unsigned			family;
+	enum chip_class			chip_class;
+	struct pb_manager *kman; /* kernel bo manager */
+	struct pb_manager *cman; /* cached bo manager */
+};
+
+struct radeon *r600_new(int fd, unsigned device);
+void r600_delete(struct radeon *r600);
+
+struct r600_reg {
+	unsigned			opcode;
+	unsigned			offset_base;
+	unsigned			offset;
+	unsigned			need_bo;
+	unsigned			flush_flags;
+};
+
+struct radeon_bo {
+	struct pipe_reference		reference;
+	unsigned			handle;
+	unsigned			size;
+	unsigned			alignment;
+	unsigned			map_count;
+	void				*data;
+	struct list_head		fencedlist;
+	boolean				shared;
+	int64_t				last_busy;
+	boolean				set_busy;
+};
+
+struct r600_bo {
+	struct pipe_reference		reference;
+	struct pb_buffer		*pb;
+	unsigned			size;
+};
+
+
+/* radeon_pciid.c */
+unsigned radeon_family_from_device(unsigned device);
+
+/* r600_drm.c */
+struct radeon *radeon_decref(struct radeon *radeon);
+
+/* radeon_bo.c */
+struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
+			    unsigned size, unsigned alignment, void *ptr);
+void radeon_bo_reference(struct radeon *radeon, struct radeon_bo **dst,
+			 struct radeon_bo *src);
+int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
+int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain);
+void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr);
+int radeon_bo_fencelist(struct radeon *radeon, struct radeon_bo **bolist, uint32_t num_bo);
+
+
+/* radeon_bo_pb.c */
+struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf);
+struct pb_manager *radeon_bo_pbmgr_create(struct radeon *radeon);
+struct pb_buffer *radeon_bo_pb_create_buffer_from_handle(struct pb_manager *_mgr,
+							 uint32_t handle);
+
+/* r600_hw_context.c */
+void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo);
+struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset);
+int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg);
+
+/* r600_bo.c */
+unsigned r600_bo_get_handle(struct r600_bo *bo);
+unsigned r600_bo_get_size(struct r600_bo *bo);
+static INLINE struct radeon_bo *r600_bo_get_bo(struct r600_bo *bo)
+{
+	return radeon_bo_pb_get_bo(bo->pb);
+}
+
+#define CTX_RANGE_ID(ctx, offset) (((offset) >> (ctx)->hash_shift) & 255)
+#define CTX_BLOCK_ID(ctx, offset) ((offset) & ((1 << (ctx)->hash_shift) - 1))
+
+static void inline r600_context_reg(struct r600_context *ctx,
+					unsigned offset, unsigned value,
+					unsigned mask)
+{
+	struct r600_range *range;
+	struct r600_block *block;
+	unsigned id;
+
+	range = &ctx->range[CTX_RANGE_ID(ctx, offset)];
+	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
+	id = (offset - block->start_offset) >> 2;
+	block->reg[id] &= ~mask;
+	block->reg[id] |= value;
+	if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
+		ctx->pm4_dirty_cdwords += block->pm4_ndwords;
+		block->status |= R600_BLOCK_STATUS_ENABLED;
+		block->status |= R600_BLOCK_STATUS_DIRTY;
+	}
+}
+
+static inline void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
+{
+	int id;
+
+	for (int j = 0; j < block->nreg; j++) {
+		if (block->pm4_bo_index[j]) {
+			/* find relocation */
+			id = block->pm4_bo_index[j];
+			for (int k = 0; k < block->reloc[id].nreloc; k++) {
+				r600_context_bo_reloc(ctx,
+					&block->pm4[block->reloc[id].bo_pm4_index[k]],
+					block->reloc[id].bo);
+			}
+		}
+	}
+	memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, block->pm4_ndwords * 4);
+	ctx->pm4_cdwords += block->pm4_ndwords;
+	block->status ^= R600_BLOCK_STATUS_DIRTY;
+}
+
+static inline int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo)
+{
+	bo->map_count++;
+	return 0;
+}
+
+static inline void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo)
+{
+	bo->map_count--;
+	assert(bo->map_count >= 0);
+}
+
+#endif
diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
new file mode 100644
index 00000000000..ccc9ffaf8e3
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -0,0 +1,2211 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600D_H
+#define R600D_H
+
+/* evergreen values */
+#define EG_RESOURCE_OFFSET                 0x00030000
+#define EG_RESOURCE_END                    0x00034000
+#define EG_LOOP_CONST_OFFSET               0x0003A200
+#define EG_LOOP_CONST_END                  0x0003A26C
+#define EG_BOOL_CONST_OFFSET               0x0003A500
+#define EG_BOOL_CONST_END                  0x0003A506
+
+
+#define R600_CONFIG_REG_OFFSET                 0X00008000
+#define R600_CONFIG_REG_END                    0X0000AC00
+#define R600_CONTEXT_REG_OFFSET                0X00028000
+#define R600_CONTEXT_REG_END                   0X00029000
+#define R600_ALU_CONST_OFFSET                  0X00030000
+#define R600_ALU_CONST_END                     0X00032000
+#define R600_RESOURCE_OFFSET                   0X00038000
+#define R600_RESOURCE_END                      0X0003C000
+#define R600_SAMPLER_OFFSET                    0X0003C000
+#define R600_SAMPLER_END                       0X0003CFF0
+#define R600_CTL_CONST_OFFSET                  0X0003CFF0
+#define R600_CTL_CONST_END                     0X0003E200
+#define R600_LOOP_CONST_OFFSET                 0X0003E200
+#define R600_LOOP_CONST_END                    0X0003E380
+#define R600_BOOL_CONST_OFFSET                 0X0003E380
+#define R600_BOOL_CONST_END                    0X00040000
+
+#define PKT3_NOP                               0x10
+#define PKT3_INDIRECT_BUFFER_END               0x17
+#define PKT3_SET_PREDICATION                   0x20
+#define PKT3_REG_RMW                           0x21
+#define PKT3_COND_EXEC                         0x22
+#define PKT3_PRED_EXEC                         0x23
+#define PKT3_START_3D_CMDBUF                   0x24
+#define PKT3_DRAW_INDEX_2                      0x27
+#define PKT3_CONTEXT_CONTROL                   0x28
+#define PKT3_DRAW_INDEX_IMMD_BE                0x29
+#define PKT3_INDEX_TYPE                        0x2A
+#define PKT3_DRAW_INDEX                        0x2B
+#define PKT3_DRAW_INDEX_AUTO                   0x2D
+#define PKT3_DRAW_INDEX_IMMD                   0x2E
+#define PKT3_NUM_INSTANCES                     0x2F
+#define PKT3_STRMOUT_BUFFER_UPDATE             0x34
+#define PKT3_INDIRECT_BUFFER_MP                0x38
+#define PKT3_MEM_SEMAPHORE                     0x39
+#define PKT3_MPEG_INDEX                        0x3A
+#define PKT3_WAIT_REG_MEM                      0x3C
+#define PKT3_MEM_WRITE                         0x3D
+#define PKT3_INDIRECT_BUFFER                   0x32
+#define PKT3_CP_INTERRUPT                      0x40
+#define PKT3_SURFACE_SYNC                      0x43
+#define PKT3_ME_INITIALIZE                     0x44
+#define PKT3_COND_WRITE                        0x45
+#define PKT3_EVENT_WRITE                       0x46
+#define PKT3_EVENT_WRITE_EOP                   0x47
+#define PKT3_ONE_REG_WRITE                     0x57
+#define PKT3_SET_CONFIG_REG                    0x68
+#define PKT3_SET_CONTEXT_REG                   0x69
+#define PKT3_SET_ALU_CONST                     0x6A
+#define PKT3_SET_BOOL_CONST                    0x6B
+#define PKT3_SET_LOOP_CONST                    0x6C
+#define PKT3_SET_RESOURCE                      0x6D
+#define PKT3_SET_SAMPLER                       0x6E
+#define PKT3_SET_CTL_CONST                     0x6F
+#define PKT3_SURFACE_BASE_UPDATE               0x73
+
+#define EVENT_TYPE_ZPASS_DONE                  0x15
+#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT   0x16
+
+#define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
+#define PKT_TYPE_G(x)                   (((x) >> 30) & 0x3)
+#define PKT_TYPE_C                      0x3FFFFFFF
+#define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
+#define PKT_COUNT_G(x)                  (((x) >> 16) & 0x3FFF)
+#define PKT_COUNT_C                     0xC000FFFF
+#define PKT0_BASE_INDEX_S(x)            (((x) & 0xFFFF) << 0)
+#define PKT0_BASE_INDEX_G(x)            (((x) >> 0) & 0xFFFF)
+#define PKT0_BASE_INDEX_C               0xFFFF0000
+#define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
+#define PKT3_IT_OPCODE_G(x)             (((x) >> 8) & 0xFF)
+#define PKT3_IT_OPCODE_C                0xFFFF00FF
+#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
+#define PKT3(op, count) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count))
+
+/* Registers */
+#define R_0280A0_CB_COLOR0_INFO                      0x0280A0
+#define   S_0280A0_ENDIAN(x)                           (((x) & 0x3) << 0)
+#define   G_0280A0_ENDIAN(x)                           (((x) >> 0) & 0x3)
+#define   C_0280A0_ENDIAN                              0xFFFFFFFC
+#define   S_0280A0_FORMAT(x)                           (((x) & 0x3F) << 2)
+#define   G_0280A0_FORMAT(x)                           (((x) >> 2) & 0x3F)
+#define   C_0280A0_FORMAT                              0xFFFFFF03
+#define     V_0280A0_COLOR_INVALID                     0x00000000
+#define     V_0280A0_COLOR_8                           0x00000001
+#define     V_0280A0_COLOR_4_4                         0x00000002
+#define     V_0280A0_COLOR_3_3_2                       0x00000003
+#define     V_0280A0_COLOR_16                          0x00000005
+#define     V_0280A0_COLOR_16_FLOAT                    0x00000006
+#define     V_0280A0_COLOR_8_8                         0x00000007
+#define     V_0280A0_COLOR_5_6_5                       0x00000008
+#define     V_0280A0_COLOR_6_5_5                       0x00000009
+#define     V_0280A0_COLOR_1_5_5_5                     0x0000000A
+#define     V_0280A0_COLOR_4_4_4_4                     0x0000000B
+#define     V_0280A0_COLOR_5_5_5_1                     0x0000000C
+#define     V_0280A0_COLOR_32                          0x0000000D
+#define     V_0280A0_COLOR_32_FLOAT                    0x0000000E
+#define     V_0280A0_COLOR_16_16                       0x0000000F
+#define     V_0280A0_COLOR_16_16_FLOAT                 0x00000010
+#define     V_0280A0_COLOR_8_24                        0x00000011
+#define     V_0280A0_COLOR_8_24_FLOAT                  0x00000012
+#define     V_0280A0_COLOR_24_8                        0x00000013
+#define     V_0280A0_COLOR_24_8_FLOAT                  0x00000014
+#define     V_0280A0_COLOR_10_11_11                    0x00000015
+#define     V_0280A0_COLOR_10_11_11_FLOAT              0x00000016
+#define     V_0280A0_COLOR_11_11_10                    0x00000017
+#define     V_0280A0_COLOR_11_11_10_FLOAT              0x00000018
+#define     V_0280A0_COLOR_2_10_10_10                  0x00000019
+#define     V_0280A0_COLOR_8_8_8_8                     0x0000001A
+#define     V_0280A0_COLOR_10_10_10_2                  0x0000001B
+#define     V_0280A0_COLOR_X24_8_32_FLOAT              0x0000001C
+#define     V_0280A0_COLOR_32_32                       0x0000001D
+#define     V_0280A0_COLOR_32_32_FLOAT                 0x0000001E
+#define     V_0280A0_COLOR_16_16_16_16                 0x0000001F
+#define     V_0280A0_COLOR_16_16_16_16_FLOAT           0x00000020
+#define     V_0280A0_COLOR_32_32_32_32                 0x00000022
+#define     V_0280A0_COLOR_32_32_32_32_FLOAT           0x00000023
+#define   S_0280A0_ARRAY_MODE(x)                       (((x) & 0xF) << 8)
+#define   G_0280A0_ARRAY_MODE(x)                       (((x) >> 8) & 0xF)
+#define   C_0280A0_ARRAY_MODE                          0xFFFFF0FF
+#define     V_0280A0_ARRAY_LINEAR_GENERAL              0x00000000
+#define     V_0280A0_ARRAY_LINEAR_ALIGNED              0x00000001
+#define     V_0280A0_ARRAY_1D_TILED_THIN1              0x00000002
+#define     V_0280A0_ARRAY_2D_TILED_THIN1              0x00000004
+#define   S_0280A0_NUMBER_TYPE(x)                      (((x) & 0x7) << 12)
+#define   G_0280A0_NUMBER_TYPE(x)                      (((x) >> 12) & 0x7)
+#define   C_0280A0_NUMBER_TYPE                         0xFFFF8FFF
+#define   S_0280A0_READ_SIZE(x)                        (((x) & 0x1) << 15)
+#define   G_0280A0_READ_SIZE(x)                        (((x) >> 15) & 0x1)
+#define   C_0280A0_READ_SIZE                           0xFFFF7FFF
+#define   S_0280A0_COMP_SWAP(x)                        (((x) & 0x3) << 16)
+#define   G_0280A0_COMP_SWAP(x)                        (((x) >> 16) & 0x3)
+#define   C_0280A0_COMP_SWAP                           0xFFFCFFFF
+#define   S_0280A0_TILE_MODE(x)                        (((x) & 0x3) << 18)
+#define   G_0280A0_TILE_MODE(x)                        (((x) >> 18) & 0x3)
+#define   C_0280A0_TILE_MODE                           0xFFF3FFFF
+#define   S_0280A0_BLEND_CLAMP(x)                      (((x) & 0x1) << 20)
+#define   G_0280A0_BLEND_CLAMP(x)                      (((x) >> 20) & 0x1)
+#define   C_0280A0_BLEND_CLAMP                         0xFFEFFFFF
+#define   S_0280A0_CLEAR_COLOR(x)                      (((x) & 0x1) << 21)
+#define   G_0280A0_CLEAR_COLOR(x)                      (((x) >> 21) & 0x1)
+#define   C_0280A0_CLEAR_COLOR                         0xFFDFFFFF
+#define   S_0280A0_BLEND_BYPASS(x)                     (((x) & 0x1) << 22)
+#define   G_0280A0_BLEND_BYPASS(x)                     (((x) >> 22) & 0x1)
+#define   C_0280A0_BLEND_BYPASS                        0xFFBFFFFF
+#define   S_0280A0_BLEND_FLOAT32(x)                    (((x) & 0x1) << 23)
+#define   G_0280A0_BLEND_FLOAT32(x)                    (((x) >> 23) & 0x1)
+#define   C_0280A0_BLEND_FLOAT32                       0xFF7FFFFF
+#define   S_0280A0_SIMPLE_FLOAT(x)                     (((x) & 0x1) << 24)
+#define   G_0280A0_SIMPLE_FLOAT(x)                     (((x) >> 24) & 0x1)
+#define   C_0280A0_SIMPLE_FLOAT                        0xFEFFFFFF
+#define   S_0280A0_ROUND_MODE(x)                       (((x) & 0x1) << 25)
+#define   G_0280A0_ROUND_MODE(x)                       (((x) >> 25) & 0x1)
+#define   C_0280A0_ROUND_MODE                          0xFDFFFFFF
+#define   S_0280A0_TILE_COMPACT(x)                     (((x) & 0x1) << 26)
+#define   G_0280A0_TILE_COMPACT(x)                     (((x) >> 26) & 0x1)
+#define   C_0280A0_TILE_COMPACT                        0xFBFFFFFF
+#define   S_0280A0_SOURCE_FORMAT(x)                    (((x) & 0x1) << 27)
+#define   G_0280A0_SOURCE_FORMAT(x)                    (((x) >> 27) & 0x1)
+#define   C_0280A0_SOURCE_FORMAT                       0xF7FFFFFF
+#define R_028060_CB_COLOR0_SIZE                      0x028060
+#define   S_028060_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
+#define   G_028060_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
+#define   C_028060_PITCH_TILE_MAX                      0xFFFFFC00
+#define   S_028060_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
+#define   G_028060_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
+#define   C_028060_SLICE_TILE_MAX                      0xC00003FF
+#define R_028800_DB_DEPTH_CONTROL                    0x028800
+#define   S_028800_STENCIL_ENABLE(x)                   (((x) & 0x1) << 0)
+#define   G_028800_STENCIL_ENABLE(x)                   (((x) >> 0) & 0x1)
+#define   C_028800_STENCIL_ENABLE                      0xFFFFFFFE
+#define   S_028800_Z_ENABLE(x)                         (((x) & 0x1) << 1)
+#define   G_028800_Z_ENABLE(x)                         (((x) >> 1) & 0x1)
+#define   C_028800_Z_ENABLE                            0xFFFFFFFD
+#define   S_028800_Z_WRITE_ENABLE(x)                   (((x) & 0x1) << 2)
+#define   G_028800_Z_WRITE_ENABLE(x)                   (((x) >> 2) & 0x1)
+#define   C_028800_Z_WRITE_ENABLE                      0xFFFFFFFB
+#define   S_028800_ZFUNC(x)                            (((x) & 0x7) << 4)
+#define   G_028800_ZFUNC(x)                            (((x) >> 4) & 0x7)
+#define   C_028800_ZFUNC                               0xFFFFFF8F
+#define   S_028800_BACKFACE_ENABLE(x)                  (((x) & 0x1) << 7)
+#define   G_028800_BACKFACE_ENABLE(x)                  (((x) >> 7) & 0x1)
+#define   C_028800_BACKFACE_ENABLE                     0xFFFFFF7F
+#define   S_028800_STENCILFUNC(x)                      (((x) & 0x7) << 8)
+#define   G_028800_STENCILFUNC(x)                      (((x) >> 8) & 0x7)
+#define   C_028800_STENCILFUNC                         0xFFFFF8FF
+#define   S_028800_STENCILFAIL(x)                      (((x) & 0x7) << 11)
+#define   G_028800_STENCILFAIL(x)                      (((x) >> 11) & 0x7)
+#define   C_028800_STENCILFAIL                         0xFFFFC7FF
+#define   S_028800_STENCILZPASS(x)                     (((x) & 0x7) << 14)
+#define   G_028800_STENCILZPASS(x)                     (((x) >> 14) & 0x7)
+#define   C_028800_STENCILZPASS                        0xFFFE3FFF
+#define   S_028800_STENCILZFAIL(x)                     (((x) & 0x7) << 17)
+#define   G_028800_STENCILZFAIL(x)                     (((x) >> 17) & 0x7)
+#define   C_028800_STENCILZFAIL                        0xFFF1FFFF
+#define   S_028800_STENCILFUNC_BF(x)                   (((x) & 0x7) << 20)
+#define   G_028800_STENCILFUNC_BF(x)                   (((x) >> 20) & 0x7)
+#define   C_028800_STENCILFUNC_BF                      0xFF8FFFFF
+#define   S_028800_STENCILFAIL_BF(x)                   (((x) & 0x7) << 23)
+#define   G_028800_STENCILFAIL_BF(x)                   (((x) >> 23) & 0x7)
+#define   C_028800_STENCILFAIL_BF                      0xFC7FFFFF
+#define   S_028800_STENCILZPASS_BF(x)                  (((x) & 0x7) << 26)
+#define   G_028800_STENCILZPASS_BF(x)                  (((x) >> 26) & 0x7)
+#define   C_028800_STENCILZPASS_BF                     0xE3FFFFFF
+#define   S_028800_STENCILZFAIL_BF(x)                  (((x) & 0x7) << 29)
+#define   G_028800_STENCILZFAIL_BF(x)                  (((x) >> 29) & 0x7)
+#define   C_028800_STENCILZFAIL_BF                     0x1FFFFFFF
+#define R_028010_DB_DEPTH_INFO                       0x028010
+#define   S_028010_FORMAT(x)                           (((x) & 0x7) << 0)
+#define   G_028010_FORMAT(x)                           (((x) >> 0) & 0x7)
+#define   C_028010_FORMAT                              0xFFFFFFF8
+#define     V_028010_DEPTH_INVALID                     0x00000000
+#define     V_028010_DEPTH_16                          0x00000001
+#define     V_028010_DEPTH_X8_24                       0x00000002
+#define     V_028010_DEPTH_8_24                        0x00000003
+#define     V_028010_DEPTH_X8_24_FLOAT                 0x00000004
+#define     V_028010_DEPTH_8_24_FLOAT                  0x00000005
+#define     V_028010_DEPTH_32_FLOAT                    0x00000006
+#define     V_028010_DEPTH_X24_8_32_FLOAT              0x00000007
+#define   S_028010_READ_SIZE(x)                        (((x) & 0x1) << 3)
+#define   G_028010_READ_SIZE(x)                        (((x) >> 3) & 0x1)
+#define   C_028010_READ_SIZE                           0xFFFFFFF7
+#define   S_028010_ARRAY_MODE(x)                       (((x) & 0xF) << 15)
+#define   G_028010_ARRAY_MODE(x)                       (((x) >> 15) & 0xF)
+#define   C_028010_ARRAY_MODE                          0xFFF87FFF
+#define   S_028010_TILE_SURFACE_ENABLE(x)              (((x) & 0x1) << 25)
+#define   G_028010_TILE_SURFACE_ENABLE(x)              (((x) >> 25) & 0x1)
+#define   C_028010_TILE_SURFACE_ENABLE                 0xFDFFFFFF
+#define   S_028010_TILE_COMPACT(x)                     (((x) & 0x1) << 26)
+#define   G_028010_TILE_COMPACT(x)                     (((x) >> 26) & 0x1)
+#define   C_028010_TILE_COMPACT                        0xFBFFFFFF
+#define   S_028010_ZRANGE_PRECISION(x)                 (((x) & 0x1) << 31)
+#define   G_028010_ZRANGE_PRECISION(x)                 (((x) >> 31) & 0x1)
+#define   C_028010_ZRANGE_PRECISION                    0x7FFFFFFF
+#define R_028000_DB_DEPTH_SIZE                       0x028000
+#define   S_028000_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
+#define   G_028000_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
+#define   C_028000_PITCH_TILE_MAX                      0xFFFFFC00
+#define   S_028000_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
+#define   G_028000_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
+#define   C_028000_SLICE_TILE_MAX                      0xC00003FF
+#define R_028004_DB_DEPTH_VIEW                       0x028004
+#define   S_028004_SLICE_START(x)                      (((x) & 0x7FF) << 0)
+#define   G_028004_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
+#define   C_028004_SLICE_START                         0xFFFFF800
+#define   S_028004_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
+#define   G_028004_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
+#define   C_028004_SLICE_MAX                           0xFF001FFF
+#define R_028D24_DB_HTILE_SURFACE                    0x028D24
+#define   S_028D24_HTILE_WIDTH(x)                      (((x) & 0x1) << 0)
+#define   G_028D24_HTILE_WIDTH(x)                      (((x) >> 0) & 0x1)
+#define   C_028D24_HTILE_WIDTH                         0xFFFFFFFE
+#define   S_028D24_HTILE_HEIGHT(x)                     (((x) & 0x1) << 1)
+#define   G_028D24_HTILE_HEIGHT(x)                     (((x) >> 1) & 0x1)
+#define   C_028D24_HTILE_HEIGHT                        0xFFFFFFFD
+#define   S_028D24_LINEAR(x)                           (((x) & 0x1) << 2)
+#define   G_028D24_LINEAR(x)                           (((x) >> 2) & 0x1)
+#define   C_028D24_LINEAR                              0xFFFFFFFB
+#define   S_028D24_FULL_CACHE(x)                       (((x) & 0x1) << 3)
+#define   G_028D24_FULL_CACHE(x)                       (((x) >> 3) & 0x1)
+#define   C_028D24_FULL_CACHE                          0xFFFFFFF7
+#define   S_028D24_HTILE_USES_PRELOAD_WIN(x)           (((x) & 0x1) << 4)
+#define   G_028D24_HTILE_USES_PRELOAD_WIN(x)           (((x) >> 4) & 0x1)
+#define   C_028D24_HTILE_USES_PRELOAD_WIN              0xFFFFFFEF
+#define   S_028D24_PRELOAD(x)                          (((x) & 0x1) << 5)
+#define   G_028D24_PRELOAD(x)                          (((x) >> 5) & 0x1)
+#define   C_028D24_PRELOAD                             0xFFFFFFDF
+#define   S_028D24_PREFETCH_WIDTH(x)                   (((x) & 0x3F) << 6)
+#define   G_028D24_PREFETCH_WIDTH(x)                   (((x) >> 6) & 0x3F)
+#define   C_028D24_PREFETCH_WIDTH                      0xFFFFF03F
+#define   S_028D24_PREFETCH_HEIGHT(x)                  (((x) & 0x3F) << 12)
+#define   G_028D24_PREFETCH_HEIGHT(x)                  (((x) >> 12) & 0x3F)
+#define   C_028D24_PREFETCH_HEIGHT                     0xFFFC0FFF
+#define R_028D34_DB_PREFETCH_LIMIT                   0x028D34
+#define   S_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) & 0x3FF) << 0)
+#define   G_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) >> 0) & 0x3FF)
+#define   C_028D34_DEPTH_HEIGHT_TILE_MAX               0xFFFFFC00
+#define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
+#define   S_028D10_FORCE_HIZ_ENABLE(x)                 (((x) & 0x3) << 0)
+#define   G_028D10_FORCE_HIZ_ENABLE(x)                 (((x) >> 0) & 0x3)
+#define   C_028D10_FORCE_HIZ_ENABLE                    0xFFFFFFFC
+#define   S_028D10_FORCE_HIS_ENABLE0(x)                (((x) & 0x3) << 2)
+#define   G_028D10_FORCE_HIS_ENABLE0(x)                (((x) >> 2) & 0x3)
+#define   C_028D10_FORCE_HIS_ENABLE0                   0xFFFFFFF3
+#define   S_028D10_FORCE_HIS_ENABLE1(x)                (((x) & 0x3) << 4)
+#define   G_028D10_FORCE_HIS_ENABLE1(x)                (((x) >> 4) & 0x3)
+#define   C_028D10_FORCE_HIS_ENABLE1                   0xFFFFFFCF
+#define   S_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) & 0x1) << 6)
+#define   G_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) >> 6) & 0x1)
+#define   C_028D10_FORCE_SHADER_Z_ORDER                0xFFFFFFBF
+#define   S_028D10_FAST_Z_DISABLE(x)                   (((x) & 0x1) << 7)
+#define   G_028D10_FAST_Z_DISABLE(x)                   (((x) >> 7) & 0x1)
+#define   C_028D10_FAST_Z_DISABLE                      0xFFFFFF7F
+#define   S_028D10_FAST_STENCIL_DISABLE(x)             (((x) & 0x1) << 8)
+#define   G_028D10_FAST_STENCIL_DISABLE(x)             (((x) >> 8) & 0x1)
+#define   C_028D10_FAST_STENCIL_DISABLE                0xFFFFFEFF
+#define   S_028D10_NOOP_CULL_DISABLE(x)                (((x) & 0x1) << 9)
+#define   G_028D10_NOOP_CULL_DISABLE(x)                (((x) >> 9) & 0x1)
+#define   C_028D10_NOOP_CULL_DISABLE                   0xFFFFFDFF
+#define   S_028D10_FORCE_COLOR_KILL(x)                 (((x) & 0x1) << 10)
+#define   G_028D10_FORCE_COLOR_KILL(x)                 (((x) >> 10) & 0x1)
+#define   C_028D10_FORCE_COLOR_KILL                    0xFFFFFBFF
+#define   S_028D10_FORCE_Z_READ(x)                     (((x) & 0x1) << 11)
+#define   G_028D10_FORCE_Z_READ(x)                     (((x) >> 11) & 0x1)
+#define   C_028D10_FORCE_Z_READ                        0xFFFFF7FF
+#define   S_028D10_FORCE_STENCIL_READ(x)               (((x) & 0x1) << 12)
+#define   G_028D10_FORCE_STENCIL_READ(x)               (((x) >> 12) & 0x1)
+#define   C_028D10_FORCE_STENCIL_READ                  0xFFFFEFFF
+#define   S_028D10_FORCE_FULL_Z_RANGE(x)               (((x) & 0x3) << 13)
+#define   G_028D10_FORCE_FULL_Z_RANGE(x)               (((x) >> 13) & 0x3)
+#define   C_028D10_FORCE_FULL_Z_RANGE                  0xFFFF9FFF
+#define   S_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) & 0x1) << 15)
+#define   G_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) >> 15) & 0x1)
+#define   C_028D10_FORCE_QC_SMASK_CONFLICT             0xFFFF7FFF
+#define   S_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) & 0x1) << 16)
+#define   G_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) >> 16) & 0x1)
+#define   C_028D10_DISABLE_VIEWPORT_CLAMP              0xFFFEFFFF
+#define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
+#define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
+#define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_028A40_VGT_GS_MODE                         0x028A40
+#define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
+#define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
+#define   C_028A40_MODE                                0xFFFFFFFC
+#define   S_028A40_ES_PASSTHRU(x)                      (((x) & 0x1) << 2)
+#define   G_028A40_ES_PASSTHRU(x)                      (((x) >> 2) & 0x1)
+#define   C_028A40_ES_PASSTHRU                         0xFFFFFFFB
+#define   S_028A40_CUT_MODE(x)                         (((x) & 0x3) << 3)
+#define   G_028A40_CUT_MODE(x)                         (((x) >> 3) & 0x3)
+#define   C_028A40_CUT_MODE                            0xFFFFFFE7
+#define R_008DFC_SQ_CF_WORD0                         0x008DFC
+#define   S_008DFC_ADDR(x)                             (((x) & 0xFFFFFFFF) << 0)
+#define   G_008DFC_ADDR(x)                             (((x) >> 0) & 0xFFFFFFFF)
+#define   C_008DFC_ADDR                                0x00000000
+#define R_008DFC_SQ_CF_WORD1                         0x008DFC
+#define   S_008DFC_POP_COUNT(x)                        (((x) & 0x7) << 0)
+#define   G_008DFC_POP_COUNT(x)                        (((x) >> 0) & 0x7)
+#define   C_008DFC_POP_COUNT                           0xFFFFFFF8
+#define   S_008DFC_CF_CONST(x)                         (((x) & 0x1F) << 3)
+#define   G_008DFC_CF_CONST(x)                         (((x) >> 3) & 0x1F)
+#define   C_008DFC_CF_CONST                            0xFFFFFF07
+#define   S_008DFC_COND(x)                             (((x) & 0x3) << 8)
+#define   G_008DFC_COND(x)                             (((x) >> 8) & 0x3)
+#define   C_008DFC_COND                                0xFFFFFCFF
+#define   S_008DFC_COUNT(x)                            (((x) & 0x7) << 10)
+#define   G_008DFC_COUNT(x)                            (((x) >> 10) & 0x7)
+#define   C_008DFC_COUNT                               0xFFFFE3FF
+#define   S_008DFC_CALL_COUNT(x)                       (((x) & 0x3F) << 13)
+#define   G_008DFC_CALL_COUNT(x)                       (((x) >> 13) & 0x3F)
+#define   C_008DFC_CALL_COUNT                          0xFFF81FFF
+#define   S_008DFC_END_OF_PROGRAM(x)                   (((x) & 0x1) << 21)
+#define   G_008DFC_END_OF_PROGRAM(x)                   (((x) >> 21) & 0x1)
+#define   C_008DFC_END_OF_PROGRAM                      0xFFDFFFFF
+#define   S_008DFC_VALID_PIXEL_MODE(x)                 (((x) & 0x1) << 22)
+#define   G_008DFC_VALID_PIXEL_MODE(x)                 (((x) >> 22) & 0x1)
+#define   C_008DFC_VALID_PIXEL_MODE                    0xFFBFFFFF
+#define   S_008DFC_CF_INST(x)                          (((x) & 0x7F) << 23)
+#define   G_008DFC_CF_INST(x)                          (((x) >> 23) & 0x7F)
+#define   C_008DFC_CF_INST                             0xC07FFFFF
+#define     V_008DFC_SQ_CF_INST_NOP                    0x00000000
+#define     V_008DFC_SQ_CF_INST_TEX                    0x00000001
+#define     V_008DFC_SQ_CF_INST_VTX                    0x00000002
+#define     V_008DFC_SQ_CF_INST_VTX_TC                 0x00000003
+#define     V_008DFC_SQ_CF_INST_LOOP_START             0x00000004
+#define     V_008DFC_SQ_CF_INST_LOOP_END               0x00000005
+#define     V_008DFC_SQ_CF_INST_LOOP_START_DX10        0x00000006
+#define     V_008DFC_SQ_CF_INST_LOOP_START_NO_AL       0x00000007
+#define     V_008DFC_SQ_CF_INST_LOOP_CONTINUE          0x00000008
+#define     V_008DFC_SQ_CF_INST_LOOP_BREAK             0x00000009
+#define     V_008DFC_SQ_CF_INST_JUMP                   0x0000000A
+#define     V_008DFC_SQ_CF_INST_PUSH                   0x0000000B
+#define     V_008DFC_SQ_CF_INST_PUSH_ELSE              0x0000000C
+#define     V_008DFC_SQ_CF_INST_ELSE                   0x0000000D
+#define     V_008DFC_SQ_CF_INST_POP                    0x0000000E
+#define     V_008DFC_SQ_CF_INST_POP_JUMP               0x0000000F
+#define     V_008DFC_SQ_CF_INST_POP_PUSH               0x00000010
+#define     V_008DFC_SQ_CF_INST_POP_PUSH_ELSE          0x00000011
+#define     V_008DFC_SQ_CF_INST_CALL                   0x00000012
+#define     V_008DFC_SQ_CF_INST_CALL_FS                0x00000013
+#define     V_008DFC_SQ_CF_INST_RETURN                 0x00000014
+#define     V_008DFC_SQ_CF_INST_EMIT_VERTEX            0x00000015
+#define     V_008DFC_SQ_CF_INST_EMIT_CUT_VERTEX        0x00000016
+#define     V_008DFC_SQ_CF_INST_CUT_VERTEX             0x00000017
+#define     V_008DFC_SQ_CF_INST_KILL                   0x00000018
+#define   S_008DFC_WHOLE_QUAD_MODE(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_WHOLE_QUAD_MODE(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_WHOLE_QUAD_MODE                     0xBFFFFFFF
+#define   S_008DFC_BARRIER(x)                          (((x) & 0x1) << 31)
+#define   G_008DFC_BARRIER(x)                          (((x) >> 31) & 0x1)
+#define   C_008DFC_BARRIER                             0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALU_WORD0                     0x008DFC
+#define   S_008DFC_ALU_ADDR(x)                         (((x) & 0x3FFFFF) << 0)
+#define   G_008DFC_ALU_ADDR(x)                         (((x) >> 0) & 0x3FFFFF)
+#define   C_008DFC_ALU_ADDR                            0xFFC00000
+#define   S_008DFC_KCACHE_BANK0(x)                     (((x) & 0xF) << 22)
+#define   G_008DFC_KCACHE_BANK0(x)                     (((x) >> 22) & 0xF)
+#define   C_008DFC_KCACHE_BANK0                        0xFC3FFFFF
+#define   S_008DFC_KCACHE_BANK1(x)                     (((x) & 0xF) << 26)
+#define   G_008DFC_KCACHE_BANK1(x)                     (((x) >> 26) & 0xF)
+#define   C_008DFC_KCACHE_BANK1                        0xC3FFFFFF
+#define   S_008DFC_KCACHE_MODE0(x)                     (((x) & 0x3) << 30)
+#define   G_008DFC_KCACHE_MODE0(x)                     (((x) >> 30) & 0x3)
+#define   C_008DFC_KCACHE_MODE0                        0x3FFFFFFF
+#define R_008DFC_SQ_CF_ALU_WORD1                     0x008DFC
+#define   S_008DFC_KCACHE_MODE1(x)                     (((x) & 0x3) << 0)
+#define   G_008DFC_KCACHE_MODE1(x)                     (((x) >> 0) & 0x3)
+#define   C_008DFC_KCACHE_MODE1                        0xFFFFFFFC
+#define   S_008DFC_KCACHE_ADDR0(x)                     (((x) & 0xFF) << 2)
+#define   G_008DFC_KCACHE_ADDR0(x)                     (((x) >> 2) & 0xFF)
+#define   C_008DFC_KCACHE_ADDR0                        0xFFFFFC03
+#define   S_008DFC_KCACHE_ADDR1(x)                     (((x) & 0xFF) << 10)
+#define   G_008DFC_KCACHE_ADDR1(x)                     (((x) >> 10) & 0xFF)
+#define   C_008DFC_KCACHE_ADDR1                        0xFFFC03FF
+#define   S_008DFC_ALU_COUNT(x)                        (((x) & 0x7F) << 18)
+#define   G_008DFC_ALU_COUNT(x)                        (((x) >> 18) & 0x7F)
+#define   C_008DFC_ALU_COUNT                           0xFE03FFFF
+#define   S_008DFC_USES_WATERFALL(x)                   (((x) & 0x1) << 25)
+#define   G_008DFC_USES_WATERFALL(x)                   (((x) >> 25) & 0x1)
+#define   C_008DFC_USES_WATERFALL                      0xFDFFFFFF
+#define   S_008DFC_CF_ALU_INST(x)                      (((x) & 0xF) << 26)
+#define   G_008DFC_CF_ALU_INST(x)                      (((x) >> 26) & 0xF)
+#define   C_008DFC_CF_ALU_INST                         0xC3FFFFFF
+#define     V_008DFC_SQ_CF_INST_ALU                    0x00000008
+#define     V_008DFC_SQ_CF_INST_ALU_PUSH_BEFORE        0x00000009
+#define     V_008DFC_SQ_CF_INST_ALU_POP_AFTER          0x0000000A
+#define     V_008DFC_SQ_CF_INST_ALU_POP2_AFTER         0x0000000B
+#define     V_008DFC_SQ_CF_INST_ALU_CONTINUE           0x0000000D
+#define     V_008DFC_SQ_CF_INST_ALU_BREAK              0x0000000E
+#define     V_008DFC_SQ_CF_INST_ALU_ELSE_AFTER         0x0000000F
+#define   S_008DFC_WHOLE_QUAD_MODE(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_WHOLE_QUAD_MODE(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_WHOLE_QUAD_MODE                     0xBFFFFFFF
+#define   S_008DFC_BARRIER(x)                          (((x) & 0x1) << 31)
+#define   G_008DFC_BARRIER(x)                          (((x) >> 31) & 0x1)
+#define   C_008DFC_BARRIER                             0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD0            0x008DFC
+#define   S_008DFC_ARRAY_BASE(x)                       (((x) & 0x1FFF) << 0)
+#define   G_008DFC_ARRAY_BASE(x)                       (((x) >> 0) & 0x1FFF)
+#define   C_008DFC_ARRAY_BASE                          0xFFFFE000
+#define   S_008DFC_TYPE(x)                             (((x) & 0x3) << 13)
+#define   G_008DFC_TYPE(x)                             (((x) >> 13) & 0x3)
+#define   C_008DFC_TYPE                                0xFFFF9FFF
+#define   S_008DFC_RW_GPR(x)                           (((x) & 0x7F) << 15)
+#define   G_008DFC_RW_GPR(x)                           (((x) >> 15) & 0x7F)
+#define   C_008DFC_RW_GPR                              0xFFC07FFF
+#define   S_008DFC_RW_REL(x)                           (((x) & 0x1) << 22)
+#define   G_008DFC_RW_REL(x)                           (((x) >> 22) & 0x1)
+#define   C_008DFC_RW_REL                              0xFFBFFFFF
+#define   S_008DFC_INDEX_GPR(x)                        (((x) & 0x7F) << 23)
+#define   G_008DFC_INDEX_GPR(x)                        (((x) >> 23) & 0x7F)
+#define   C_008DFC_INDEX_GPR                           0xC07FFFFF
+#define   S_008DFC_ELEM_SIZE(x)                        (((x) & 0x3) << 30)
+#define   G_008DFC_ELEM_SIZE(x)                        (((x) >> 30) & 0x3)
+#define   C_008DFC_ELEM_SIZE                           0x3FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1            0x008DFC
+#define   S_008DFC_BURST_COUNT(x)                      (((x) & 0xF) << 17)
+#define   G_008DFC_BURST_COUNT(x)                      (((x) >> 17) & 0xF)
+#define   C_008DFC_BURST_COUNT                         0xFFE1FFFF
+#define   S_008DFC_END_OF_PROGRAM(x)                   (((x) & 0x1) << 21)
+#define   G_008DFC_END_OF_PROGRAM(x)                   (((x) >> 21) & 0x1)
+#define   C_008DFC_END_OF_PROGRAM                      0xFFDFFFFF
+#define   S_008DFC_VALID_PIXEL_MODE(x)                 (((x) & 0x1) << 22)
+#define   G_008DFC_VALID_PIXEL_MODE(x)                 (((x) >> 22) & 0x1)
+#define   C_008DFC_VALID_PIXEL_MODE                    0xFFBFFFFF
+#define   S_008DFC_CF_INST(x)                          (((x) & 0x7F) << 23)
+#define   G_008DFC_CF_INST(x)                          (((x) >> 23) & 0x7F)
+#define   C_008DFC_CF_INST                             0xC07FFFFF
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM0            0x00000020
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM1            0x00000021
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM2            0x00000022
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM3            0x00000023
+#define     V_008DFC_SQ_CF_INST_MEM_SCRATCH            0x00000024
+#define     V_008DFC_SQ_CF_INST_MEM_REDUCTION          0x00000025
+#define     V_008DFC_SQ_CF_INST_MEM_RING               0x00000026
+#define     V_008DFC_SQ_CF_INST_EXPORT                 0x00000027
+#define     V_008DFC_SQ_CF_INST_EXPORT_DONE            0x00000028
+#define   S_008DFC_WHOLE_QUAD_MODE(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_WHOLE_QUAD_MODE(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_WHOLE_QUAD_MODE                     0xBFFFFFFF
+#define   S_008DFC_BARRIER(x)                          (((x) & 0x1) << 31)
+#define   G_008DFC_BARRIER(x)                          (((x) >> 31) & 0x1)
+#define   C_008DFC_BARRIER                             0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_BUF        0x008DFC
+#define   S_008DFC_ARRAY_SIZE(x)                       (((x) & 0xFFF) << 0)
+#define   G_008DFC_ARRAY_SIZE(x)                       (((x) >> 0) & 0xFFF)
+#define   C_008DFC_ARRAY_SIZE                          0xFFFFF000
+#define   S_008DFC_COMP_MASK(x)                        (((x) & 0xF) << 12)
+#define   G_008DFC_COMP_MASK(x)                        (((x) >> 12) & 0xF)
+#define   C_008DFC_COMP_MASK                           0xFFFF0FFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ       0x008DFC
+#define   S_008DFC_SEL_X(x)                            (((x) & 0x7) << 0)
+#define   G_008DFC_SEL_X(x)                            (((x) >> 0) & 0x7)
+#define   C_008DFC_SEL_X                               0xFFFFFFF8
+#define   S_008DFC_SEL_Y(x)                            (((x) & 0x7) << 3)
+#define   G_008DFC_SEL_Y(x)                            (((x) >> 3) & 0x7)
+#define   C_008DFC_SEL_Y                               0xFFFFFFC7
+#define   S_008DFC_SEL_Z(x)                            (((x) & 0x7) << 6)
+#define   G_008DFC_SEL_Z(x)                            (((x) >> 6) & 0x7)
+#define   C_008DFC_SEL_Z                               0xFFFFFE3F
+#define   S_008DFC_SEL_W(x)                            (((x) & 0x7) << 9)
+#define   G_008DFC_SEL_W(x)                            (((x) >> 9) & 0x7)
+#define   C_008DFC_SEL_W                               0xFFFFF1FF
+#define R_008DFC_SQ_VTX_WORD0                        0x008DFC
+#define   S_008DFC_VTX_INST(x)                         (((x) & 0x1F) << 0)
+#define   G_008DFC_VTX_INST(x)                         (((x) >> 0) & 0x1F)
+#define   C_008DFC_VTX_INST                            0xFFFFFFE0
+#define   S_008DFC_FETCH_TYPE(x)                       (((x) & 0x3) << 5)
+#define   G_008DFC_FETCH_TYPE(x)                       (((x) >> 5) & 0x3)
+#define   C_008DFC_FETCH_TYPE                          0xFFFFFF9F
+#define   S_008DFC_FETCH_WHOLE_QUAD(x)                 (((x) & 0x1) << 7)
+#define   G_008DFC_FETCH_WHOLE_QUAD(x)                 (((x) >> 7) & 0x1)
+#define   C_008DFC_FETCH_WHOLE_QUAD                    0xFFFFFF7F
+#define   S_008DFC_BUFFER_ID(x)                        (((x) & 0xFF) << 8)
+#define   G_008DFC_BUFFER_ID(x)                        (((x) >> 8) & 0xFF)
+#define   C_008DFC_BUFFER_ID                           0xFFFF00FF
+#define   S_008DFC_SRC_GPR(x)                          (((x) & 0x7F) << 16)
+#define   G_008DFC_SRC_GPR(x)                          (((x) >> 16) & 0x7F)
+#define   C_008DFC_SRC_GPR                             0xFF80FFFF
+#define   S_008DFC_SRC_REL(x)                          (((x) & 0x1) << 23)
+#define   G_008DFC_SRC_REL(x)                          (((x) >> 23) & 0x1)
+#define   C_008DFC_SRC_REL                             0xFF7FFFFF
+#define   S_008DFC_SRC_SEL_X(x)                        (((x) & 0x3) << 24)
+#define   G_008DFC_SRC_SEL_X(x)                        (((x) >> 24) & 0x3)
+#define   C_008DFC_SRC_SEL_X                           0xFCFFFFFF
+#define   S_008DFC_MEGA_FETCH_COUNT(x)                 (((x) & 0x3F) << 26)
+#define   G_008DFC_MEGA_FETCH_COUNT(x)                 (((x) >> 26) & 0x3F)
+#define   C_008DFC_MEGA_FETCH_COUNT                    0x03FFFFFF
+#define R_008DFC_SQ_VTX_WORD1                        0x008DFC
+#define   S_008DFC_DST_SEL_X(x)                        (((x) & 0x7) << 9)
+#define   G_008DFC_DST_SEL_X(x)                        (((x) >> 9) & 0x7)
+#define   C_008DFC_DST_SEL_X                           0xFFFFF1FF
+#define   S_008DFC_DST_SEL_Y(x)                        (((x) & 0x7) << 12)
+#define   G_008DFC_DST_SEL_Y(x)                        (((x) >> 12) & 0x7)
+#define   C_008DFC_DST_SEL_Y                           0xFFFF8FFF
+#define   S_008DFC_DST_SEL_Z(x)                        (((x) & 0x7) << 15)
+#define   G_008DFC_DST_SEL_Z(x)                        (((x) >> 15) & 0x7)
+#define   C_008DFC_DST_SEL_Z                           0xFFFC7FFF
+#define   S_008DFC_DST_SEL_W(x)                        (((x) & 0x7) << 18)
+#define   G_008DFC_DST_SEL_W(x)                        (((x) >> 18) & 0x7)
+#define   C_008DFC_DST_SEL_W                           0xFFE3FFFF
+#define   S_008DFC_USE_CONST_FIELDS(x)                 (((x) & 0x1) << 21)
+#define   G_008DFC_USE_CONST_FIELDS(x)                 (((x) >> 21) & 0x1)
+#define   C_008DFC_USE_CONST_FIELDS                    0xFFDFFFFF
+#define   S_008DFC_DATA_FORMAT(x)                      (((x) & 0x3F) << 22)
+#define   G_008DFC_DATA_FORMAT(x)                      (((x) >> 22) & 0x3F)
+#define   C_008DFC_DATA_FORMAT                         0xF03FFFFF
+#define   S_008DFC_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 28)
+#define   G_008DFC_NUM_FORMAT_ALL(x)                   (((x) >> 28) & 0x3)
+#define   C_008DFC_NUM_FORMAT_ALL                      0xCFFFFFFF
+#define   S_008DFC_FORMAT_COMP_ALL(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_FORMAT_COMP_ALL(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_FORMAT_COMP_ALL                     0xBFFFFFFF
+#define   S_008DFC_SRF_MODE_ALL(x)                     (((x) & 0x1) << 31)
+#define   G_008DFC_SRF_MODE_ALL(x)                     (((x) >> 31) & 0x1)
+#define   C_008DFC_SRF_MODE_ALL                        0x7FFFFFFF
+#define R_008DFC_SQ_VTX_WORD1_GPR                    0x008DFC
+#define   S_008DFC_DST_GPR(x)                          (((x) & 0x7F) << 0)
+#define   G_008DFC_DST_GPR(x)                          (((x) >> 0) & 0x7F)
+#define   C_008DFC_DST_GPR                             0xFFFFFF80
+#define   S_008DFC_DST_REL(x)                          (((x) & 0x1) << 7)
+#define   G_008DFC_DST_REL(x)                          (((x) >> 7) & 0x1)
+#define   C_008DFC_DST_REL                             0xFFFFFF7F
+#define R_008DFC_SQ_VTX_WORD2                        0x008DFC
+#define   S_008DFC_OFFSET(x)                           (((x) & 0xFFFF) << 0)
+#define   G_008DFC_OFFSET(x)                           (((x) >> 0) & 0xFFFF)
+#define   C_008DFC_OFFSET                              0xFFFF0000
+#define   S_008DFC_ENDIAN_SWAP(x)                      (((x) & 0x3) << 16)
+#define   G_008DFC_ENDIAN_SWAP(x)                      (((x) >> 16) & 0x3)
+#define   C_008DFC_ENDIAN_SWAP                         0xFFFCFFFF
+#define   S_008DFC_CONST_BUF_NO_STRIDE(x)              (((x) & 0x1) << 18)
+#define   G_008DFC_CONST_BUF_NO_STRIDE(x)              (((x) >> 18) & 0x1)
+#define   C_008DFC_CONST_BUF_NO_STRIDE                 0xFFFBFFFF
+#define   S_008DFC_MEGA_FETCH(x)                       (((x) & 0x1) << 19)
+#define   G_008DFC_MEGA_FETCH(x)                       (((x) >> 19) & 0x1)
+#define   C_008DFC_MEGA_FETCH                          0xFFF7FFFF
+#define   S_008DFC_ALT_CONST(x)                        (((x) & 0x1) << 20)
+#define   G_008DFC_ALT_CONST(x)                        (((x) >> 20) & 0x1)
+#define   C_008DFC_ALT_CONST                           0xFFEFFFFF
+#define R_008040_WAIT_UNTIL                          0x008040
+#define   S_008040_WAIT_CP_DMA_IDLE(x)                 (((x) & 0x1) << 8)
+#define   G_008040_WAIT_CP_DMA_IDLE(x)                 (((x) >> 8) & 0x1)
+#define   C_008040_WAIT_CP_DMA_IDLE                    0xFFFFFEFF
+#define   S_008040_WAIT_CMDFIFO(x)                     (((x) & 0x1) << 10)
+#define   G_008040_WAIT_CMDFIFO(x)                     (((x) >> 10) & 0x1)
+#define   C_008040_WAIT_CMDFIFO                        0xFFFFFBFF
+#define   S_008040_WAIT_2D_IDLE(x)                     (((x) & 0x1) << 14)
+#define   G_008040_WAIT_2D_IDLE(x)                     (((x) >> 14) & 0x1)
+#define   C_008040_WAIT_2D_IDLE                        0xFFFFBFFF
+#define   S_008040_WAIT_3D_IDLE(x)                     (((x) & 0x1) << 15)
+#define   G_008040_WAIT_3D_IDLE(x)                     (((x) >> 15) & 0x1)
+#define   C_008040_WAIT_3D_IDLE                        0xFFFF7FFF
+#define   S_008040_WAIT_2D_IDLECLEAN(x)                (((x) & 0x1) << 16)
+#define   G_008040_WAIT_2D_IDLECLEAN(x)                (((x) >> 16) & 0x1)
+#define   C_008040_WAIT_2D_IDLECLEAN                   0xFFFEFFFF
+#define   S_008040_WAIT_3D_IDLECLEAN(x)                (((x) & 0x1) << 17)
+#define   G_008040_WAIT_3D_IDLECLEAN(x)                (((x) >> 17) & 0x1)
+#define   C_008040_WAIT_3D_IDLECLEAN                   0xFFFDFFFF
+#define   S_008040_WAIT_EXTERN_SIG(x)                  (((x) & 0x1) << 19)
+#define   G_008040_WAIT_EXTERN_SIG(x)                  (((x) >> 19) & 0x1)
+#define   C_008040_WAIT_EXTERN_SIG                     0xFFF7FFFF
+#define   S_008040_CMDFIFO_ENTRIES(x)                  (((x) & 0x1F) << 20)
+#define   G_008040_CMDFIFO_ENTRIES(x)                  (((x) >> 20) & 0x1F)
+#define   C_008040_CMDFIFO_ENTRIES                     0xFE0FFFFF
+#define R_0286CC_SPI_PS_IN_CONTROL_0                 0x0286CC
+#define   S_0286CC_NUM_INTERP(x)                       (((x) & 0x3F) << 0)
+#define   G_0286CC_NUM_INTERP(x)                       (((x) >> 0) & 0x3F)
+#define   C_0286CC_NUM_INTERP                          0xFFFFFFC0
+#define   S_0286CC_POSITION_ENA(x)                     (((x) & 0x1) << 8)
+#define   G_0286CC_POSITION_ENA(x)                     (((x) >> 8) & 0x1)
+#define   C_0286CC_POSITION_ENA                        0xFFFFFEFF
+#define   S_0286CC_POSITION_CENTROID(x)                (((x) & 0x1) << 9)
+#define   G_0286CC_POSITION_CENTROID(x)                (((x) >> 9) & 0x1)
+#define   C_0286CC_POSITION_CENTROID                   0xFFFFFDFF
+#define   S_0286CC_POSITION_ADDR(x)                    (((x) & 0x1F) << 10)
+#define   G_0286CC_POSITION_ADDR(x)                    (((x) >> 10) & 0x1F)
+#define   C_0286CC_POSITION_ADDR                       0xFFFF83FF
+#define   S_0286CC_PARAM_GEN(x)                        (((x) & 0xF) << 15)
+#define   G_0286CC_PARAM_GEN(x)                        (((x) >> 15) & 0xF)
+#define   C_0286CC_PARAM_GEN                           0xFFF87FFF
+#define   S_0286CC_PARAM_GEN_ADDR(x)                   (((x) & 0x7F) << 19)
+#define   G_0286CC_PARAM_GEN_ADDR(x)                   (((x) >> 19) & 0x7F)
+#define   C_0286CC_PARAM_GEN_ADDR                      0xFC07FFFF
+#define   S_0286CC_BARYC_SAMPLE_CNTL(x)                (((x) & 0x3) << 26)
+#define   G_0286CC_BARYC_SAMPLE_CNTL(x)                (((x) >> 26) & 0x3)
+#define   C_0286CC_BARYC_SAMPLE_CNTL                   0xF3FFFFFF
+#define   S_0286CC_PERSP_GRADIENT_ENA(x)               (((x) & 0x1) << 28)
+#define   G_0286CC_PERSP_GRADIENT_ENA(x)               (((x) >> 28) & 0x1)
+#define   C_0286CC_PERSP_GRADIENT_ENA                  0xEFFFFFFF
+#define   S_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) & 0x1) << 29)
+#define   G_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) >> 29) & 0x1)
+#define   C_0286CC_LINEAR_GRADIENT_ENA                 0xDFFFFFFF
+#define   S_0286CC_POSITION_SAMPLE(x)                  (((x) & 0x1) << 30)
+#define   G_0286CC_POSITION_SAMPLE(x)                  (((x) >> 30) & 0x1)
+#define   C_0286CC_POSITION_SAMPLE                     0xBFFFFFFF
+#define   S_0286CC_BARYC_AT_SAMPLE_ENA(x)              (((x) & 0x1) << 31)
+#define   G_0286CC_BARYC_AT_SAMPLE_ENA(x)              (((x) >> 31) & 0x1)
+#define   C_0286CC_BARYC_AT_SAMPLE_ENA                 0x7FFFFFFF
+#define R_0286D0_SPI_PS_IN_CONTROL_1                 0x0286D0
+#define   S_0286D0_GEN_INDEX_PIX(x)                    (((x) & 0x1) << 0)
+#define   G_0286D0_GEN_INDEX_PIX(x)                    (((x) >> 0) & 0x1)
+#define   C_0286D0_GEN_INDEX_PIX                       0xFFFFFFFE
+#define   S_0286D0_GEN_INDEX_PIX_ADDR(x)               (((x) & 0x7F) << 1)
+#define   G_0286D0_GEN_INDEX_PIX_ADDR(x)               (((x) >> 1) & 0x7F)
+#define   C_0286D0_GEN_INDEX_PIX_ADDR                  0xFFFFFF01
+#define   S_0286D0_FRONT_FACE_ENA(x)                   (((x) & 0x1) << 8)
+#define   G_0286D0_FRONT_FACE_ENA(x)                   (((x) >> 8) & 0x1)
+#define   C_0286D0_FRONT_FACE_ENA                      0xFFFFFEFF
+#define   S_0286D0_FRONT_FACE_CHAN(x)                  (((x) & 0x3) << 9)
+#define   G_0286D0_FRONT_FACE_CHAN(x)                  (((x) >> 9) & 0x3)
+#define   C_0286D0_FRONT_FACE_CHAN                     0xFFFFF9FF
+#define   S_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) & 0x1) << 11)
+#define   G_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) >> 11) & 0x1)
+#define   C_0286D0_FRONT_FACE_ALL_BITS                 0xFFFFF7FF
+#define   S_0286D0_FRONT_FACE_ADDR(x)                  (((x) & 0x1F) << 12)
+#define   G_0286D0_FRONT_FACE_ADDR(x)                  (((x) >> 12) & 0x1F)
+#define   C_0286D0_FRONT_FACE_ADDR                     0xFFFE0FFF
+#define   S_0286D0_FOG_ADDR(x)                         (((x) & 0x7F) << 17)
+#define   G_0286D0_FOG_ADDR(x)                         (((x) >> 17) & 0x7F)
+#define   C_0286D0_FOG_ADDR                            0xFF01FFFF
+#define   S_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) & 0x1) << 24)
+#define   G_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) >> 24) & 0x1)
+#define   C_0286D0_FIXED_PT_POSITION_ENA               0xFEFFFFFF
+#define   S_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) & 0x1F) << 25)
+#define   G_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) >> 25) & 0x1F)
+#define   C_0286D0_FIXED_PT_POSITION_ADDR              0xC1FFFFFF
+#define R_0286C4_SPI_VS_OUT_CONFIG                   0x0286C4
+#define   S_0286C4_VS_PER_COMPONENT(x)                 (((x) & 0x1) << 0)
+#define   G_0286C4_VS_PER_COMPONENT(x)                 (((x) >> 0) & 0x1)
+#define   C_0286C4_VS_PER_COMPONENT                    0xFFFFFFFE
+#define   S_0286C4_VS_EXPORT_COUNT(x)                  (((x) & 0x1F) << 1)
+#define   G_0286C4_VS_EXPORT_COUNT(x)                  (((x) >> 1) & 0x1F)
+#define   C_0286C4_VS_EXPORT_COUNT                     0xFFFFFFC1
+#define   S_0286C4_VS_EXPORTS_FOG(x)                   (((x) & 0x1) << 8)
+#define   G_0286C4_VS_EXPORTS_FOG(x)                   (((x) >> 8) & 0x1)
+#define   C_0286C4_VS_EXPORTS_FOG                      0xFFFFFEFF
+#define   S_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) & 0x1F) << 9)
+#define   G_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) >> 9) & 0x1F)
+#define   C_0286C4_VS_OUT_FOG_VEC_ADDR                 0xFFFFC1FF
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028240_TL_X                                0xFFFFC000
+#define   S_028240_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028240_TL_Y                                0xC000FFFF
+#define   S_028240_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028240_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028240_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR            0x028244
+#define   S_028244_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028244_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028244_BR_X                                0xFFFFC000
+#define   S_028244_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028244_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028244_BR_Y                                0xC000FFFF
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL             0x028030
+#define   S_028030_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028030_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028030_TL_X                                0xFFFF8000
+#define   S_028030_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028030_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028030_TL_Y                                0x8000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR             0x028034
+#define   S_028034_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028034_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028034_BR_X                                0xFFFF8000
+#define   S_028034_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028034_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028034_BR_Y                                0x8000FFFF
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL             0x028204
+#define   S_028204_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028204_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028204_TL_X                                0xFFFFC000
+#define   S_028204_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028204_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028204_TL_Y                                0xC000FFFF
+#define   S_028204_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028204_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028204_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR             0x028208
+#define   S_028208_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028208_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028208_BR_X                                0xFFFFC000
+#define   S_028208_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028208_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028208_BR_Y                                0xC000FFFF
+#define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
+#define   S_0287F0_SOURCE_SELECT(x)                    (((x) & 0x3) << 0)
+#define   G_0287F0_SOURCE_SELECT(x)                    (((x) >> 0) & 0x3)
+#define   C_0287F0_SOURCE_SELECT                       0xFFFFFFFC
+#define   S_0287F0_MAJOR_MODE(x)                       (((x) & 0x3) << 2)
+#define   G_0287F0_MAJOR_MODE(x)                       (((x) >> 2) & 0x3)
+#define   C_0287F0_MAJOR_MODE                          0xFFFFFFF3
+#define   S_0287F0_SPRITE_EN(x)                        (((x) & 0x1) << 4)
+#define   G_0287F0_SPRITE_EN(x)                        (((x) >> 4) & 0x1)
+#define   C_0287F0_SPRITE_EN                           0xFFFFFFEF
+#define   S_0287F0_NOT_EOP(x)                          (((x) & 0x1) << 5)
+#define   G_0287F0_NOT_EOP(x)                          (((x) >> 5) & 0x1)
+#define   C_0287F0_NOT_EOP                             0xFFFFFFDF
+#define   S_0287F0_USE_OPAQUE(x)                       (((x) & 0x1) << 6)
+#define   G_0287F0_USE_OPAQUE(x)                       (((x) >> 6) & 0x1)
+#define   C_0287F0_USE_OPAQUE                          0xFFFFFFBF
+#define R_0280A0_CB_COLOR0_INFO                      0x0280A0
+#define R_0280A4_CB_COLOR1_INFO                      0x0280A4
+#define R_0280A8_CB_COLOR2_INFO                      0x0280A8
+#define R_0280AC_CB_COLOR3_INFO                      0x0280AC
+#define R_0280B0_CB_COLOR4_INFO                      0x0280B0
+#define R_0280B4_CB_COLOR5_INFO                      0x0280B4
+#define R_0280B8_CB_COLOR6_INFO                      0x0280B8
+#define R_0280BC_CB_COLOR7_INFO                      0x0280BC
+#define R_02800C_DB_DEPTH_BASE                       0x02800C
+#define R_028000_DB_DEPTH_SIZE                       0x028000
+#define R_028004_DB_DEPTH_VIEW                       0x028004
+#define R_028010_DB_DEPTH_INFO                       0x028010
+#define R_028D24_DB_HTILE_SURFACE                    0x028D24
+#define R_028D34_DB_PREFETCH_LIMIT                   0x028D34
+#define R_0286D4_SPI_INTERP_CONTROL_0                0x0286D4
+#define R_028A48_PA_SC_MPASS_PS_CNTL                 0x028A48
+#define R_028C00_PA_SC_LINE_CNTL                     0x028C00
+#define R_028C04_PA_SC_AA_CONFIG                     0x028C04
+#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX           0x028C1C
+#define R_028C48_PA_SC_AA_MASK                       0x028C48
+#define R_028810_PA_CL_CLIP_CNTL                     0x028810
+#define R_02881C_PA_CL_VS_OUT_CNTL                   0x02881C
+#define R_028820_PA_CL_NANINF_CNTL                   0x028820
+#define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ              0x028C0C
+#define R_028C10_PA_CL_GB_VERT_DISC_ADJ              0x028C10
+#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ              0x028C14
+#define R_028C18_PA_CL_GB_HORZ_DISC_ADJ              0x028C18
+#define R_028814_PA_SU_SC_MODE_CNTL                  0x028814
+#define R_028A00_PA_SU_POINT_SIZE                    0x028A00
+#define R_028A04_PA_SU_POINT_MINMAX                  0x028A04
+#define R_028A08_PA_SU_LINE_CNTL                     0x028A08
+#define R_028A0C_PA_SC_LINE_STIPPLE                  0x028A0C
+#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
+#define R_028DFC_PA_SU_POLY_OFFSET_CLAMP             0x028DFC
+#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE       0x028E00
+#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x028E04
+#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
+#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
+#define R_028818_PA_CL_VTE_CNTL                      0x028818
+#define R_02843C_PA_CL_VPORT_XSCALE_0                0x02843C
+#define R_028444_PA_CL_VPORT_YSCALE_0                0x028444
+#define R_02844C_PA_CL_VPORT_ZSCALE_0                0x02844C
+#define R_028440_PA_CL_VPORT_XOFFSET_0               0x028440
+#define R_028448_PA_CL_VPORT_YOFFSET_0               0x028448
+#define R_028450_PA_CL_VPORT_ZOFFSET_0               0x028450
+#define R_028250_PA_SC_VPORT_SCISSOR_0_TL            0x028250
+#define R_028254_PA_SC_VPORT_SCISSOR_0_BR            0x028254
+#define R_028780_CB_BLEND0_CONTROL                   0x028780
+#define R_028784_CB_BLEND1_CONTROL                   0x028784
+#define R_028788_CB_BLEND2_CONTROL                   0x028788
+#define R_02878C_CB_BLEND3_CONTROL                   0x02878C
+#define R_028790_CB_BLEND4_CONTROL                   0x028790
+#define R_028794_CB_BLEND5_CONTROL                   0x028794
+#define R_028798_CB_BLEND6_CONTROL                   0x028798
+#define R_02879C_CB_BLEND7_CONTROL                   0x02879C
+#define R_028804_CB_BLEND_CONTROL                    0x028804
+#define R_028028_DB_STENCIL_CLEAR                    0x028028
+#define R_02802C_DB_DEPTH_CLEAR                      0x02802C
+#define R_028430_DB_STENCILREFMASK                   0x028430
+#define R_028434_DB_STENCILREFMASK_BF                0x028434
+#define R_028800_DB_DEPTH_CONTROL                    0x028800
+#define R_02880C_DB_SHADER_CONTROL                   0x02880C
+#define R_028D0C_DB_RENDER_CONTROL                   0x028D0C
+#define   S_028D0C_DEPTH_CLEAR_ENABLE(x)               (((x) & 0x1) << 0)
+#define   S_028D0C_STENCIL_CLEAR_ENABLE(x)             (((x) & 0x1) << 1)
+#define   S_028D0C_DEPTH_COPY_ENABLE(x)                (((x) & 0x1) << 2)
+#define   S_028D0C_STENCIL_COPY_ENABLE(x)              (((x) & 0x1) << 3)
+#define   S_028D0C_RESUMMARIZE_ENABLE(x)               (((x) & 0x1) << 4)
+#define   S_028D0C_STENCIL_COMPRESS_DISABLE(x)         (((x) & 0x1) << 5)
+#define   S_028D0C_DEPTH_COMPRESS_DISABLE(x)           (((x) & 0x1) << 6)
+#define   S_028D0C_COPY_CENTROID(x)                    (((x) & 0x1) << 7)
+#define   S_028D0C_COPY_SAMPLE(x)                      (((x) & 0x1) << 8)
+#define   S_028D0C_R700_PERFECT_ZPASS_COUNTS(x)        (((x) & 0x1) << 15)
+#define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
+#define R_028D2C_DB_SRESULTS_COMPARE_STATE1          0x028D2C
+#define R_028D30_DB_PRELOAD_CONTROL                  0x028D30
+#define R_028D44_DB_ALPHA_TO_MASK                    0x028D44
+#define R_028868_SQ_PGM_RESOURCES_VS                 0x028868
+#define R_0286CC_SPI_PS_IN_CONTROL_0                 0x0286CC
+#define R_0286D0_SPI_PS_IN_CONTROL_1                 0x0286D0
+#define R_028644_SPI_PS_INPUT_CNTL_0                 0x028644
+#define R_028648_SPI_PS_INPUT_CNTL_1                 0x028648
+#define R_02864C_SPI_PS_INPUT_CNTL_2                 0x02864C
+#define R_028650_SPI_PS_INPUT_CNTL_3                 0x028650
+#define R_028654_SPI_PS_INPUT_CNTL_4                 0x028654
+#define R_028658_SPI_PS_INPUT_CNTL_5                 0x028658
+#define R_02865C_SPI_PS_INPUT_CNTL_6                 0x02865C
+#define R_028660_SPI_PS_INPUT_CNTL_7                 0x028660
+#define R_028664_SPI_PS_INPUT_CNTL_8                 0x028664
+#define R_028668_SPI_PS_INPUT_CNTL_9                 0x028668
+#define R_02866C_SPI_PS_INPUT_CNTL_10                0x02866C
+#define R_028670_SPI_PS_INPUT_CNTL_11                0x028670
+#define R_028674_SPI_PS_INPUT_CNTL_12                0x028674
+#define R_028678_SPI_PS_INPUT_CNTL_13                0x028678
+#define R_02867C_SPI_PS_INPUT_CNTL_14                0x02867C
+#define R_028680_SPI_PS_INPUT_CNTL_15                0x028680
+#define R_028684_SPI_PS_INPUT_CNTL_16                0x028684
+#define R_028688_SPI_PS_INPUT_CNTL_17                0x028688
+#define R_02868C_SPI_PS_INPUT_CNTL_18                0x02868C
+#define R_028690_SPI_PS_INPUT_CNTL_19                0x028690
+#define R_028694_SPI_PS_INPUT_CNTL_20                0x028694
+#define R_028698_SPI_PS_INPUT_CNTL_21                0x028698
+#define R_02869C_SPI_PS_INPUT_CNTL_22                0x02869C
+#define R_0286A0_SPI_PS_INPUT_CNTL_23                0x0286A0
+#define R_0286A4_SPI_PS_INPUT_CNTL_24                0x0286A4
+#define R_0286A8_SPI_PS_INPUT_CNTL_25                0x0286A8
+#define R_0286AC_SPI_PS_INPUT_CNTL_26                0x0286AC
+#define R_0286B0_SPI_PS_INPUT_CNTL_27                0x0286B0
+#define R_0286B4_SPI_PS_INPUT_CNTL_28                0x0286B4
+#define R_0286B8_SPI_PS_INPUT_CNTL_29                0x0286B8
+#define R_0286BC_SPI_PS_INPUT_CNTL_30                0x0286BC
+#define R_0286C0_SPI_PS_INPUT_CNTL_31                0x0286C0
+#define R_028850_SQ_PGM_RESOURCES_PS                 0x028850
+#define R_028854_SQ_PGM_EXPORTS_PS                   0x028854
+#define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
+#define R_028A7C_VGT_DMA_INDEX_TYPE                  0x028A7C
+#define R_028A88_VGT_DMA_NUM_INSTANCES               0x028A88
+#define R_008970_VGT_NUM_INDICES                     0x008970
+#define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
+#define R_028238_CB_TARGET_MASK                      0x028238
+#define R_02823C_CB_SHADER_MASK                      0x02823C
+#define R_028060_CB_COLOR0_SIZE                      0x028060
+#define   S_028060_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
+#define   G_028060_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
+#define   C_028060_PITCH_TILE_MAX                      0xFFFFFC00
+#define   S_028060_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
+#define   G_028060_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
+#define   C_028060_SLICE_TILE_MAX                      0xC00003FF
+#define R_028064_CB_COLOR1_SIZE                      0x028064
+#define R_028068_CB_COLOR2_SIZE                      0x028068
+#define R_02806C_CB_COLOR3_SIZE                      0x02806C
+#define R_028070_CB_COLOR4_SIZE                      0x028070
+#define R_028074_CB_COLOR5_SIZE                      0x028074
+#define R_028078_CB_COLOR6_SIZE                      0x028078
+#define R_02807C_CB_COLOR7_SIZE                      0x02807C
+#define R_028040_CB_COLOR0_BASE                      0x028040
+#define R_028044_CB_COLOR1_BASE                      0x028044
+#define R_028048_CB_COLOR2_BASE                      0x028048
+#define R_02804C_CB_COLOR3_BASE                      0x02804C
+#define R_028050_CB_COLOR4_BASE                      0x028050
+#define R_028054_CB_COLOR5_BASE                      0x028054
+#define R_028058_CB_COLOR6_BASE                      0x028058
+#define R_02805C_CB_COLOR7_BASE                      0x02805C
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028240_TL_X                                0xFFFFC000
+#define   S_028240_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028240_TL_Y                                0xC000FFFF
+#define R_028C04_PA_SC_AA_CONFIG                     0x028C04
+#define   S_028C04_MSAA_NUM_SAMPLES(x)                 (((x) & 0x3) << 0)
+#define   G_028C04_MSAA_NUM_SAMPLES(x)                 (((x) >> 0) & 0x3)
+#define   C_028C04_MSAA_NUM_SAMPLES                    0xFFFFFFFC
+#define   S_028C04_AA_MASK_CENTROID_DTMN(x)            (((x) & 0x1) << 4)
+#define   G_028C04_AA_MASK_CENTROID_DTMN(x)            (((x) >> 4) & 0x1)
+#define   C_028C04_AA_MASK_CENTROID_DTMN               0xFFFFFFEF
+#define   S_028C04_MAX_SAMPLE_DIST(x)                  (((x) & 0xF) << 13)
+#define   G_028C04_MAX_SAMPLE_DIST(x)                  (((x) >> 13) & 0xF)
+#define   C_028C04_MAX_SAMPLE_DIST                     0xFFFE1FFF
+#define R_0288CC_SQ_PGM_CF_OFFSET_PS                 0x0288CC
+#define R_0288DC_SQ_PGM_CF_OFFSET_FS                 0x0288DC
+#define R_0288D0_SQ_PGM_CF_OFFSET_VS                 0x0288D0
+#define R_028840_SQ_PGM_START_PS                     0x028840
+#define R_028894_SQ_PGM_START_FS                     0x028894
+#define R_028858_SQ_PGM_START_VS                     0x028858
+#define R_028080_CB_COLOR0_VIEW                      0x028080
+#define   S_028080_SLICE_START(x)                      (((x) & 0x7FF) << 0)
+#define   G_028080_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
+#define   C_028080_SLICE_START                         0xFFFFF800
+#define   S_028080_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
+#define   G_028080_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
+#define   C_028080_SLICE_MAX                           0xFF001FFF
+#define R_028084_CB_COLOR1_VIEW                      0x028084
+#define R_028088_CB_COLOR2_VIEW                      0x028088
+#define R_02808C_CB_COLOR3_VIEW                      0x02808C
+#define R_028090_CB_COLOR4_VIEW                      0x028090
+#define R_028094_CB_COLOR5_VIEW                      0x028094
+#define R_028098_CB_COLOR6_VIEW                      0x028098
+#define R_02809C_CB_COLOR7_VIEW                      0x02809C
+#define R_028100_CB_COLOR0_MASK                      0x028100
+#define   S_028100_CMASK_BLOCK_MAX(x)                  (((x) & 0xFFF) << 0)
+#define   G_028100_CMASK_BLOCK_MAX(x)                  (((x) >> 0) & 0xFFF)
+#define   C_028100_CMASK_BLOCK_MAX                     0xFFFFF000
+#define   S_028100_FMASK_TILE_MAX(x)                   (((x) & 0xFFFFF) << 12)
+#define   G_028100_FMASK_TILE_MAX(x)                   (((x) >> 12) & 0xFFFFF)
+#define   C_028100_FMASK_TILE_MAX                      0x00000FFF
+#define R_028104_CB_COLOR1_MASK                      0x028104
+#define R_028108_CB_COLOR2_MASK                      0x028108
+#define R_02810C_CB_COLOR3_MASK                      0x02810C
+#define R_028110_CB_COLOR4_MASK                      0x028110
+#define R_028114_CB_COLOR5_MASK                      0x028114
+#define R_028118_CB_COLOR6_MASK                      0x028118
+#define R_02811C_CB_COLOR7_MASK                      0x02811C
+#define R_028040_CB_COLOR0_BASE                      0x028040
+#define   S_028040_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028040_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028040_BASE_256B                           0x00000000
+#define R_0280E0_CB_COLOR0_FRAG                      0x0280E0
+#define   S_0280E0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_0280E0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0280E0_BASE_256B                           0x00000000
+#define R_0280E4_CB_COLOR1_FRAG                      0x0280E4
+#define R_0280E8_CB_COLOR2_FRAG                      0x0280E8
+#define R_0280EC_CB_COLOR3_FRAG                      0x0280EC
+#define R_0280F0_CB_COLOR4_FRAG                      0x0280F0
+#define R_0280F4_CB_COLOR5_FRAG                      0x0280F4
+#define R_0280F8_CB_COLOR6_FRAG                      0x0280F8
+#define R_0280FC_CB_COLOR7_FRAG                      0x0280FC
+#define R_0280C0_CB_COLOR0_TILE                      0x0280C0
+#define   S_0280C0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_0280C0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0280C0_BASE_256B                           0x00000000
+#define R_0280C4_CB_COLOR1_TILE                      0x0280C4
+#define R_0280C8_CB_COLOR2_TILE                      0x0280C8
+#define R_0280CC_CB_COLOR3_TILE                      0x0280CC
+#define R_0280D0_CB_COLOR4_TILE                      0x0280D0
+#define R_0280D4_CB_COLOR5_TILE                      0x0280D4
+#define R_0280D8_CB_COLOR6_TILE                      0x0280D8
+#define R_0280DC_CB_COLOR7_TILE                      0x0280DC
+#define R_028808_CB_COLOR_CONTROL                    0x028808
+#define   S_028808_FOG_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_028808_FOG_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_028808_FOG_ENABLE                          0xFFFFFFFE
+#define   S_028808_MULTIWRITE_ENABLE(x)                (((x) & 0x1) << 1)
+#define   G_028808_MULTIWRITE_ENABLE(x)                (((x) >> 1) & 0x1)
+#define   C_028808_MULTIWRITE_ENABLE                   0xFFFFFFFD
+#define   S_028808_DITHER_ENABLE(x)                    (((x) & 0x1) << 2)
+#define   G_028808_DITHER_ENABLE(x)                    (((x) >> 2) & 0x1)
+#define   C_028808_DITHER_ENABLE                       0xFFFFFFFB
+#define   S_028808_DEGAMMA_ENABLE(x)                   (((x) & 0x1) << 3)
+#define   G_028808_DEGAMMA_ENABLE(x)                   (((x) >> 3) & 0x1)
+#define   C_028808_DEGAMMA_ENABLE                      0xFFFFFFF7
+#define   S_028808_SPECIAL_OP(x)                       (((x) & 0x7) << 4)
+#define   G_028808_SPECIAL_OP(x)                       (((x) >> 4) & 0x7)
+#define   C_028808_SPECIAL_OP                          0xFFFFFF8F
+#define   S_028808_PER_MRT_BLEND(x)                    (((x) & 0x1) << 7)
+#define   G_028808_PER_MRT_BLEND(x)                    (((x) >> 7) & 0x1)
+#define   C_028808_PER_MRT_BLEND                       0xFFFFFF7F
+#define   S_028808_TARGET_BLEND_ENABLE(x)              (((x) & 0xFF) << 8)
+#define   G_028808_TARGET_BLEND_ENABLE(x)              (((x) >> 8) & 0xFF)
+#define   C_028808_TARGET_BLEND_ENABLE                 0xFFFF00FF
+#define   S_028808_ROP3(x)                             (((x) & 0xFF) << 16)
+#define   G_028808_ROP3(x)                             (((x) >> 16) & 0xFF)
+#define   C_028808_ROP3                                0xFF00FFFF
+#define R_028614_SPI_VS_OUT_ID_0                     0x028614
+#define   S_028614_SEMANTIC_0(x)                       (((x) & 0xFF) << 0)
+#define   G_028614_SEMANTIC_0(x)                       (((x) >> 0) & 0xFF)
+#define   C_028614_SEMANTIC_0                          0xFFFFFF00
+#define   S_028614_SEMANTIC_1(x)                       (((x) & 0xFF) << 8)
+#define   G_028614_SEMANTIC_1(x)                       (((x) >> 8) & 0xFF)
+#define   C_028614_SEMANTIC_1                          0xFFFF00FF
+#define   S_028614_SEMANTIC_2(x)                       (((x) & 0xFF) << 16)
+#define   G_028614_SEMANTIC_2(x)                       (((x) >> 16) & 0xFF)
+#define   C_028614_SEMANTIC_2                          0xFF00FFFF
+#define   S_028614_SEMANTIC_3(x)                       (((x) & 0xFF) << 24)
+#define   G_028614_SEMANTIC_3(x)                       (((x) >> 24) & 0xFF)
+#define   C_028614_SEMANTIC_3                          0x00FFFFFF
+#define R_028618_SPI_VS_OUT_ID_1                     0x028618
+#define R_02861C_SPI_VS_OUT_ID_2                     0x02861C
+#define R_028620_SPI_VS_OUT_ID_3                     0x028620
+#define R_028624_SPI_VS_OUT_ID_4                     0x028624
+#define R_028628_SPI_VS_OUT_ID_5                     0x028628
+#define R_02862C_SPI_VS_OUT_ID_6                     0x02862C
+#define R_028630_SPI_VS_OUT_ID_7                     0x028630
+#define R_028634_SPI_VS_OUT_ID_8                     0x028634
+#define R_028638_SPI_VS_OUT_ID_9                     0x028638
+#define R_038000_SQ_TEX_RESOURCE_WORD0_0             0x038000
+#define   S_038000_DIM(x)                              (((x) & 0x7) << 0)
+#define   G_038000_DIM(x)                              (((x) >> 0) & 0x7)
+#define   C_038000_DIM                                 0xFFFFFFF8
+#define   S_038000_TILE_MODE(x)                        (((x) & 0xF) << 3)
+#define   G_038000_TILE_MODE(x)                        (((x) >> 3) & 0xF)
+#define   C_038000_TILE_MODE                           0xFFFFFF87
+#define   S_038000_TILE_TYPE(x)                        (((x) & 0x1) << 7)
+#define   G_038000_TILE_TYPE(x)                        (((x) >> 7) & 0x1)
+#define   C_038000_TILE_TYPE                           0xFFFFFF7F
+#define   S_038000_PITCH(x)                            (((x) & 0x7FF) << 8)
+#define   G_038000_PITCH(x)                            (((x) >> 8) & 0x7FF)
+#define   C_038000_PITCH                               0xFFF800FF
+#define   S_038000_TEX_WIDTH(x)                        (((x) & 0x1FFF) << 19)
+#define   G_038000_TEX_WIDTH(x)                        (((x) >> 19) & 0x1FFF)
+#define   C_038000_TEX_WIDTH                           0x0007FFFF
+#define R_038004_SQ_TEX_RESOURCE_WORD1_0             0x038004
+#define   S_038004_TEX_HEIGHT(x)                       (((x) & 0x1FFF) << 0)
+#define   G_038004_TEX_HEIGHT(x)                       (((x) >> 0) & 0x1FFF)
+#define   C_038004_TEX_HEIGHT                          0xFFFFE000
+#define   S_038004_TEX_DEPTH(x)                        (((x) & 0x1FFF) << 13)
+#define   G_038004_TEX_DEPTH(x)                        (((x) >> 13) & 0x1FFF)
+#define   C_038004_TEX_DEPTH                           0xFC001FFF
+#define   S_038004_DATA_FORMAT(x)                      (((x) & 0x3F) << 26)
+#define   G_038004_DATA_FORMAT(x)                      (((x) >> 26) & 0x3F)
+#define   C_038004_DATA_FORMAT                         0x03FFFFFF
+#define     V_038004_COLOR_INVALID                     0x00000000
+#define     V_038004_COLOR_8                           0x00000001
+#define     V_038004_COLOR_4_4                         0x00000002
+#define     V_038004_COLOR_3_3_2                       0x00000003
+#define     V_038004_COLOR_16                          0x00000005
+#define     V_038004_COLOR_16_FLOAT                    0x00000006
+#define     V_038004_COLOR_8_8                         0x00000007
+#define     V_038004_COLOR_5_6_5                       0x00000008
+#define     V_038004_COLOR_6_5_5                       0x00000009
+#define     V_038004_COLOR_1_5_5_5                     0x0000000A
+#define     V_038004_COLOR_4_4_4_4                     0x0000000B
+#define     V_038004_COLOR_5_5_5_1                     0x0000000C
+#define     V_038004_COLOR_32                          0x0000000D
+#define     V_038004_COLOR_32_FLOAT                    0x0000000E
+#define     V_038004_COLOR_16_16                       0x0000000F
+#define     V_038004_COLOR_16_16_FLOAT                 0x00000010
+#define     V_038004_COLOR_8_24                        0x00000011
+#define     V_038004_COLOR_8_24_FLOAT                  0x00000012
+#define     V_038004_COLOR_24_8                        0x00000013
+#define     V_038004_COLOR_24_8_FLOAT                  0x00000014
+#define     V_038004_COLOR_10_11_11                    0x00000015
+#define     V_038004_COLOR_10_11_11_FLOAT              0x00000016
+#define     V_038004_COLOR_11_11_10                    0x00000017
+#define     V_038004_COLOR_11_11_10_FLOAT              0x00000018
+#define     V_038004_COLOR_2_10_10_10                  0x00000019
+#define     V_038004_COLOR_8_8_8_8                     0x0000001A
+#define     V_038004_COLOR_10_10_10_2                  0x0000001B
+#define     V_038004_COLOR_X24_8_32_FLOAT              0x0000001C
+#define     V_038004_COLOR_32_32                       0x0000001D
+#define     V_038004_COLOR_32_32_FLOAT                 0x0000001E
+#define     V_038004_COLOR_16_16_16_16                 0x0000001F
+#define     V_038004_COLOR_16_16_16_16_FLOAT           0x00000020
+#define     V_038004_COLOR_32_32_32_32                 0x00000022
+#define     V_038004_COLOR_32_32_32_32_FLOAT           0x00000023
+#define R_038008_SQ_TEX_RESOURCE_WORD2_0             0x038008
+#define   S_038008_BASE_ADDRESS(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_038008_BASE_ADDRESS(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_038008_BASE_ADDRESS                        0x00000000
+#define R_03800C_SQ_TEX_RESOURCE_WORD3_0             0x03800C
+#define   S_03800C_MIP_ADDRESS(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_03800C_MIP_ADDRESS(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_03800C_MIP_ADDRESS                         0x00000000
+#define R_038010_SQ_TEX_RESOURCE_WORD4_0             0x038010
+#define   S_038010_FORMAT_COMP_X(x)                    (((x) & 0x3) << 0)
+#define   G_038010_FORMAT_COMP_X(x)                    (((x) >> 0) & 0x3)
+#define   C_038010_FORMAT_COMP_X                       0xFFFFFFFC
+#define   S_038010_FORMAT_COMP_Y(x)                    (((x) & 0x3) << 2)
+#define   G_038010_FORMAT_COMP_Y(x)                    (((x) >> 2) & 0x3)
+#define   C_038010_FORMAT_COMP_Y                       0xFFFFFFF3
+#define   S_038010_FORMAT_COMP_Z(x)                    (((x) & 0x3) << 4)
+#define   G_038010_FORMAT_COMP_Z(x)                    (((x) >> 4) & 0x3)
+#define   C_038010_FORMAT_COMP_Z                       0xFFFFFFCF
+#define   S_038010_FORMAT_COMP_W(x)                    (((x) & 0x3) << 6)
+#define   G_038010_FORMAT_COMP_W(x)                    (((x) >> 6) & 0x3)
+#define   C_038010_FORMAT_COMP_W                       0xFFFFFF3F
+#define   S_038010_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 8)
+#define   G_038010_NUM_FORMAT_ALL(x)                   (((x) >> 8) & 0x3)
+#define   C_038010_NUM_FORMAT_ALL                      0xFFFFFCFF
+#define   S_038010_SRF_MODE_ALL(x)                     (((x) & 0x1) << 10)
+#define   G_038010_SRF_MODE_ALL(x)                     (((x) >> 10) & 0x1)
+#define   C_038010_SRF_MODE_ALL                        0xFFFFFBFF
+#define   S_038010_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 11)
+#define   G_038010_FORCE_DEGAMMA(x)                    (((x) >> 11) & 0x1)
+#define   C_038010_FORCE_DEGAMMA                       0xFFFFF7FF
+#define   S_038010_ENDIAN_SWAP(x)                      (((x) & 0x3) << 12)
+#define   G_038010_ENDIAN_SWAP(x)                      (((x) >> 12) & 0x3)
+#define   C_038010_ENDIAN_SWAP                         0xFFFFCFFF
+#define   S_038010_REQUEST_SIZE(x)                     (((x) & 0x3) << 14)
+#define   G_038010_REQUEST_SIZE(x)                     (((x) >> 14) & 0x3)
+#define   C_038010_REQUEST_SIZE                        0xFFFF3FFF
+#define   S_038010_DST_SEL_X(x)                        (((x) & 0x7) << 16)
+#define   G_038010_DST_SEL_X(x)                        (((x) >> 16) & 0x7)
+#define   C_038010_DST_SEL_X                           0xFFF8FFFF
+#define   S_038010_DST_SEL_Y(x)                        (((x) & 0x7) << 19)
+#define   G_038010_DST_SEL_Y(x)                        (((x) >> 19) & 0x7)
+#define   C_038010_DST_SEL_Y                           0xFFC7FFFF
+#define   S_038010_DST_SEL_Z(x)                        (((x) & 0x7) << 22)
+#define   G_038010_DST_SEL_Z(x)                        (((x) >> 22) & 0x7)
+#define   C_038010_DST_SEL_Z                           0xFE3FFFFF
+#define   S_038010_DST_SEL_W(x)                        (((x) & 0x7) << 25)
+#define   G_038010_DST_SEL_W(x)                        (((x) >> 25) & 0x7)
+#define   C_038010_DST_SEL_W                           0xF1FFFFFF
+#define   S_038010_BASE_LEVEL(x)                       (((x) & 0xF) << 28)
+#define   G_038010_BASE_LEVEL(x)                       (((x) >> 28) & 0xF)
+#define   C_038010_BASE_LEVEL                          0x0FFFFFFF
+#define R_038014_SQ_TEX_RESOURCE_WORD5_0             0x038014
+#define   S_038014_LAST_LEVEL(x)                       (((x) & 0xF) << 0)
+#define   G_038014_LAST_LEVEL(x)                       (((x) >> 0) & 0xF)
+#define   C_038014_LAST_LEVEL                          0xFFFFFFF0
+#define   S_038014_BASE_ARRAY(x)                       (((x) & 0x1FFF) << 4)
+#define   G_038014_BASE_ARRAY(x)                       (((x) >> 4) & 0x1FFF)
+#define   C_038014_BASE_ARRAY                          0xFFFE000F
+#define   S_038014_LAST_ARRAY(x)                       (((x) & 0x1FFF) << 17)
+#define   G_038014_LAST_ARRAY(x)                       (((x) >> 17) & 0x1FFF)
+#define   C_038014_LAST_ARRAY                          0xC001FFFF
+#define R_038018_SQ_TEX_RESOURCE_WORD6_0             0x038018
+#define   S_038018_MPEG_CLAMP(x)                       (((x) & 0x3) << 0)
+#define   G_038018_MPEG_CLAMP(x)                       (((x) >> 0) & 0x3)
+#define   C_038018_MPEG_CLAMP                          0xFFFFFFFC
+#define   S_038018_PERF_MODULATION(x)                  (((x) & 0x7) << 5)
+#define   G_038018_PERF_MODULATION(x)                  (((x) >> 5) & 0x7)
+#define   C_038018_PERF_MODULATION                     0xFFFFFF1F
+#define   S_038018_INTERLACED(x)                       (((x) & 0x1) << 8)
+#define   G_038018_INTERLACED(x)                       (((x) >> 8) & 0x1)
+#define   C_038018_INTERLACED                          0xFFFFFEFF
+#define   S_038018_TYPE(x)                             (((x) & 0x3) << 30)
+#define   G_038018_TYPE(x)                             (((x) >> 30) & 0x3)
+#define   C_038018_TYPE                                0x3FFFFFFF
+#define R_008040_WAIT_UNTIL                          0x008040
+#define   S_008040_WAIT_CP_DMA_IDLE(x)                 (((x) & 0x1) << 8)
+#define   G_008040_WAIT_CP_DMA_IDLE(x)                 (((x) >> 8) & 0x1)
+#define   C_008040_WAIT_CP_DMA_IDLE                    0xFFFFFEFF
+#define   S_008040_WAIT_CMDFIFO(x)                     (((x) & 0x1) << 10)
+#define   G_008040_WAIT_CMDFIFO(x)                     (((x) >> 10) & 0x1)
+#define   C_008040_WAIT_CMDFIFO                        0xFFFFFBFF
+#define   S_008040_WAIT_2D_IDLE(x)                     (((x) & 0x1) << 14)
+#define   G_008040_WAIT_2D_IDLE(x)                     (((x) >> 14) & 0x1)
+#define   C_008040_WAIT_2D_IDLE                        0xFFFFBFFF
+#define   S_008040_WAIT_3D_IDLE(x)                     (((x) & 0x1) << 15)
+#define   G_008040_WAIT_3D_IDLE(x)                     (((x) >> 15) & 0x1)
+#define   C_008040_WAIT_3D_IDLE                        0xFFFF7FFF
+#define   S_008040_WAIT_2D_IDLECLEAN(x)                (((x) & 0x1) << 16)
+#define   G_008040_WAIT_2D_IDLECLEAN(x)                (((x) >> 16) & 0x1)
+#define   C_008040_WAIT_2D_IDLECLEAN                   0xFFFEFFFF
+#define   S_008040_WAIT_3D_IDLECLEAN(x)                (((x) & 0x1) << 17)
+#define   G_008040_WAIT_3D_IDLECLEAN(x)                (((x) >> 17) & 0x1)
+#define   C_008040_WAIT_3D_IDLECLEAN                   0xFFFDFFFF
+#define   S_008040_WAIT_EXTERN_SIG(x)                  (((x) & 0x1) << 19)
+#define   G_008040_WAIT_EXTERN_SIG(x)                  (((x) >> 19) & 0x1)
+#define   C_008040_WAIT_EXTERN_SIG                     0xFFF7FFFF
+#define   S_008040_CMDFIFO_ENTRIES(x)                  (((x) & 0x1F) << 20)
+#define   G_008040_CMDFIFO_ENTRIES(x)                  (((x) >> 20) & 0x1F)
+#define   C_008040_CMDFIFO_ENTRIES                     0xFE0FFFFF
+#define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
+#define   S_008958_PRIM_TYPE(x)                        (((x) & 0x3F) << 0)
+#define   G_008958_PRIM_TYPE(x)                        (((x) >> 0) & 0x3F)
+#define   C_008958_PRIM_TYPE                           0xFFFFFFC0
+#define R_008C00_SQ_CONFIG                           0x008C00
+#define   S_008C00_VC_ENABLE(x)                        (((x) & 0x1) << 0)
+#define   G_008C00_VC_ENABLE(x)                        (((x) >> 0) & 0x1)
+#define   C_008C00_VC_ENABLE                           0xFFFFFFFE
+#define   S_008C00_EXPORT_SRC_C(x)                     (((x) & 0x1) << 1)
+#define   G_008C00_EXPORT_SRC_C(x)                     (((x) >> 1) & 0x1)
+#define   C_008C00_EXPORT_SRC_C                        0xFFFFFFFD
+#define   S_008C00_DX9_CONSTS(x)                       (((x) & 0x1) << 2)
+#define   G_008C00_DX9_CONSTS(x)                       (((x) >> 2) & 0x1)
+#define   C_008C00_DX9_CONSTS                          0xFFFFFFFB
+#define   S_008C00_ALU_INST_PREFER_VECTOR(x)           (((x) & 0x1) << 3)
+#define   G_008C00_ALU_INST_PREFER_VECTOR(x)           (((x) >> 3) & 0x1)
+#define   C_008C00_ALU_INST_PREFER_VECTOR              0xFFFFFFF7
+#define   S_008C00_DX10_CLAMP(x)                       (((x) & 0x1) << 4)
+#define   G_008C00_DX10_CLAMP(x)                       (((x) >> 4) & 0x1)
+#define   C_008C00_DX10_CLAMP                          0xFFFFFFEF
+#define   S_008C00_ALU_PREFER_ONE_WATERFALL(x)         (((x) & 0x1) << 5)
+#define   G_008C00_ALU_PREFER_ONE_WATERFALL(x)         (((x) >> 5) & 0x1)
+#define   C_008C00_ALU_PREFER_ONE_WATERFALL            0xFFFFFFDF
+#define   S_008C00_ALU_MAX_ONE_WATERFALL(x)            (((x) & 0x1) << 6)
+#define   G_008C00_ALU_MAX_ONE_WATERFALL(x)            (((x) >> 6) & 0x1)
+#define   C_008C00_ALU_MAX_ONE_WATERFALL               0xFFFFFFBF
+#define   S_008C00_CLAUSE_SEQ_PRIO(x)                  (((x) & 0x3) << 8)
+#define   G_008C00_CLAUSE_SEQ_PRIO(x)                  (((x) >> 8) & 0x3)
+#define   C_008C00_CLAUSE_SEQ_PRIO                     0xFFFFFCFF
+#define   S_008C00_PS_PRIO(x)                          (((x) & 0x3) << 24)
+#define   G_008C00_PS_PRIO(x)                          (((x) >> 24) & 0x3)
+#define   C_008C00_PS_PRIO                             0xFCFFFFFF
+#define   S_008C00_VS_PRIO(x)                          (((x) & 0x3) << 26)
+#define   G_008C00_VS_PRIO(x)                          (((x) >> 26) & 0x3)
+#define   C_008C00_VS_PRIO                             0xF3FFFFFF
+#define   S_008C00_GS_PRIO(x)                          (((x) & 0x3) << 28)
+#define   G_008C00_GS_PRIO(x)                          (((x) >> 28) & 0x3)
+#define   C_008C00_GS_PRIO                             0xCFFFFFFF
+#define   S_008C00_ES_PRIO(x)                          (((x) & 0x3) << 30)
+#define   G_008C00_ES_PRIO(x)                          (((x) >> 30) & 0x3)
+#define   C_008C00_ES_PRIO                             0x3FFFFFFF
+#define R_008C04_SQ_GPR_RESOURCE_MGMT_1              0x008C04
+#define   S_008C04_NUM_PS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C04_NUM_PS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C04_NUM_PS_GPRS                         0xFFFFFF00
+#define   S_008C04_NUM_VS_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C04_NUM_VS_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C04_NUM_VS_GPRS                         0xFF00FFFF
+#define   S_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) & 0xF) << 28)
+#define   G_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) >> 28) & 0xF)
+#define   C_008C04_NUM_CLAUSE_TEMP_GPRS                0x0FFFFFFF
+#define R_008C08_SQ_GPR_RESOURCE_MGMT_2              0x008C08
+#define   S_008C08_NUM_GS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C08_NUM_GS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C08_NUM_GS_GPRS                         0xFFFFFF00
+#define   S_008C08_NUM_ES_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C08_NUM_ES_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C08_NUM_ES_GPRS                         0xFF00FFFF
+#define R_008C0C_SQ_THREAD_RESOURCE_MGMT             0x008C0C
+#define   S_008C0C_NUM_PS_THREADS(x)                   (((x) & 0xFF) << 0)
+#define   G_008C0C_NUM_PS_THREADS(x)                   (((x) >> 0) & 0xFF)
+#define   C_008C0C_NUM_PS_THREADS                      0xFFFFFF00
+#define   S_008C0C_NUM_VS_THREADS(x)                   (((x) & 0xFF) << 8)
+#define   G_008C0C_NUM_VS_THREADS(x)                   (((x) >> 8) & 0xFF)
+#define   C_008C0C_NUM_VS_THREADS                      0xFFFF00FF
+#define   S_008C0C_NUM_GS_THREADS(x)                   (((x) & 0xFF) << 16)
+#define   G_008C0C_NUM_GS_THREADS(x)                   (((x) >> 16) & 0xFF)
+#define   C_008C0C_NUM_GS_THREADS                      0xFF00FFFF
+#define   S_008C0C_NUM_ES_THREADS(x)                   (((x) & 0xFF) << 24)
+#define   G_008C0C_NUM_ES_THREADS(x)                   (((x) >> 24) & 0xFF)
+#define   C_008C0C_NUM_ES_THREADS                      0x00FFFFFF
+#define R_008C10_SQ_STACK_RESOURCE_MGMT_1            0x008C10
+#define   S_008C10_NUM_PS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C10_NUM_PS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C10_NUM_PS_STACK_ENTRIES                0xFFFFF000
+#define   S_008C10_NUM_VS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C10_NUM_VS_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C10_NUM_VS_STACK_ENTRIES                0xF000FFFF
+#define R_008C14_SQ_STACK_RESOURCE_MGMT_2            0x008C14
+#define   S_008C14_NUM_GS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C14_NUM_GS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C14_NUM_GS_STACK_ENTRIES                0xFFFFF000
+#define   S_008C14_NUM_ES_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C14_NUM_ES_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C14_NUM_ES_STACK_ENTRIES                0xF000FFFF
+#define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ        0x008D8C
+#define   S_008D8C_RING0_OFFSET(x)                     (((x) & 0xFF) << 0)
+#define   G_008D8C_RING0_OFFSET(x)                     (((x) >> 0) & 0xFF)
+#define   C_008D8C_RING0_OFFSET                        0xFFFFFF00
+#define   S_008D8C_ISOLATE_ES_ENABLE(x)                (((x) & 0x1) << 12)
+#define   G_008D8C_ISOLATE_ES_ENABLE(x)                (((x) >> 12) & 0x1)
+#define   C_008D8C_ISOLATE_ES_ENABLE                   0xFFFFEFFF
+#define   S_008D8C_ISOLATE_GS_ENABLE(x)                (((x) & 0x1) << 13)
+#define   G_008D8C_ISOLATE_GS_ENABLE(x)                (((x) >> 13) & 0x1)
+#define   C_008D8C_ISOLATE_GS_ENABLE                   0xFFFFDFFF
+#define   S_008D8C_VS_PC_LIMIT_ENABLE(x)               (((x) & 0x1) << 14)
+#define   G_008D8C_VS_PC_LIMIT_ENABLE(x)               (((x) >> 14) & 0x1)
+#define   C_008D8C_VS_PC_LIMIT_ENABLE                  0xFFFFBFFF
+#define R_009508_TA_CNTL_AUX                         0x009508
+#define   S_009508_DISABLE_CUBE_WRAP(x)                (((x) & 0x1) << 0)
+#define   G_009508_DISABLE_CUBE_WRAP(x)                (((x) >> 0) & 0x1)
+#define   C_009508_DISABLE_CUBE_WRAP                   0xFFFFFFFE
+#define   S_009508_SYNC_GRADIENT(x)                    (((x) & 0x1) << 24)
+#define   G_009508_SYNC_GRADIENT(x)                    (((x) >> 24) & 0x1)
+#define   C_009508_SYNC_GRADIENT                       0xFEFFFFFF
+#define   S_009508_SYNC_WALKER(x)                      (((x) & 0x1) << 25)
+#define   G_009508_SYNC_WALKER(x)                      (((x) >> 25) & 0x1)
+#define   C_009508_SYNC_WALKER                         0xFDFFFFFF
+#define   S_009508_SYNC_ALIGNER(x)                     (((x) & 0x1) << 26)
+#define   G_009508_SYNC_ALIGNER(x)                     (((x) >> 26) & 0x1)
+#define   C_009508_SYNC_ALIGNER                        0xFBFFFFFF
+#define   S_009508_BILINEAR_PRECISION(x)               (((x) & 0x1) << 31)
+#define   G_009508_BILINEAR_PRECISION(x)               (((x) >> 31) & 0x1)
+#define   C_009508_BILINEAR_PRECISION                  0x7FFFFFFF
+#define R_009714_VC_ENHANCE                          0x009714
+#define R_009830_DB_DEBUG                            0x009830
+#define R_009838_DB_WATERMARKS                       0x009838
+#define   S_009838_DEPTH_FREE(x)                       (((x) & 0x1F) << 0)
+#define   G_009838_DEPTH_FREE(x)                       (((x) >> 0) & 0x1F)
+#define   C_009838_DEPTH_FREE                          0xFFFFFFE0
+#define   S_009838_DEPTH_FLUSH(x)                      (((x) & 0x3F) << 5)
+#define   G_009838_DEPTH_FLUSH(x)                      (((x) >> 5) & 0x3F)
+#define   C_009838_DEPTH_FLUSH                         0xFFFFF81F
+#define   S_009838_FORCE_SUMMARIZE(x)                  (((x) & 0xF) << 11)
+#define   G_009838_FORCE_SUMMARIZE(x)                  (((x) >> 11) & 0xF)
+#define   C_009838_FORCE_SUMMARIZE                     0xFFFF87FF
+#define   S_009838_DEPTH_PENDING_FREE(x)               (((x) & 0x1F) << 15)
+#define   G_009838_DEPTH_PENDING_FREE(x)               (((x) >> 15) & 0x1F)
+#define   C_009838_DEPTH_PENDING_FREE                  0xFFF07FFF
+#define   S_009838_DEPTH_CACHELINE_FREE(x)             (((x) & 0x1F) << 20)
+#define   G_009838_DEPTH_CACHELINE_FREE(x)             (((x) >> 20) & 0x1F)
+#define   C_009838_DEPTH_CACHELINE_FREE                0xFE0FFFFF
+#define   S_009838_EARLY_Z_PANIC_DISABLE(x)            (((x) & 0x1) << 25)
+#define   G_009838_EARLY_Z_PANIC_DISABLE(x)            (((x) >> 25) & 0x1)
+#define   C_009838_EARLY_Z_PANIC_DISABLE               0xFDFFFFFF
+#define   S_009838_LATE_Z_PANIC_DISABLE(x)             (((x) & 0x1) << 26)
+#define   G_009838_LATE_Z_PANIC_DISABLE(x)             (((x) >> 26) & 0x1)
+#define   C_009838_LATE_Z_PANIC_DISABLE                0xFBFFFFFF
+#define   S_009838_RE_Z_PANIC_DISABLE(x)               (((x) & 0x1) << 27)
+#define   G_009838_RE_Z_PANIC_DISABLE(x)               (((x) >> 27) & 0x1)
+#define   C_009838_RE_Z_PANIC_DISABLE                  0xF7FFFFFF
+#define   S_009838_DB_EXTRA_DEBUG(x)                   (((x) & 0xF) << 28)
+#define   G_009838_DB_EXTRA_DEBUG(x)                   (((x) >> 28) & 0xF)
+#define   C_009838_DB_EXTRA_DEBUG                      0x0FFFFFFF
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL             0x028030
+#define   S_028030_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028030_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028030_TL_X                                0xFFFF8000
+#define   S_028030_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028030_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028030_TL_Y                                0x8000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR             0x028034
+#define   S_028034_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028034_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028034_BR_X                                0xFFFF8000
+#define   S_028034_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028034_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028034_BR_Y                                0x8000FFFF
+#define R_028200_PA_SC_WINDOW_OFFSET                 0x028200
+#define   S_028200_WINDOW_X_OFFSET(x)                  (((x) & 0x7FFF) << 0)
+#define   G_028200_WINDOW_X_OFFSET(x)                  (((x) >> 0) & 0x7FFF)
+#define   C_028200_WINDOW_X_OFFSET                     0xFFFF8000
+#define   S_028200_WINDOW_Y_OFFSET(x)                  (((x) & 0x7FFF) << 16)
+#define   G_028200_WINDOW_Y_OFFSET(x)                  (((x) >> 16) & 0x7FFF)
+#define   C_028200_WINDOW_Y_OFFSET                     0x8000FFFF
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL             0x028204
+#define   S_028204_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028204_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028204_TL_X                                0xFFFFC000
+#define   S_028204_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028204_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028204_TL_Y                                0xC000FFFF
+#define   S_028204_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028204_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028204_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR             0x028208
+#define   S_028208_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028208_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028208_BR_X                                0xFFFFC000
+#define   S_028208_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028208_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028208_BR_Y                                0xC000FFFF
+#define R_02820C_PA_SC_CLIPRECT_RULE                 0x02820C
+#define   S_02820C_CLIP_RULE(x)                        (((x) & 0xFFFF) << 0)
+#define   G_02820C_CLIP_RULE(x)                        (((x) >> 0) & 0xFFFF)
+#define   C_02820C_CLIP_RULE                           0xFFFF0000
+#define R_028210_PA_SC_CLIPRECT_0_TL                 0x028210
+#define   S_028210_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028210_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028210_TL_X                                0xFFFFC000
+#define   S_028210_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028210_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028210_TL_Y                                0xC000FFFF
+#define R_028214_PA_SC_CLIPRECT_0_BR                 0x028214
+#define   S_028214_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028214_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028214_BR_X                                0xFFFFC000
+#define   S_028214_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028214_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028214_BR_Y                                0xC000FFFF
+#define R_028218_PA_SC_CLIPRECT_1_TL                 0x028218
+#define R_02821C_PA_SC_CLIPRECT_1_BR                 0x02821C
+#define R_028220_PA_SC_CLIPRECT_2_TL                 0x028220
+#define R_028224_PA_SC_CLIPRECT_2_BR                 0x028224
+#define R_028228_PA_SC_CLIPRECT_3_TL                 0x028228
+#define R_02822C_PA_SC_CLIPRECT_3_BR                 0x02822C
+#define R_028230_PA_SC_EDGERULE                      0x028230
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028240_TL_X                                0xFFFFC000
+#define   S_028240_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028240_TL_Y                                0xC000FFFF
+#define   S_028240_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028240_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028240_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR            0x028244
+#define   S_028244_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028244_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028244_BR_X                                0xFFFFC000
+#define   S_028244_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028244_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028244_BR_Y                                0xC000FFFF
+#define R_0282D0_PA_SC_VPORT_ZMIN_0                  0x0282D0
+#define   S_0282D0_VPORT_ZMIN(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_0282D0_VPORT_ZMIN(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0282D0_VPORT_ZMIN                          0x00000000
+#define R_0282D4_PA_SC_VPORT_ZMAX_0                  0x0282D4
+#define   S_0282D4_VPORT_ZMAX(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_0282D4_VPORT_ZMAX(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0282D4_VPORT_ZMAX                          0x00000000
+#define R_028350_SX_MISC                             0x028350
+#define   S_028350_MULTIPASS(x)                        (((x) & 0x1) << 0)
+#define   G_028350_MULTIPASS(x)                        (((x) >> 0) & 0x1)
+#define   C_028350_MULTIPASS                           0xFFFFFFFE
+#define R_028380_SQ_VTX_SEMANTIC_0                   0x028380
+#define   S_028380_SEMANTIC_ID(x)                      (((x) & 0xFF) << 0)
+#define   G_028380_SEMANTIC_ID(x)                      (((x) >> 0) & 0xFF)
+#define   C_028380_SEMANTIC_ID                         0xFFFFFF00
+#define R_028384_SQ_VTX_SEMANTIC_1                   0x028384
+#define R_028388_SQ_VTX_SEMANTIC_2                   0x028388
+#define R_02838C_SQ_VTX_SEMANTIC_3                   0x02838C
+#define R_028390_SQ_VTX_SEMANTIC_4                   0x028390
+#define R_028394_SQ_VTX_SEMANTIC_5                   0x028394
+#define R_028398_SQ_VTX_SEMANTIC_6                   0x028398
+#define R_02839C_SQ_VTX_SEMANTIC_7                   0x02839C
+#define R_0283A0_SQ_VTX_SEMANTIC_8                   0x0283A0
+#define R_0283A4_SQ_VTX_SEMANTIC_9                   0x0283A4
+#define R_0283A8_SQ_VTX_SEMANTIC_10                  0x0283A8
+#define R_0283AC_SQ_VTX_SEMANTIC_11                  0x0283AC
+#define R_0283B0_SQ_VTX_SEMANTIC_12                  0x0283B0
+#define R_0283B4_SQ_VTX_SEMANTIC_13                  0x0283B4
+#define R_0283B8_SQ_VTX_SEMANTIC_14                  0x0283B8
+#define R_0283BC_SQ_VTX_SEMANTIC_15                  0x0283BC
+#define R_0283C0_SQ_VTX_SEMANTIC_16                  0x0283C0
+#define R_0283C4_SQ_VTX_SEMANTIC_17                  0x0283C4
+#define R_0283C8_SQ_VTX_SEMANTIC_18                  0x0283C8
+#define R_0283CC_SQ_VTX_SEMANTIC_19                  0x0283CC
+#define R_0283D0_SQ_VTX_SEMANTIC_20                  0x0283D0
+#define R_0283D4_SQ_VTX_SEMANTIC_21                  0x0283D4
+#define R_0283D8_SQ_VTX_SEMANTIC_22                  0x0283D8
+#define R_0283DC_SQ_VTX_SEMANTIC_23                  0x0283DC
+#define R_0283E0_SQ_VTX_SEMANTIC_24                  0x0283E0
+#define R_0283E4_SQ_VTX_SEMANTIC_25                  0x0283E4
+#define R_0283E8_SQ_VTX_SEMANTIC_26                  0x0283E8
+#define R_0283EC_SQ_VTX_SEMANTIC_27                  0x0283EC
+#define R_0283F0_SQ_VTX_SEMANTIC_28                  0x0283F0
+#define R_0283F4_SQ_VTX_SEMANTIC_29                  0x0283F4
+#define R_0283F8_SQ_VTX_SEMANTIC_30                  0x0283F8
+#define R_0283FC_SQ_VTX_SEMANTIC_31                  0x0283FC
+#define R_028400_VGT_MAX_VTX_INDX                    0x028400
+#define   S_028400_MAX_INDX(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028400_MAX_INDX(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028400_MAX_INDX                            0x00000000
+#define R_028404_VGT_MIN_VTX_INDX                    0x028404
+#define   S_028404_MIN_INDX(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028404_MIN_INDX(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028404_MIN_INDX                            0x00000000
+#define R_028408_VGT_INDX_OFFSET                     0x028408
+#define   S_028408_INDX_OFFSET(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028408_INDX_OFFSET(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028408_INDX_OFFSET                         0x00000000
+#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX        0x02840C
+#define   S_02840C_RESET_INDX(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_02840C_RESET_INDX(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02840C_RESET_INDX                          0x00000000
+#define R_028410_SX_ALPHA_TEST_CONTROL               0x028410
+#define   S_028410_ALPHA_FUNC(x)                       (((x) & 0x7) << 0)
+#define   G_028410_ALPHA_FUNC(x)                       (((x) >> 0) & 0x7)
+#define   C_028410_ALPHA_FUNC                          0xFFFFFFF8
+#define   S_028410_ALPHA_TEST_ENABLE(x)                (((x) & 0x1) << 3)
+#define   G_028410_ALPHA_TEST_ENABLE(x)                (((x) >> 3) & 0x1)
+#define   C_028410_ALPHA_TEST_ENABLE                   0xFFFFFFF7
+#define   S_028410_ALPHA_TEST_BYPASS(x)                (((x) & 0x1) << 8)
+#define   G_028410_ALPHA_TEST_BYPASS(x)                (((x) >> 8) & 0x1)
+#define   C_028410_ALPHA_TEST_BYPASS                   0xFFFFFEFF
+#define R_028414_CB_BLEND_RED                        0x028414
+#define   S_028414_BLEND_RED(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028414_BLEND_RED(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028414_BLEND_RED                           0x00000000
+#define R_028418_CB_BLEND_GREEN                      0x028418
+#define   S_028418_BLEND_GREEN(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028418_BLEND_GREEN(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028418_BLEND_GREEN                         0x00000000
+#define R_02841C_CB_BLEND_BLUE                       0x02841C
+#define   S_02841C_BLEND_BLUE(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_02841C_BLEND_BLUE(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02841C_BLEND_BLUE                          0x00000000
+#define R_028420_CB_BLEND_ALPHA                      0x028420
+#define   S_028420_BLEND_ALPHA(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028420_BLEND_ALPHA(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028420_BLEND_ALPHA                         0x00000000
+#define R_028438_SX_ALPHA_REF                        0x028438
+#define   S_028438_ALPHA_REF(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028438_ALPHA_REF(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028438_ALPHA_REF                           0x00000000
+#define R_0286C8_SPI_THREAD_GROUPING                 0x0286C8
+#define   S_0286C8_PS_GROUPING(x)                      (((x) & 0x1F) << 0)
+#define   G_0286C8_PS_GROUPING(x)                      (((x) >> 0) & 0x1F)
+#define   C_0286C8_PS_GROUPING                         0xFFFFFFE0
+#define   S_0286C8_VS_GROUPING(x)                      (((x) & 0x1F) << 8)
+#define   G_0286C8_VS_GROUPING(x)                      (((x) >> 8) & 0x1F)
+#define   C_0286C8_VS_GROUPING                         0xFFFFE0FF
+#define   S_0286C8_GS_GROUPING(x)                      (((x) & 0x1F) << 16)
+#define   G_0286C8_GS_GROUPING(x)                      (((x) >> 16) & 0x1F)
+#define   C_0286C8_GS_GROUPING                         0xFFE0FFFF
+#define   S_0286C8_ES_GROUPING(x)                      (((x) & 0x1F) << 24)
+#define   G_0286C8_ES_GROUPING(x)                      (((x) >> 24) & 0x1F)
+#define   C_0286C8_ES_GROUPING                         0xE0FFFFFF
+#define R_0286D8_SPI_INPUT_Z                         0x0286D8
+#define   S_0286D8_PROVIDE_Z_TO_SPI(x)                 (((x) & 0x1) << 0)
+#define   G_0286D8_PROVIDE_Z_TO_SPI(x)                 (((x) >> 0) & 0x1)
+#define   C_0286D8_PROVIDE_Z_TO_SPI                    0xFFFFFFFE
+#define R_0286DC_SPI_FOG_CNTL                        0x0286DC
+#define   S_0286DC_PASS_FOG_THROUGH_PS(x)              (((x) & 0x1) << 0)
+#define   G_0286DC_PASS_FOG_THROUGH_PS(x)              (((x) >> 0) & 0x1)
+#define   C_0286DC_PASS_FOG_THROUGH_PS                 0xFFFFFFFE
+#define   S_0286DC_PIXEL_FOG_FUNC(x)                   (((x) & 0x3) << 1)
+#define   G_0286DC_PIXEL_FOG_FUNC(x)                   (((x) >> 1) & 0x3)
+#define   C_0286DC_PIXEL_FOG_FUNC                      0xFFFFFFF9
+#define   S_0286DC_PIXEL_FOG_SRC_SEL(x)                (((x) & 0x1) << 3)
+#define   G_0286DC_PIXEL_FOG_SRC_SEL(x)                (((x) >> 3) & 0x1)
+#define   C_0286DC_PIXEL_FOG_SRC_SEL                   0xFFFFFFF7
+#define   S_0286DC_VS_FOG_CLAMP_DISABLE(x)             (((x) & 0x1) << 4)
+#define   G_0286DC_VS_FOG_CLAMP_DISABLE(x)             (((x) >> 4) & 0x1)
+#define   C_0286DC_VS_FOG_CLAMP_DISABLE                0xFFFFFFEF
+#define R_0286E0_SPI_FOG_FUNC_SCALE                  0x0286E0
+#define   S_0286E0_VALUE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_0286E0_VALUE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0286E0_VALUE                               0x00000000
+#define R_0286E4_SPI_FOG_FUNC_BIAS                   0x0286E4
+#define   S_0286E4_VALUE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_0286E4_VALUE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0286E4_VALUE                               0x00000000
+#define R_0287A0_CB_SHADER_CONTROL                   0x0287A0
+#define   S_0287A0_RT0_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_0287A0_RT0_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_0287A0_RT0_ENABLE                          0xFFFFFFFE
+#define   S_0287A0_RT1_ENABLE(x)                       (((x) & 0x1) << 1)
+#define   G_0287A0_RT1_ENABLE(x)                       (((x) >> 1) & 0x1)
+#define   C_0287A0_RT1_ENABLE                          0xFFFFFFFD
+#define   S_0287A0_RT2_ENABLE(x)                       (((x) & 0x1) << 2)
+#define   G_0287A0_RT2_ENABLE(x)                       (((x) >> 2) & 0x1)
+#define   C_0287A0_RT2_ENABLE                          0xFFFFFFFB
+#define   S_0287A0_RT3_ENABLE(x)                       (((x) & 0x1) << 3)
+#define   G_0287A0_RT3_ENABLE(x)                       (((x) >> 3) & 0x1)
+#define   C_0287A0_RT3_ENABLE                          0xFFFFFFF7
+#define   S_0287A0_RT4_ENABLE(x)                       (((x) & 0x1) << 4)
+#define   G_0287A0_RT4_ENABLE(x)                       (((x) >> 4) & 0x1)
+#define   C_0287A0_RT4_ENABLE                          0xFFFFFFEF
+#define   S_0287A0_RT5_ENABLE(x)                       (((x) & 0x1) << 5)
+#define   G_0287A0_RT5_ENABLE(x)                       (((x) >> 5) & 0x1)
+#define   C_0287A0_RT5_ENABLE                          0xFFFFFFDF
+#define   S_0287A0_RT6_ENABLE(x)                       (((x) & 0x1) << 6)
+#define   G_0287A0_RT6_ENABLE(x)                       (((x) >> 6) & 0x1)
+#define   C_0287A0_RT6_ENABLE                          0xFFFFFFBF
+#define   S_0287A0_RT7_ENABLE(x)                       (((x) & 0x1) << 7)
+#define   G_0287A0_RT7_ENABLE(x)                       (((x) >> 7) & 0x1)
+#define   C_0287A0_RT7_ENABLE                          0xFFFFFF7F
+#define R_028894_SQ_PGM_START_FS                     0x028894
+#define   S_028894_PGM_START(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028894_PGM_START(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028894_PGM_START                           0x00000000
+#define R_0288A4_SQ_PGM_RESOURCES_FS                 0x0288A4
+#define   S_0288A4_NUM_GPRS(x)                         (((x) & 0xFF) << 0)
+#define   G_0288A4_NUM_GPRS(x)                         (((x) >> 0) & 0xFF)
+#define   C_0288A4_NUM_GPRS                            0xFFFFFF00
+#define   S_0288A4_STACK_SIZE(x)                       (((x) & 0xFF) << 8)
+#define   G_0288A4_STACK_SIZE(x)                       (((x) >> 8) & 0xFF)
+#define   C_0288A4_STACK_SIZE                          0xFFFF00FF
+#define   S_0288A4_DX10_CLAMP(x)                       (((x) & 0x1) << 21)
+#define   G_0288A4_DX10_CLAMP(x)                       (((x) >> 21) & 0x1)
+#define   C_0288A4_DX10_CLAMP                          0xFFDFFFFF
+#define R_0288A8_SQ_ESGS_RING_ITEMSIZE               0x0288A8
+#define   S_0288A8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288A8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288A8_ITEMSIZE                            0xFFFF8000
+#define R_0288AC_SQ_GSVS_RING_ITEMSIZE               0x0288AC
+#define   S_0288AC_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288AC_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288AC_ITEMSIZE                            0xFFFF8000
+#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE              0x0288B0
+#define   S_0288B0_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288B0_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288B0_ITEMSIZE                            0xFFFF8000
+#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE              0x0288B4
+#define   S_0288B4_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288B4_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288B4_ITEMSIZE                            0xFFFF8000
+#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE              0x0288B8
+#define   S_0288B8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288B8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288B8_ITEMSIZE                            0xFFFF8000
+#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE              0x0288BC
+#define   S_0288BC_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288BC_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288BC_ITEMSIZE                            0xFFFF8000
+#define R_0288C0_SQ_FBUF_RING_ITEMSIZE               0x0288C0
+#define   S_0288C0_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288C0_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288C0_ITEMSIZE                            0xFFFF8000
+#define R_0288C4_SQ_REDUC_RING_ITEMSIZE              0x0288C4
+#define   S_0288C4_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288C4_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288C4_ITEMSIZE                            0xFFFF8000
+#define R_0288C8_SQ_GS_VERT_ITEMSIZE                 0x0288C8
+#define   S_0288C8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288C8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288C8_ITEMSIZE                            0xFFFF8000
+#define R_0288DC_SQ_PGM_CF_OFFSET_FS                 0x0288DC
+#define   S_0288DC_PGM_CF_OFFSET(x)                    (((x) & 0xFFFFF) << 0)
+#define   G_0288DC_PGM_CF_OFFSET(x)                    (((x) >> 0) & 0xFFFFF)
+#define   C_0288DC_PGM_CF_OFFSET                       0xFFF00000
+#define R_028A10_VGT_OUTPUT_PATH_CNTL                0x028A10
+#define   S_028A10_PATH_SELECT(x)                      (((x) & 0x3) << 0)
+#define   G_028A10_PATH_SELECT(x)                      (((x) >> 0) & 0x3)
+#define   C_028A10_PATH_SELECT                         0xFFFFFFFC
+#define R_028A14_VGT_HOS_CNTL                        0x028A14
+#define   S_028A14_TESS_MODE(x)                        (((x) & 0x3) << 0)
+#define   G_028A14_TESS_MODE(x)                        (((x) >> 0) & 0x3)
+#define   C_028A14_TESS_MODE                           0xFFFFFFFC
+#define R_028A18_VGT_HOS_MAX_TESS_LEVEL              0x028A18
+#define   S_028A18_MAX_TESS(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028A18_MAX_TESS(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028A18_MAX_TESS                            0x00000000
+#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL              0x028A1C
+#define   S_028A1C_MIN_TESS(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028A1C_MIN_TESS(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028A1C_MIN_TESS                            0x00000000
+#define R_028A20_VGT_HOS_REUSE_DEPTH                 0x028A20
+#define   S_028A20_REUSE_DEPTH(x)                      (((x) & 0xFF) << 0)
+#define   G_028A20_REUSE_DEPTH(x)                      (((x) >> 0) & 0xFF)
+#define   C_028A20_REUSE_DEPTH                         0xFFFFFF00
+#define R_028A24_VGT_GROUP_PRIM_TYPE                 0x028A24
+#define   S_028A24_PRIM_TYPE(x)                        (((x) & 0x1F) << 0)
+#define   G_028A24_PRIM_TYPE(x)                        (((x) >> 0) & 0x1F)
+#define   C_028A24_PRIM_TYPE                           0xFFFFFFE0
+#define   S_028A24_RETAIN_ORDER(x)                     (((x) & 0x1) << 14)
+#define   G_028A24_RETAIN_ORDER(x)                     (((x) >> 14) & 0x1)
+#define   C_028A24_RETAIN_ORDER                        0xFFFFBFFF
+#define   S_028A24_RETAIN_QUADS(x)                     (((x) & 0x1) << 15)
+#define   G_028A24_RETAIN_QUADS(x)                     (((x) >> 15) & 0x1)
+#define   C_028A24_RETAIN_QUADS                        0xFFFF7FFF
+#define   S_028A24_PRIM_ORDER(x)                       (((x) & 0x7) << 16)
+#define   G_028A24_PRIM_ORDER(x)                       (((x) >> 16) & 0x7)
+#define   C_028A24_PRIM_ORDER                          0xFFF8FFFF
+#define R_028A28_VGT_GROUP_FIRST_DECR                0x028A28
+#define   S_028A28_FIRST_DECR(x)                       (((x) & 0xF) << 0)
+#define   G_028A28_FIRST_DECR(x)                       (((x) >> 0) & 0xF)
+#define   C_028A28_FIRST_DECR                          0xFFFFFFF0
+#define R_028A2C_VGT_GROUP_DECR                      0x028A2C
+#define   S_028A2C_DECR(x)                             (((x) & 0xF) << 0)
+#define   G_028A2C_DECR(x)                             (((x) >> 0) & 0xF)
+#define   C_028A2C_DECR                                0xFFFFFFF0
+#define R_028A30_VGT_GROUP_VECT_0_CNTL               0x028A30
+#define   S_028A30_COMP_X_EN(x)                        (((x) & 0x1) << 0)
+#define   G_028A30_COMP_X_EN(x)                        (((x) >> 0) & 0x1)
+#define   C_028A30_COMP_X_EN                           0xFFFFFFFE
+#define   S_028A30_COMP_Y_EN(x)                        (((x) & 0x1) << 1)
+#define   G_028A30_COMP_Y_EN(x)                        (((x) >> 1) & 0x1)
+#define   C_028A30_COMP_Y_EN                           0xFFFFFFFD
+#define   S_028A30_COMP_Z_EN(x)                        (((x) & 0x1) << 2)
+#define   G_028A30_COMP_Z_EN(x)                        (((x) >> 2) & 0x1)
+#define   C_028A30_COMP_Z_EN                           0xFFFFFFFB
+#define   S_028A30_COMP_W_EN(x)                        (((x) & 0x1) << 3)
+#define   G_028A30_COMP_W_EN(x)                        (((x) >> 3) & 0x1)
+#define   C_028A30_COMP_W_EN                           0xFFFFFFF7
+#define   S_028A30_STRIDE(x)                           (((x) & 0xFF) << 8)
+#define   G_028A30_STRIDE(x)                           (((x) >> 8) & 0xFF)
+#define   C_028A30_STRIDE                              0xFFFF00FF
+#define   S_028A30_SHIFT(x)                            (((x) & 0xFF) << 16)
+#define   G_028A30_SHIFT(x)                            (((x) >> 16) & 0xFF)
+#define   C_028A30_SHIFT                               0xFF00FFFF
+#define R_028A34_VGT_GROUP_VECT_1_CNTL               0x028A34
+#define   S_028A34_COMP_X_EN(x)                        (((x) & 0x1) << 0)
+#define   G_028A34_COMP_X_EN(x)                        (((x) >> 0) & 0x1)
+#define   C_028A34_COMP_X_EN                           0xFFFFFFFE
+#define   S_028A34_COMP_Y_EN(x)                        (((x) & 0x1) << 1)
+#define   G_028A34_COMP_Y_EN(x)                        (((x) >> 1) & 0x1)
+#define   C_028A34_COMP_Y_EN                           0xFFFFFFFD
+#define   S_028A34_COMP_Z_EN(x)                        (((x) & 0x1) << 2)
+#define   G_028A34_COMP_Z_EN(x)                        (((x) >> 2) & 0x1)
+#define   C_028A34_COMP_Z_EN                           0xFFFFFFFB
+#define   S_028A34_COMP_W_EN(x)                        (((x) & 0x1) << 3)
+#define   G_028A34_COMP_W_EN(x)                        (((x) >> 3) & 0x1)
+#define   C_028A34_COMP_W_EN                           0xFFFFFFF7
+#define   S_028A34_STRIDE(x)                           (((x) & 0xFF) << 8)
+#define   G_028A34_STRIDE(x)                           (((x) >> 8) & 0xFF)
+#define   C_028A34_STRIDE                              0xFFFF00FF
+#define   S_028A34_SHIFT(x)                            (((x) & 0xFF) << 16)
+#define   G_028A34_SHIFT(x)                            (((x) >> 16) & 0xFF)
+#define   C_028A34_SHIFT                               0xFF00FFFF
+#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL           0x028A38
+#define   S_028A38_X_CONV(x)                           (((x) & 0xF) << 0)
+#define   G_028A38_X_CONV(x)                           (((x) >> 0) & 0xF)
+#define   C_028A38_X_CONV                              0xFFFFFFF0
+#define   S_028A38_X_OFFSET(x)                         (((x) & 0xF) << 4)
+#define   G_028A38_X_OFFSET(x)                         (((x) >> 4) & 0xF)
+#define   C_028A38_X_OFFSET                            0xFFFFFF0F
+#define   S_028A38_Y_CONV(x)                           (((x) & 0xF) << 8)
+#define   G_028A38_Y_CONV(x)                           (((x) >> 8) & 0xF)
+#define   C_028A38_Y_CONV                              0xFFFFF0FF
+#define   S_028A38_Y_OFFSET(x)                         (((x) & 0xF) << 12)
+#define   G_028A38_Y_OFFSET(x)                         (((x) >> 12) & 0xF)
+#define   C_028A38_Y_OFFSET                            0xFFFF0FFF
+#define   S_028A38_Z_CONV(x)                           (((x) & 0xF) << 16)
+#define   G_028A38_Z_CONV(x)                           (((x) >> 16) & 0xF)
+#define   C_028A38_Z_CONV                              0xFFF0FFFF
+#define   S_028A38_Z_OFFSET(x)                         (((x) & 0xF) << 20)
+#define   G_028A38_Z_OFFSET(x)                         (((x) >> 20) & 0xF)
+#define   C_028A38_Z_OFFSET                            0xFF0FFFFF
+#define   S_028A38_W_CONV(x)                           (((x) & 0xF) << 24)
+#define   G_028A38_W_CONV(x)                           (((x) >> 24) & 0xF)
+#define   C_028A38_W_CONV                              0xF0FFFFFF
+#define   S_028A38_W_OFFSET(x)                         (((x) & 0xF) << 28)
+#define   G_028A38_W_OFFSET(x)                         (((x) >> 28) & 0xF)
+#define   C_028A38_W_OFFSET                            0x0FFFFFFF
+#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL           0x028A3C
+#define   S_028A3C_X_CONV(x)                           (((x) & 0xF) << 0)
+#define   G_028A3C_X_CONV(x)                           (((x) >> 0) & 0xF)
+#define   C_028A3C_X_CONV                              0xFFFFFFF0
+#define   S_028A3C_X_OFFSET(x)                         (((x) & 0xF) << 4)
+#define   G_028A3C_X_OFFSET(x)                         (((x) >> 4) & 0xF)
+#define   C_028A3C_X_OFFSET                            0xFFFFFF0F
+#define   S_028A3C_Y_CONV(x)                           (((x) & 0xF) << 8)
+#define   G_028A3C_Y_CONV(x)                           (((x) >> 8) & 0xF)
+#define   C_028A3C_Y_CONV                              0xFFFFF0FF
+#define   S_028A3C_Y_OFFSET(x)                         (((x) & 0xF) << 12)
+#define   G_028A3C_Y_OFFSET(x)                         (((x) >> 12) & 0xF)
+#define   C_028A3C_Y_OFFSET                            0xFFFF0FFF
+#define   S_028A3C_Z_CONV(x)                           (((x) & 0xF) << 16)
+#define   G_028A3C_Z_CONV(x)                           (((x) >> 16) & 0xF)
+#define   C_028A3C_Z_CONV                              0xFFF0FFFF
+#define   S_028A3C_Z_OFFSET(x)                         (((x) & 0xF) << 20)
+#define   G_028A3C_Z_OFFSET(x)                         (((x) >> 20) & 0xF)
+#define   C_028A3C_Z_OFFSET                            0xFF0FFFFF
+#define   S_028A3C_W_CONV(x)                           (((x) & 0xF) << 24)
+#define   G_028A3C_W_CONV(x)                           (((x) >> 24) & 0xF)
+#define   C_028A3C_W_CONV                              0xF0FFFFFF
+#define   S_028A3C_W_OFFSET(x)                         (((x) & 0xF) << 28)
+#define   G_028A3C_W_OFFSET(x)                         (((x) >> 28) & 0xF)
+#define   C_028A3C_W_OFFSET                            0x0FFFFFFF
+#define R_028A40_VGT_GS_MODE                         0x028A40
+#define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
+#define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
+#define   C_028A40_MODE                                0xFFFFFFFC
+#define   S_028A40_ES_PASSTHRU(x)                      (((x) & 0x1) << 2)
+#define   G_028A40_ES_PASSTHRU(x)                      (((x) >> 2) & 0x1)
+#define   C_028A40_ES_PASSTHRU                         0xFFFFFFFB
+#define   S_028A40_CUT_MODE(x)                         (((x) & 0x3) << 3)
+#define   G_028A40_CUT_MODE(x)                         (((x) >> 3) & 0x3)
+#define   C_028A40_CUT_MODE                            0xFFFFFFE7
+#define R_028A4C_PA_SC_MODE_CNTL                     0x028A4C
+#define   S_028A4C_MSAA_ENABLE(x)                      (((x) & 0x1) << 0)
+#define   G_028A4C_MSAA_ENABLE(x)                      (((x) >> 0) & 0x1)
+#define   C_028A4C_MSAA_ENABLE                         0xFFFFFFFE
+#define   S_028A4C_CLIPRECT_ENABLE(x)                  (((x) & 0x1) << 1)
+#define   G_028A4C_CLIPRECT_ENABLE(x)                  (((x) >> 1) & 0x1)
+#define   C_028A4C_CLIPRECT_ENABLE                     0xFFFFFFFD
+#define   S_028A4C_LINE_STIPPLE_ENABLE(x)              (((x) & 0x1) << 2)
+#define   G_028A4C_LINE_STIPPLE_ENABLE(x)              (((x) >> 2) & 0x1)
+#define   C_028A4C_LINE_STIPPLE_ENABLE                 0xFFFFFFFB
+#define   S_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x)     (((x) & 0x1) << 3)
+#define   G_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x)     (((x) >> 3) & 0x1)
+#define   C_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB        0xFFFFFFF7
+#define   S_028A4C_WALK_ORDER_ENABLE(x)                (((x) & 0x1) << 4)
+#define   G_028A4C_WALK_ORDER_ENABLE(x)                (((x) >> 4) & 0x1)
+#define   C_028A4C_WALK_ORDER_ENABLE                   0xFFFFFFEF
+#define   S_028A4C_HALVE_DETAIL_SAMPLE_PERF(x)         (((x) & 0x1) << 5)
+#define   G_028A4C_HALVE_DETAIL_SAMPLE_PERF(x)         (((x) >> 5) & 0x1)
+#define   C_028A4C_HALVE_DETAIL_SAMPLE_PERF            0xFFFFFFDF
+#define   S_028A4C_WALK_SIZE(x)                        (((x) & 0x1) << 6)
+#define   G_028A4C_WALK_SIZE(x)                        (((x) >> 6) & 0x1)
+#define   C_028A4C_WALK_SIZE                           0xFFFFFFBF
+#define   S_028A4C_WALK_ALIGNMENT(x)                   (((x) & 0x1) << 7)
+#define   G_028A4C_WALK_ALIGNMENT(x)                   (((x) >> 7) & 0x1)
+#define   C_028A4C_WALK_ALIGNMENT                      0xFFFFFF7F
+#define   S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x)         (((x) & 0x1) << 8)
+#define   G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x)         (((x) >> 8) & 0x1)
+#define   C_028A4C_WALK_ALIGN8_PRIM_FITS_ST            0xFFFFFEFF
+#define   S_028A4C_TILE_COVER_NO_SCISSOR(x)            (((x) & 0x1) << 9)
+#define   G_028A4C_TILE_COVER_NO_SCISSOR(x)            (((x) >> 9) & 0x1)
+#define   C_028A4C_TILE_COVER_NO_SCISSOR               0xFFFFFDFF
+#define   S_028A4C_KILL_PIX_POST_HI_Z(x)               (((x) & 0x1) << 10)
+#define   G_028A4C_KILL_PIX_POST_HI_Z(x)               (((x) >> 10) & 0x1)
+#define   C_028A4C_KILL_PIX_POST_HI_Z                  0xFFFFFBFF
+#define   S_028A4C_KILL_PIX_POST_DETAIL_MASK(x)        (((x) & 0x1) << 11)
+#define   G_028A4C_KILL_PIX_POST_DETAIL_MASK(x)        (((x) >> 11) & 0x1)
+#define   C_028A4C_KILL_PIX_POST_DETAIL_MASK           0xFFFFF7FF
+#define   S_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x)      (((x) & 0x1) << 12)
+#define   G_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x)      (((x) >> 12) & 0x1)
+#define   C_028A4C_MULTI_CHIP_SUPERTILE_ENABLE         0xFFFFEFFF
+#define   S_028A4C_TILE_COVER_DISABLE(x)               (((x) & 0x1) << 13)
+#define   G_028A4C_TILE_COVER_DISABLE(x)               (((x) >> 13) & 0x1)
+#define   C_028A4C_TILE_COVER_DISABLE                  0xFFFFDFFF
+#define   S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x)          (((x) & 0x1) << 14)
+#define   G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x)          (((x) >> 14) & 0x1)
+#define   C_028A4C_FORCE_EOV_CNTDWN_ENABLE             0xFFFFBFFF
+#define   S_028A4C_FORCE_EOV_TILE_ENABLE(x)            (((x) & 0x1) << 15)
+#define   G_028A4C_FORCE_EOV_TILE_ENABLE(x)            (((x) >> 15) & 0x1)
+#define   C_028A4C_FORCE_EOV_TILE_ENABLE               0xFFFF7FFF
+#define   S_028A4C_FORCE_EOV_REZ_ENABLE(x)             (((x) & 0x1) << 16)
+#define   G_028A4C_FORCE_EOV_REZ_ENABLE(x)             (((x) >> 16) & 0x1)
+#define   C_028A4C_FORCE_EOV_REZ_ENABLE                0xFFFEFFFF
+#define   S_028A4C_PS_ITER_SAMPLE(x)                   (((x) & 0x1) << 17)
+#define   G_028A4C_PS_ITER_SAMPLE(x)                   (((x) >> 17) & 0x1)
+#define   C_028A4C_PS_ITER_SAMPLE                      0xFFFDFFFF
+#define R_028A84_VGT_PRIMITIVEID_EN                  0x028A84
+#define   S_028A84_PRIMITIVEID_EN(x)                   (((x) & 0x1) << 0)
+#define   G_028A84_PRIMITIVEID_EN(x)                   (((x) >> 0) & 0x1)
+#define   C_028A84_PRIMITIVEID_EN                      0xFFFFFFFE
+#define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN          0x028A94
+#define   S_028A94_RESET_EN(x)                         (((x) & 0x1) << 0)
+#define   G_028A94_RESET_EN(x)                         (((x) >> 0) & 0x1)
+#define   C_028A94_RESET_EN                            0xFFFFFFFE
+#define R_028AA0_VGT_INSTANCE_STEP_RATE_0            0x028AA0
+#define   S_028AA0_STEP_RATE(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028AA0_STEP_RATE(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028AA0_STEP_RATE                           0x00000000
+#define R_028AA4_VGT_INSTANCE_STEP_RATE_1            0x028AA4
+#define   S_028AA4_STEP_RATE(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028AA4_STEP_RATE(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028AA4_STEP_RATE                           0x00000000
+#define R_028AB0_VGT_STRMOUT_EN                      0x028AB0
+#define   S_028AB0_STREAMOUT(x)                        (((x) & 0x1) << 0)
+#define   G_028AB0_STREAMOUT(x)                        (((x) >> 0) & 0x1)
+#define   C_028AB0_STREAMOUT                           0xFFFFFFFE
+#define R_028AB4_VGT_REUSE_OFF                       0x028AB4
+#define   S_028AB4_REUSE_OFF(x)                        (((x) & 0x1) << 0)
+#define   G_028AB4_REUSE_OFF(x)                        (((x) >> 0) & 0x1)
+#define   C_028AB4_REUSE_OFF                           0xFFFFFFFE
+#define R_028AB8_VGT_VTX_CNT_EN                      0x028AB8
+#define   S_028AB8_VTX_CNT_EN(x)                       (((x) & 0x1) << 0)
+#define   G_028AB8_VTX_CNT_EN(x)                       (((x) >> 0) & 0x1)
+#define   C_028AB8_VTX_CNT_EN                          0xFFFFFFFE
+#define R_028B20_VGT_STRMOUT_BUFFER_EN               0x028B20
+#define   S_028B20_BUFFER_0_EN(x)                      (((x) & 0x1) << 0)
+#define   G_028B20_BUFFER_0_EN(x)                      (((x) >> 0) & 0x1)
+#define   C_028B20_BUFFER_0_EN                         0xFFFFFFFE
+#define   S_028B20_BUFFER_1_EN(x)                      (((x) & 0x1) << 1)
+#define   G_028B20_BUFFER_1_EN(x)                      (((x) >> 1) & 0x1)
+#define   C_028B20_BUFFER_1_EN                         0xFFFFFFFD
+#define   S_028B20_BUFFER_2_EN(x)                      (((x) & 0x1) << 2)
+#define   G_028B20_BUFFER_2_EN(x)                      (((x) >> 2) & 0x1)
+#define   C_028B20_BUFFER_2_EN                         0xFFFFFFFB
+#define   S_028B20_BUFFER_3_EN(x)                      (((x) & 0x1) << 3)
+#define   G_028B20_BUFFER_3_EN(x)                      (((x) >> 3) & 0x1)
+#define   C_028B20_BUFFER_3_EN                         0xFFFFFFF7
+#define R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX    0x028C20
+#define   S_028C20_S4_X(x)                             (((x) & 0xF) << 0)
+#define   G_028C20_S4_X(x)                             (((x) >> 0) & 0xF)
+#define   C_028C20_S4_X                                0xFFFFFFF0
+#define   S_028C20_S4_Y(x)                             (((x) & 0xF) << 4)
+#define   G_028C20_S4_Y(x)                             (((x) >> 4) & 0xF)
+#define   C_028C20_S4_Y                                0xFFFFFF0F
+#define   S_028C20_S5_X(x)                             (((x) & 0xF) << 8)
+#define   G_028C20_S5_X(x)                             (((x) >> 8) & 0xF)
+#define   C_028C20_S5_X                                0xFFFFF0FF
+#define   S_028C20_S5_Y(x)                             (((x) & 0xF) << 12)
+#define   G_028C20_S5_Y(x)                             (((x) >> 12) & 0xF)
+#define   C_028C20_S5_Y                                0xFFFF0FFF
+#define   S_028C20_S6_X(x)                             (((x) & 0xF) << 16)
+#define   G_028C20_S6_X(x)                             (((x) >> 16) & 0xF)
+#define   C_028C20_S6_X                                0xFFF0FFFF
+#define   S_028C20_S6_Y(x)                             (((x) & 0xF) << 20)
+#define   G_028C20_S6_Y(x)                             (((x) >> 20) & 0xF)
+#define   C_028C20_S6_Y                                0xFF0FFFFF
+#define   S_028C20_S7_X(x)                             (((x) & 0xF) << 24)
+#define   G_028C20_S7_X(x)                             (((x) >> 24) & 0xF)
+#define   C_028C20_S7_X                                0xF0FFFFFF
+#define   S_028C20_S7_Y(x)                             (((x) & 0xF) << 28)
+#define   G_028C20_S7_Y(x)                             (((x) >> 28) & 0xF)
+#define   C_028C20_S7_Y                                0x0FFFFFFF
+#define R_028C30_CB_CLRCMP_CONTROL                   0x028C30
+#define   S_028C30_CLRCMP_FCN_SRC(x)                   (((x) & 0x7) << 0)
+#define   G_028C30_CLRCMP_FCN_SRC(x)                   (((x) >> 0) & 0x7)
+#define   C_028C30_CLRCMP_FCN_SRC                      0xFFFFFFF8
+#define   S_028C30_CLRCMP_FCN_DST(x)                   (((x) & 0x7) << 8)
+#define   G_028C30_CLRCMP_FCN_DST(x)                   (((x) >> 8) & 0x7)
+#define   C_028C30_CLRCMP_FCN_DST                      0xFFFFF8FF
+#define   S_028C30_CLRCMP_FCN_SEL(x)                   (((x) & 0x3) << 24)
+#define   G_028C30_CLRCMP_FCN_SEL(x)                   (((x) >> 24) & 0x3)
+#define   C_028C30_CLRCMP_FCN_SEL                      0xFCFFFFFF
+#define R_028C34_CB_CLRCMP_SRC                       0x028C34
+#define   S_028C34_CLRCMP_SRC(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028C34_CLRCMP_SRC(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028C34_CLRCMP_SRC                          0x00000000
+#define R_028C38_CB_CLRCMP_DST                       0x028C38
+#define   S_028C38_CLRCMP_DST(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028C38_CLRCMP_DST(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028C38_CLRCMP_DST                          0x00000000
+#define R_028C3C_CB_CLRCMP_MSK                       0x028C3C
+#define   S_028C3C_CLRCMP_MSK(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028C3C_CLRCMP_MSK(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028C3C_CLRCMP_MSK                          0x00000000
+#define R_0085F0_CP_COHER_CNTL                       0x0085F0
+#define   S_0085F0_DEST_BASE_0_ENA(x)                  (((x) & 0x1) << 0)
+#define   G_0085F0_DEST_BASE_0_ENA(x)                  (((x) >> 0) & 0x1)
+#define   C_0085F0_DEST_BASE_0_ENA                     0xFFFFFFFE
+#define   S_0085F0_DEST_BASE_1_ENA(x)                  (((x) & 0x1) << 1)
+#define   G_0085F0_DEST_BASE_1_ENA(x)                  (((x) >> 1) & 0x1)
+#define   C_0085F0_DEST_BASE_1_ENA                     0xFFFFFFFD
+#define   S_0085F0_SO0_DEST_BASE_ENA(x)                (((x) & 0x1) << 2)
+#define   G_0085F0_SO0_DEST_BASE_ENA(x)                (((x) >> 2) & 0x1)
+#define   C_0085F0_SO0_DEST_BASE_ENA                   0xFFFFFFFB
+#define   S_0085F0_SO1_DEST_BASE_ENA(x)                (((x) & 0x1) << 3)
+#define   G_0085F0_SO1_DEST_BASE_ENA(x)                (((x) >> 3) & 0x1)
+#define   C_0085F0_SO1_DEST_BASE_ENA                   0xFFFFFFF7
+#define   S_0085F0_SO2_DEST_BASE_ENA(x)                (((x) & 0x1) << 4)
+#define   G_0085F0_SO2_DEST_BASE_ENA(x)                (((x) >> 4) & 0x1)
+#define   C_0085F0_SO2_DEST_BASE_ENA                   0xFFFFFFEF
+#define   S_0085F0_SO3_DEST_BASE_ENA(x)                (((x) & 0x1) << 5)
+#define   G_0085F0_SO3_DEST_BASE_ENA(x)                (((x) >> 5) & 0x1)
+#define   C_0085F0_SO3_DEST_BASE_ENA                   0xFFFFFFDF
+#define   S_0085F0_CB0_DEST_BASE_ENA(x)                (((x) & 0x1) << 6)
+#define   G_0085F0_CB0_DEST_BASE_ENA(x)                (((x) >> 6) & 0x1)
+#define   C_0085F0_CB0_DEST_BASE_ENA                   0xFFFFFFBF
+#define   S_0085F0_CB1_DEST_BASE_ENA(x)                (((x) & 0x1) << 7)
+#define   G_0085F0_CB1_DEST_BASE_ENA(x)                (((x) >> 7) & 0x1)
+#define   C_0085F0_CB1_DEST_BASE_ENA                   0xFFFFFF7F
+#define   S_0085F0_CB2_DEST_BASE_ENA(x)                (((x) & 0x1) << 8)
+#define   G_0085F0_CB2_DEST_BASE_ENA(x)                (((x) >> 8) & 0x1)
+#define   C_0085F0_CB2_DEST_BASE_ENA                   0xFFFFFEFF
+#define   S_0085F0_CB3_DEST_BASE_ENA(x)                (((x) & 0x1) << 9)
+#define   G_0085F0_CB3_DEST_BASE_ENA(x)                (((x) >> 9) & 0x1)
+#define   C_0085F0_CB3_DEST_BASE_ENA                   0xFFFFFDFF
+#define   S_0085F0_CB4_DEST_BASE_ENA(x)                (((x) & 0x1) << 10)
+#define   G_0085F0_CB4_DEST_BASE_ENA(x)                (((x) >> 10) & 0x1)
+#define   C_0085F0_CB4_DEST_BASE_ENA                   0xFFFFFBFF
+#define   S_0085F0_CB5_DEST_BASE_ENA(x)                (((x) & 0x1) << 11)
+#define   G_0085F0_CB5_DEST_BASE_ENA(x)                (((x) >> 11) & 0x1)
+#define   C_0085F0_CB5_DEST_BASE_ENA                   0xFFFFF7FF
+#define   S_0085F0_CB6_DEST_BASE_ENA(x)                (((x) & 0x1) << 12)
+#define   G_0085F0_CB6_DEST_BASE_ENA(x)                (((x) >> 12) & 0x1)
+#define   C_0085F0_CB6_DEST_BASE_ENA                   0xFFFFEFFF
+#define   S_0085F0_CB7_DEST_BASE_ENA(x)                (((x) & 0x1) << 13)
+#define   G_0085F0_CB7_DEST_BASE_ENA(x)                (((x) >> 13) & 0x1)
+#define   C_0085F0_CB7_DEST_BASE_ENA                   0xFFFFDFFF
+#define   S_0085F0_DB_DEST_BASE_ENA(x)                 (((x) & 0x1) << 14)
+#define   G_0085F0_DB_DEST_BASE_ENA(x)                 (((x) >> 14) & 0x1)
+#define   C_0085F0_DB_DEST_BASE_ENA                    0xFFFFBFFF
+#define   S_0085F0_CR_DEST_BASE_ENA(x)                 (((x) & 0x1) << 15)
+#define   G_0085F0_CR_DEST_BASE_ENA(x)                 (((x) >> 15) & 0x1)
+#define   C_0085F0_CR_DEST_BASE_ENA                    0xFFFF7FFF
+#define   S_0085F0_TC_ACTION_ENA(x)                    (((x) & 0x1) << 23)
+#define   G_0085F0_TC_ACTION_ENA(x)                    (((x) >> 23) & 0x1)
+#define   C_0085F0_TC_ACTION_ENA                       0xFF7FFFFF
+#define   S_0085F0_VC_ACTION_ENA(x)                    (((x) & 0x1) << 24)
+#define   G_0085F0_VC_ACTION_ENA(x)                    (((x) >> 24) & 0x1)
+#define   C_0085F0_VC_ACTION_ENA                       0xFEFFFFFF
+#define   S_0085F0_CB_ACTION_ENA(x)                    (((x) & 0x1) << 25)
+#define   G_0085F0_CB_ACTION_ENA(x)                    (((x) >> 25) & 0x1)
+#define   C_0085F0_CB_ACTION_ENA                       0xFDFFFFFF
+#define   S_0085F0_DB_ACTION_ENA(x)                    (((x) & 0x1) << 26)
+#define   G_0085F0_DB_ACTION_ENA(x)                    (((x) >> 26) & 0x1)
+#define   C_0085F0_DB_ACTION_ENA                       0xFBFFFFFF
+#define   S_0085F0_SH_ACTION_ENA(x)                    (((x) & 0x1) << 27)
+#define   G_0085F0_SH_ACTION_ENA(x)                    (((x) >> 27) & 0x1)
+#define   C_0085F0_SH_ACTION_ENA                       0xF7FFFFFF
+#define   S_0085F0_SMX_ACTION_ENA(x)                   (((x) & 0x1) << 28)
+#define   G_0085F0_SMX_ACTION_ENA(x)                   (((x) >> 28) & 0x1)
+#define   C_0085F0_SMX_ACTION_ENA                      0xEFFFFFFF
+#define   S_0085F0_CR0_ACTION_ENA(x)                   (((x) & 0x1) << 29)
+#define   G_0085F0_CR0_ACTION_ENA(x)                   (((x) >> 29) & 0x1)
+#define   C_0085F0_CR0_ACTION_ENA                      0xDFFFFFFF
+#define   S_0085F0_CR1_ACTION_ENA(x)                   (((x) & 0x1) << 30)
+#define   G_0085F0_CR1_ACTION_ENA(x)                   (((x) >> 30) & 0x1)
+#define   C_0085F0_CR1_ACTION_ENA                      0xBFFFFFFF
+#define   S_0085F0_CR2_ACTION_ENA(x)                   (((x) & 0x1) << 31)
+#define   G_0085F0_CR2_ACTION_ENA(x)                   (((x) >> 31) & 0x1)
+#define   C_0085F0_CR2_ACTION_ENA                      0x7FFFFFFF
+
+
+#define R_02812C_CB_CLEAR_ALPHA                      0x02812C
+#define   S_02812C_CLEAR_ALPHA(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_02812C_CLEAR_ALPHA(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02812C_CLEAR_ALPHA                         0x00000000
+#define R_028128_CB_CLEAR_BLUE                       0x028128
+#define   S_028128_CLEAR_BLUE(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028128_CLEAR_BLUE(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028128_CLEAR_BLUE                          0x00000000
+#define R_028124_CB_CLEAR_GREEN                      0x028124
+#define   S_028124_CLEAR_GREEN(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028124_CLEAR_GREEN(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028124_CLEAR_GREEN                         0x00000000
+#define R_028120_CB_CLEAR_RED                        0x028120
+#define   S_028120_CLEAR_RED(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028120_CLEAR_RED(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028120_CLEAR_RED                           0x00000000
+#define R_02842C_CB_FOG_BLUE                         0x02842C
+#define   S_02842C_FOG_BLUE(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_02842C_FOG_BLUE(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02842C_FOG_BLUE                            0x00000000
+#define R_028428_CB_FOG_GREEN                        0x028428
+#define   S_028428_FOG_GREEN(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028428_FOG_GREEN(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028428_FOG_GREEN                           0x00000000
+#define R_028424_CB_FOG_RED                          0x028424
+#define   S_028424_FOG_RED(x)                          (((x) & 0xFFFFFFFF) << 0)
+#define   G_028424_FOG_RED(x)                          (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028424_FOG_RED                             0x00000000
+#define R_03C000_SQ_TEX_SAMPLER_WORD0_0              0x03C000
+#define   S_03C000_CLAMP_X(x)                          (((x) & 0x7) << 0)
+#define   G_03C000_CLAMP_X(x)                          (((x) >> 0) & 0x7)
+#define   C_03C000_CLAMP_X                             0xFFFFFFF8
+#define   S_03C000_CLAMP_Y(x)                          (((x) & 0x7) << 3)
+#define   G_03C000_CLAMP_Y(x)                          (((x) >> 3) & 0x7)
+#define   C_03C000_CLAMP_Y                             0xFFFFFFC7
+#define   S_03C000_CLAMP_Z(x)                          (((x) & 0x7) << 6)
+#define   G_03C000_CLAMP_Z(x)                          (((x) >> 6) & 0x7)
+#define   C_03C000_CLAMP_Z                             0xFFFFFE3F
+#define   S_03C000_XY_MAG_FILTER(x)                    (((x) & 0x7) << 9)
+#define   G_03C000_XY_MAG_FILTER(x)                    (((x) >> 9) & 0x7)
+#define   C_03C000_XY_MAG_FILTER                       0xFFFFF1FF
+#define   S_03C000_XY_MIN_FILTER(x)                    (((x) & 0x7) << 12)
+#define   G_03C000_XY_MIN_FILTER(x)                    (((x) >> 12) & 0x7)
+#define   C_03C000_XY_MIN_FILTER                       0xFFFF8FFF
+#define   S_03C000_Z_FILTER(x)                         (((x) & 0x3) << 15)
+#define   G_03C000_Z_FILTER(x)                         (((x) >> 15) & 0x3)
+#define   C_03C000_Z_FILTER                            0xFFFE7FFF
+#define   S_03C000_MIP_FILTER(x)                       (((x) & 0x3) << 17)
+#define   G_03C000_MIP_FILTER(x)                       (((x) >> 17) & 0x3)
+#define   C_03C000_MIP_FILTER                          0xFFF9FFFF
+#define   S_03C000_BORDER_COLOR_TYPE(x)                (((x) & 0x3) << 22)
+#define   G_03C000_BORDER_COLOR_TYPE(x)                (((x) >> 22) & 0x3)
+#define   C_03C000_BORDER_COLOR_TYPE                   0xFF3FFFFF
+#define   S_03C000_POINT_SAMPLING_CLAMP(x)             (((x) & 0x1) << 24)
+#define   G_03C000_POINT_SAMPLING_CLAMP(x)             (((x) >> 24) & 0x1)
+#define   C_03C000_POINT_SAMPLING_CLAMP                0xFEFFFFFF
+#define   S_03C000_TEX_ARRAY_OVERRIDE(x)               (((x) & 0x1) << 25)
+#define   G_03C000_TEX_ARRAY_OVERRIDE(x)               (((x) >> 25) & 0x1)
+#define   C_03C000_TEX_ARRAY_OVERRIDE                  0xFDFFFFFF
+#define   S_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) & 0x7) << 26)
+#define   G_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) >> 26) & 0x7)
+#define   C_03C000_DEPTH_COMPARE_FUNCTION              0xE3FFFFFF
+#define   S_03C000_CHROMA_KEY(x)                       (((x) & 0x3) << 29)
+#define   G_03C000_CHROMA_KEY(x)                       (((x) >> 29) & 0x3)
+#define   C_03C000_CHROMA_KEY                          0x9FFFFFFF
+#define   S_03C000_LOD_USES_MINOR_AXIS(x)              (((x) & 0x1) << 31)
+#define   G_03C000_LOD_USES_MINOR_AXIS(x)              (((x) >> 31) & 0x1)
+#define   C_03C000_LOD_USES_MINOR_AXIS                 0x7FFFFFFF
+#define R_03C004_SQ_TEX_SAMPLER_WORD1_0              0x03C004
+#define   S_03C004_MIN_LOD(x)                          (((x) & 0x3FF) << 0)
+#define   G_03C004_MIN_LOD(x)                          (((x) >> 0) & 0x3FF)
+#define   C_03C004_MIN_LOD                             0xFFFFFC00
+#define   S_03C004_MAX_LOD(x)                          (((x) & 0x3FF) << 10)
+#define   G_03C004_MAX_LOD(x)                          (((x) >> 10) & 0x3FF)
+#define   C_03C004_MAX_LOD                             0xFFF003FF
+#define   S_03C004_LOD_BIAS(x)                         (((x) & 0xFFF) << 20)
+#define   G_03C004_LOD_BIAS(x)                         (((x) >> 20) & 0xFFF)
+#define   C_03C004_LOD_BIAS                            0x000FFFFF
+#define R_03C008_SQ_TEX_SAMPLER_WORD2_0              0x03C008
+#define   S_03C008_LOD_BIAS_SEC(x)                     (((x) & 0xFFF) << 0)
+#define   G_03C008_LOD_BIAS_SEC(x)                     (((x) >> 0) & 0xFFF)
+#define   C_03C008_LOD_BIAS_SEC                        0xFFFFF000
+#define   S_03C008_MC_COORD_TRUNCATE(x)                (((x) & 0x1) << 12)
+#define   G_03C008_MC_COORD_TRUNCATE(x)                (((x) >> 12) & 0x1)
+#define   C_03C008_MC_COORD_TRUNCATE                   0xFFFFEFFF
+#define   S_03C008_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 13)
+#define   G_03C008_FORCE_DEGAMMA(x)                    (((x) >> 13) & 0x1)
+#define   C_03C008_FORCE_DEGAMMA                       0xFFFFDFFF
+#define   S_03C008_HIGH_PRECISION_FILTER(x)            (((x) & 0x1) << 14)
+#define   G_03C008_HIGH_PRECISION_FILTER(x)            (((x) >> 14) & 0x1)
+#define   C_03C008_HIGH_PRECISION_FILTER               0xFFFFBFFF
+#define   S_03C008_PERF_MIP(x)                         (((x) & 0x7) << 15)
+#define   G_03C008_PERF_MIP(x)                         (((x) >> 15) & 0x7)
+#define   C_03C008_PERF_MIP                            0xFFFC7FFF
+#define   S_03C008_PERF_Z(x)                           (((x) & 0x3) << 18)
+#define   G_03C008_PERF_Z(x)                           (((x) >> 18) & 0x3)
+#define   C_03C008_PERF_Z                              0xFFF3FFFF
+#define   S_03C008_FETCH_4(x)                          (((x) & 0x1) << 26)
+#define   G_03C008_FETCH_4(x)                          (((x) >> 26) & 0x1)
+#define   C_03C008_FETCH_4                             0xFBFFFFFF
+#define   S_03C008_SAMPLE_IS_PCF(x)                    (((x) & 0x1) << 27)
+#define   G_03C008_SAMPLE_IS_PCF(x)                    (((x) >> 27) & 0x1)
+#define   C_03C008_SAMPLE_IS_PCF                       0xF7FFFFFF
+#define   S_03C008_TYPE(x)                             (((x) & 0x1) << 31)
+#define   G_03C008_TYPE(x)                             (((x) >> 31) & 0x1)
+#define   C_03C008_TYPE                                0x7FFFFFFF
+#define R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA         0x00A40C
+#define   S_00A40C_BORDER_ALPHA(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A40C_BORDER_ALPHA(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A40C_BORDER_ALPHA                        0x00000000
+#define R_00A408_TD_PS_SAMPLER0_BORDER_BLUE          0x00A408
+#define   S_00A408_BORDER_BLUE(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A408_BORDER_BLUE(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A408_BORDER_BLUE                         0x00000000
+#define R_00A404_TD_PS_SAMPLER0_BORDER_GREEN         0x00A404
+#define   S_00A404_BORDER_GREEN(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A404_BORDER_GREEN(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A404_BORDER_GREEN                        0x00000000
+#define R_00A400_TD_PS_SAMPLER0_BORDER_RED           0x00A400
+#define   S_00A400_BORDER_RED(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A400_BORDER_RED(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A400_BORDER_RED                          0x00000000
+#define R_00A60C_TD_VS_SAMPLER0_BORDER_ALPHA         0x00A60C
+#define   S_00A60C_BORDER_ALPHA(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A60C_BORDER_ALPHA(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A60C_BORDER_ALPHA                        0x00000000
+#define R_00A608_TD_VS_SAMPLER0_BORDER_BLUE          0x00A608
+#define   S_00A608_BORDER_BLUE(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A608_BORDER_BLUE(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A608_BORDER_BLUE                         0x00000000
+#define R_00A604_TD_VS_SAMPLER0_BORDER_GREEN         0x00A604
+#define   S_00A604_BORDER_GREEN(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A604_BORDER_GREEN(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A604_BORDER_GREEN                        0x00000000
+#define R_00A600_TD_VS_SAMPLER0_BORDER_RED           0x00A600
+#define   S_00A600_BORDER_RED(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A600_BORDER_RED(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A600_BORDER_RED                          0x00000000
+#define R_00A80C_TD_GS_SAMPLER0_BORDER_ALPHA         0x00A80C
+#define   S_00A80C_BORDER_ALPHA(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A80C_BORDER_ALPHA(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A80C_BORDER_ALPHA                        0x00000000
+#define R_00A808_TD_GS_SAMPLER0_BORDER_BLUE          0x00A808
+#define   S_00A808_BORDER_BLUE(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A808_BORDER_BLUE(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A808_BORDER_BLUE                         0x00000000
+#define R_00A804_TD_GS_SAMPLER0_BORDER_GREEN         0x00A804
+#define   S_00A804_BORDER_GREEN(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A804_BORDER_GREEN(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A804_BORDER_GREEN                        0x00000000
+#define R_00A800_TD_GS_SAMPLER0_BORDER_RED           0x00A800
+#define   S_00A800_BORDER_RED(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A800_BORDER_RED(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A800_BORDER_RED                          0x00000000
+#define R_030000_SQ_ALU_CONSTANT0_0                  0x030000
+#define   S_030000_X(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_030000_X(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030000_X                                   0x00000000
+#define R_030004_SQ_ALU_CONSTANT1_0                  0x030004
+#define   S_030004_Y(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_030004_Y(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030004_Y                                   0x00000000
+#define R_030008_SQ_ALU_CONSTANT2_0                  0x030008
+#define   S_030008_Z(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_030008_Z(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030008_Z                                   0x00000000
+#define R_03000C_SQ_ALU_CONSTANT3_0                  0x03000C
+#define   S_03000C_W(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_03000C_W(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_03000C_W                                   0x00000000
+#define R_0287E4_VGT_DMA_BASE_HI                     0x0287E4
+#define R_0287E8_VGT_DMA_BASE                        0x0287E8
+#define R_028E20_PA_CL_UCP0_X                        0x028E20
+#define R_028E24_PA_CL_UCP0_Y                        0x028E24
+#define R_028E28_PA_CL_UCP0_Z                        0x028E28
+#define R_028E2C_PA_CL_UCP0_W                        0x028E2C
+#define R_028E30_PA_CL_UCP1_X                        0x028E30
+#define R_028E34_PA_CL_UCP1_Y                        0x028E34
+#define R_028E38_PA_CL_UCP1_Z                        0x028E38
+#define R_028E3C_PA_CL_UCP1_W                        0x028E3C
+#define R_028E40_PA_CL_UCP2_X                        0x028E40
+#define R_028E44_PA_CL_UCP2_Y                        0x028E44
+#define R_028E48_PA_CL_UCP2_Z                        0x028E48
+#define R_028E4C_PA_CL_UCP2_W                        0x028E4C
+#define R_028E50_PA_CL_UCP3_X                        0x028E50
+#define R_028E54_PA_CL_UCP3_Y                        0x028E54
+#define R_028E58_PA_CL_UCP3_Z                        0x028E58
+#define R_028E5C_PA_CL_UCP3_W                        0x028E5C
+#define R_028E60_PA_CL_UCP4_X                        0x028E60
+#define R_028E64_PA_CL_UCP4_Y                        0x028E64
+#define R_028E68_PA_CL_UCP4_Z                        0x028E68
+#define R_028E6C_PA_CL_UCP4_W                        0x028E6C
+#define R_028E70_PA_CL_UCP5_X                        0x028E70
+#define R_028E74_PA_CL_UCP5_Y                        0x028E74
+#define R_028E78_PA_CL_UCP5_Z                        0x028E78
+#define R_028E7C_PA_CL_UCP5_W                        0x028E7C
+#define R_038000_RESOURCE0_WORD0                     0x038000
+#define R_038004_RESOURCE0_WORD1                     0x038004
+#define R_038008_RESOURCE0_WORD2                     0x038008
+#define R_03800C_RESOURCE0_WORD3                     0x03800C
+#define R_038010_RESOURCE0_WORD4                     0x038010
+#define R_038014_RESOURCE0_WORD5                     0x038014
+#define R_038018_RESOURCE0_WORD6                     0x038018
+
+#define R_028140_ALU_CONST_BUFFER_SIZE_PS_0          0x00028140
+#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0          0x00028180
+#define R_028940_ALU_CONST_CACHE_PS_0                0x00028940
+#define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
+
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC                 0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC               0x03CFF4
+
+#endif
diff --git a/src/gallium/winsys/r600/drm/radeon_bo.c b/src/gallium/winsys/r600/drm/radeon_bo.c
new file mode 100644
index 00000000000..42a23f0ab8f
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/radeon_bo.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#define _FILE_OFFSET_BITS 64
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <errno.h>
+#include "r600_priv.h"
+#include "xf86drm.h"
+#include "radeon_drm.h"
+#include "util/u_time.h"
+
+static int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo)
+{
+	struct drm_radeon_gem_mmap args;
+	void *ptr;
+	int r;
+
+	/* Zero out args to make valgrind happy */
+	memset(&args, 0, sizeof(args));
+	args.handle = bo->handle;
+	args.offset = 0;
+	args.size = (uint64_t)bo->size;
+	r = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_MMAP,
+				&args, sizeof(args));
+	if (r) {
+		fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n",
+			bo, bo->handle, r);
+		return r;
+	}
+	ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, radeon->fd, args.addr_ptr);
+	if (ptr == MAP_FAILED) {
+		fprintf(stderr, "%s failed to map bo\n", __func__);
+		return -errno;
+	}
+	bo->data = ptr;
+
+	bo->map_count++;
+	return 0;
+}
+
+static void radeon_bo_fixed_unmap(struct radeon *radeon, struct radeon_bo *bo)
+{
+	munmap(bo->data, bo->size);
+	bo->data = NULL;
+}
+
+struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
+			unsigned size, unsigned alignment, void *ptr)
+{
+	struct radeon_bo *bo;
+	int r;
+
+	bo = calloc(1, sizeof(*bo));
+	if (bo == NULL) {
+		return NULL;
+	}
+	bo->size = size;
+	bo->handle = handle;
+	pipe_reference_init(&bo->reference, 1);
+	bo->alignment = alignment;
+
+	if (handle) {
+		struct drm_gem_open open_arg;
+
+		memset(&open_arg, 0, sizeof(open_arg));
+		open_arg.name = handle;
+		r = drmIoctl(radeon->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
+		if (r != 0) {
+			free(bo);
+			return NULL;
+		}
+		bo->handle = open_arg.handle;
+		bo->size = open_arg.size;
+		bo->shared = TRUE;
+	} else {
+		struct drm_radeon_gem_create args;
+
+		args.size = size;
+		args.alignment = alignment;
+		args.initial_domain = RADEON_GEM_DOMAIN_CPU;
+		args.flags = 0;
+		args.handle = 0;
+		r = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_CREATE,
+					&args, sizeof(args));
+		bo->handle = args.handle;
+		if (r) {
+			fprintf(stderr, "Failed to allocate :\n");
+			fprintf(stderr, "   size      : %d bytes\n", size);
+			fprintf(stderr, "   alignment : %d bytes\n", alignment);
+			free(bo);
+			return NULL;
+		}
+	}
+	if (radeon_bo_fixed_map(radeon, bo)) {
+		R600_ERR("failed to map bo\n");
+		radeon_bo_reference(radeon, &bo, NULL);
+		return bo;
+	}
+	if (ptr) {
+		memcpy(bo->data, ptr, size);
+	}
+	LIST_INITHEAD(&bo->fencedlist);
+	return bo;
+}
+
+
+static void radeon_bo_destroy(struct radeon *radeon, struct radeon_bo *bo)
+{
+	struct drm_gem_close args;
+
+	LIST_DEL(&bo->fencedlist);
+	radeon_bo_fixed_unmap(radeon, bo);
+	memset(&args, 0, sizeof(args));
+	args.handle = bo->handle;
+	drmIoctl(radeon->fd, DRM_IOCTL_GEM_CLOSE, &args);
+	memset(bo, 0, sizeof(struct radeon_bo));
+	free(bo);
+}
+
+void radeon_bo_reference(struct radeon *radeon,
+			 struct radeon_bo **dst,
+			 struct radeon_bo *src)
+{
+	struct radeon_bo *old = *dst;
+	if (pipe_reference(&(*dst)->reference, &src->reference)) {
+		radeon_bo_destroy(radeon, old);
+	}
+	*dst = src;
+}
+
+int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo)
+{
+	struct drm_radeon_gem_wait_idle args;
+	int ret;
+
+	if (LIST_IS_EMPTY(&bo->fencedlist) && !bo->shared)
+		return 0;
+
+	/* Zero out args to make valgrind happy */
+	memset(&args, 0, sizeof(args));
+	args.handle = bo->handle;
+	do {
+		ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_WAIT_IDLE,
+					&args, sizeof(args));
+	} while (ret == -EBUSY);
+	return ret;
+}
+
+#define BO_BUSY_BACKOFF 10000
+
+int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain)
+{
+	struct drm_radeon_gem_busy args;
+	int ret;
+	int64_t now;
+
+	now = os_time_get();
+	if (LIST_IS_EMPTY(&bo->fencedlist) && !bo->shared)
+		return 0;
+
+	if (bo->set_busy && (now - bo->last_busy < BO_BUSY_BACKOFF))
+		return -EBUSY;
+
+	bo->set_busy = FALSE;
+
+	memset(&args, 0, sizeof(args));
+	args.handle = bo->handle;
+	args.domain = 0;
+
+	ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_BUSY,
+			&args, sizeof(args));
+
+	if (ret == 0) {
+		struct radeon_bo *entry, *tent;
+		LIST_FOR_EACH_ENTRY_SAFE(entry, tent, &bo->fencedlist, fencedlist) {
+			LIST_DELINIT(&entry->fencedlist);
+		}
+	} else {
+		bo->set_busy = TRUE;
+		bo->last_busy = now;
+	}
+	*domain = args.domain;
+	return ret;
+}
+
+int radeon_bo_fencelist(struct radeon *radeon, struct radeon_bo **bolist,
+			uint32_t num_bo)
+{
+	struct radeon_bo *first;
+	int i;
+
+	first = bolist[0];
+
+	if (!LIST_IS_EMPTY(&first->fencedlist))
+		LIST_DELINIT(&first->fencedlist);
+
+	LIST_INITHEAD(&first->fencedlist);
+
+	for (i = 1; i < num_bo; i++) {
+		if (!LIST_IS_EMPTY(&bolist[i]->fencedlist))
+			LIST_DELINIT(&bolist[i]->fencedlist);
+
+		LIST_ADDTAIL(&bolist[i]->fencedlist, &first->fencedlist);
+	}
+	return 0;
+}
diff --git a/src/gallium/winsys/r600/drm/radeon_bo_pb.c b/src/gallium/winsys/r600/drm/radeon_bo_pb.c
new file mode 100644
index 00000000000..a3452027f27
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/radeon_bo_pb.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright 2010 Dave Airlie
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Dave Airlie
+ */
+#include <util/u_inlines.h>
+#include <util/u_memory.h>
+#include <util/u_double_list.h>
+#include <pipebuffer/pb_buffer.h>
+#include <pipebuffer/pb_bufmgr.h>
+#include "r600_priv.h"
+
+struct radeon_bo_pb {
+	struct pb_buffer b;
+	struct radeon_bo *bo;
+
+	struct radeon_bo_pbmgr *mgr;
+	struct list_head maplist;
+};
+
+extern const struct pb_vtbl radeon_bo_pb_vtbl;
+
+static INLINE struct radeon_bo_pb *radeon_bo_pb(struct pb_buffer *buf)
+{
+	assert(buf);
+	assert(buf->vtbl == &radeon_bo_pb_vtbl);
+	return (struct radeon_bo_pb *)buf;
+}
+
+struct radeon_bo_pbmgr {
+	struct pb_manager b;
+	struct radeon *radeon;
+	struct list_head buffer_map_list;
+};
+
+static INLINE struct radeon_bo_pbmgr *radeon_bo_pbmgr(struct pb_manager *mgr)
+{
+	assert(mgr);
+	return (struct radeon_bo_pbmgr *)mgr;
+}
+
+static void radeon_bo_pb_destroy(struct pb_buffer *_buf)
+{
+	struct radeon_bo_pb *buf = radeon_bo_pb(_buf);
+
+	LIST_DEL(&buf->maplist);
+
+	if (buf->bo->data != NULL) {
+		radeon_bo_unmap(buf->mgr->radeon, buf->bo);
+	}
+	radeon_bo_reference(buf->mgr->radeon, &buf->bo, NULL);
+	FREE(buf);
+}
+
+static void *
+radeon_bo_pb_map_internal(struct pb_buffer *_buf,
+			  unsigned flags, void *ctx)
+{
+	struct radeon_bo_pb *buf = radeon_bo_pb(_buf);
+	struct pipe_context *pctx = ctx;
+
+	if (flags & PB_USAGE_UNSYNCHRONIZED) {
+		if (!buf->bo->data && radeon_bo_map(buf->mgr->radeon, buf->bo)) {
+			return NULL;
+		}
+		LIST_DELINIT(&buf->maplist);
+		return buf->bo->data;
+	}
+
+	if (p_atomic_read(&buf->bo->reference.count) > 1) {
+		if (flags & PB_USAGE_DONTBLOCK) {
+			return NULL;
+		}
+		if (ctx) {
+			pctx->flush(pctx, 0, NULL);
+		}
+	}
+
+	if (flags & PB_USAGE_DONTBLOCK) {
+		uint32_t domain;
+		if (radeon_bo_busy(buf->mgr->radeon, buf->bo, &domain))
+			return NULL;
+		if (radeon_bo_map(buf->mgr->radeon, buf->bo)) {
+			return NULL;
+		}
+		goto out;
+	}
+
+	if (buf->bo->data != NULL) {
+		if (radeon_bo_wait(buf->mgr->radeon, buf->bo)) {
+			return NULL;
+		}
+	} else {
+		if (radeon_bo_map(buf->mgr->radeon, buf->bo)) {
+			return NULL;
+		}
+		if (radeon_bo_wait(buf->mgr->radeon, buf->bo)) {
+			radeon_bo_unmap(buf->mgr->radeon, buf->bo);
+			return NULL;
+		}
+	}
+out:
+	LIST_DELINIT(&buf->maplist);
+	return buf->bo->data;
+}
+
+static void radeon_bo_pb_unmap_internal(struct pb_buffer *_buf)
+{
+	struct radeon_bo_pb *buf = radeon_bo_pb(_buf);
+	LIST_ADDTAIL(&buf->maplist, &buf->mgr->buffer_map_list);
+}
+
+static void
+radeon_bo_pb_get_base_buffer(struct pb_buffer *buf,
+			     struct pb_buffer **base_buf,
+			     unsigned *offset)
+{
+	*base_buf = buf;
+	*offset = 0;
+}
+
+static enum pipe_error
+radeon_bo_pb_validate(struct pb_buffer *_buf, 
+		      struct pb_validate *vl,
+		      unsigned flags)
+{
+	/* Always pinned */
+	return PIPE_OK;
+}
+
+static void
+radeon_bo_pb_fence(struct pb_buffer *buf,
+		   struct pipe_fence_handle *fence)
+{
+}
+
+const struct pb_vtbl radeon_bo_pb_vtbl = {
+    radeon_bo_pb_destroy,
+    radeon_bo_pb_map_internal,
+    radeon_bo_pb_unmap_internal,
+    radeon_bo_pb_validate,
+    radeon_bo_pb_fence,
+    radeon_bo_pb_get_base_buffer,
+};
+
+struct pb_buffer *
+radeon_bo_pb_create_buffer_from_handle(struct pb_manager *_mgr,
+				       uint32_t handle)
+{
+	struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr);
+	struct radeon *radeon = mgr->radeon;
+	struct radeon_bo_pb *bo;
+	struct radeon_bo *hw_bo;
+
+	hw_bo = radeon_bo(radeon, handle, 0, 0, NULL);
+	if (hw_bo == NULL)
+		return NULL;
+
+	bo = CALLOC_STRUCT(radeon_bo_pb);
+	if (!bo) {
+		radeon_bo_reference(radeon, &hw_bo, NULL);
+		return NULL;
+	}
+
+	LIST_INITHEAD(&bo->maplist);
+	pipe_reference_init(&bo->b.base.reference, 1);
+	bo->b.base.alignment = 0;
+	bo->b.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
+	bo->b.base.size = hw_bo->size;
+	bo->b.vtbl = &radeon_bo_pb_vtbl;
+	bo->mgr = mgr;
+
+	bo->bo = hw_bo;
+
+	return &bo->b;
+}
+
+static struct pb_buffer *
+radeon_bo_pb_create_buffer(struct pb_manager *_mgr,
+			   pb_size size,
+			   const struct pb_desc *desc)
+{
+	struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr);
+	struct radeon *radeon = mgr->radeon;
+	struct radeon_bo_pb *bo;
+
+	bo = CALLOC_STRUCT(radeon_bo_pb);
+	if (!bo)
+		goto error1;
+
+	pipe_reference_init(&bo->b.base.reference, 1);
+	bo->b.base.alignment = desc->alignment;
+	bo->b.base.usage = desc->usage;
+	bo->b.base.size = size;
+	bo->b.vtbl = &radeon_bo_pb_vtbl;
+	bo->mgr = mgr;
+
+	LIST_INITHEAD(&bo->maplist);
+
+	bo->bo = radeon_bo(radeon, 0, size,
+			   desc->alignment, NULL);
+	if (bo->bo == NULL)
+		goto error2;
+	return &bo->b;
+
+error2:
+	FREE(bo);
+error1:
+	return NULL;
+}
+
+static void
+radeon_bo_pbmgr_flush(struct pb_manager *mgr)
+{
+    /* NOP */
+}
+
+static void
+radeon_bo_pbmgr_destroy(struct pb_manager *_mgr)
+{
+	struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr);
+	FREE(mgr);
+}
+
+struct pb_manager *radeon_bo_pbmgr_create(struct radeon *radeon)
+{
+	struct radeon_bo_pbmgr *mgr;
+
+	mgr = CALLOC_STRUCT(radeon_bo_pbmgr);
+	if (!mgr)
+		return NULL;
+
+	mgr->b.destroy = radeon_bo_pbmgr_destroy;
+	mgr->b.create_buffer = radeon_bo_pb_create_buffer;
+	mgr->b.flush = radeon_bo_pbmgr_flush;
+
+	mgr->radeon = radeon;
+	LIST_INITHEAD(&mgr->buffer_map_list);
+	return &mgr->b;
+}
+
+void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr)
+{
+	struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr);
+	struct radeon_bo_pb *rpb = NULL;
+	struct radeon_bo_pb *t_rpb;
+
+	LIST_FOR_EACH_ENTRY_SAFE(rpb, t_rpb, &mgr->buffer_map_list, maplist) {
+		radeon_bo_unmap(mgr->radeon, rpb->bo);
+		LIST_DELINIT(&rpb->maplist);
+	}
+
+	LIST_INITHEAD(&mgr->buffer_map_list);
+}
+
+struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf)
+{
+	struct radeon_bo_pb *buf;
+	if (_buf->vtbl == &radeon_bo_pb_vtbl) {
+		buf = radeon_bo_pb(_buf);
+		return buf->bo;
+	} else {
+		struct pb_buffer *base_buf;
+		pb_size offset;
+		pb_get_base_buffer(_buf, &base_buf, &offset);
+		if (base_buf->vtbl == &radeon_bo_pb_vtbl) {
+			buf = radeon_bo_pb(base_buf);
+			return buf->bo;
+		}
+	}
+	return NULL;
+}
diff --git a/src/gallium/winsys/r600/drm/radeon_pciid.c b/src/gallium/winsys/r600/drm/radeon_pciid.c
new file mode 100644
index 00000000000..08cc1c41e37
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/radeon_pciid.c
@@ -0,0 +1,528 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <stdlib.h>
+#include "r600.h"
+
+struct pci_id {
+	unsigned	vendor;
+	unsigned	device;
+	unsigned	family;
+};
+
+struct pci_id radeon_pci_id[] = {
+	{0x1002, 0x3150, CHIP_RV380},
+	{0x1002, 0x3152, CHIP_RV380},
+	{0x1002, 0x3154, CHIP_RV380},
+	{0x1002, 0x3E50, CHIP_RV380},
+	{0x1002, 0x3E54, CHIP_RV380},
+	{0x1002, 0x4136, CHIP_RS100},
+	{0x1002, 0x4137, CHIP_RS200},
+	{0x1002, 0x4144, CHIP_R300}, 
+	{0x1002, 0x4145, CHIP_R300}, 
+	{0x1002, 0x4146, CHIP_R300}, 
+	{0x1002, 0x4147, CHIP_R300}, 
+	{0x1002, 0x4148, CHIP_R350}, 
+	{0x1002, 0x4149, CHIP_R350}, 
+	{0x1002, 0x414A, CHIP_R350}, 
+	{0x1002, 0x414B, CHIP_R350}, 
+	{0x1002, 0x4150, CHIP_RV350}, 
+	{0x1002, 0x4151, CHIP_RV350}, 
+	{0x1002, 0x4152, CHIP_RV350}, 
+	{0x1002, 0x4153, CHIP_RV350}, 
+	{0x1002, 0x4154, CHIP_RV350}, 
+	{0x1002, 0x4155, CHIP_RV350}, 
+	{0x1002, 0x4156, CHIP_RV350}, 
+	{0x1002, 0x4237, CHIP_RS200},
+	{0x1002, 0x4242, CHIP_R200}, 
+	{0x1002, 0x4243, CHIP_R200}, 
+	{0x1002, 0x4336, CHIP_RS100},
+	{0x1002, 0x4337, CHIP_RS200},
+	{0x1002, 0x4437, CHIP_RS200},
+	{0x1002, 0x4966, CHIP_RV250}, 
+	{0x1002, 0x4967, CHIP_RV250}, 
+	{0x1002, 0x4A48, CHIP_R420},
+	{0x1002, 0x4A49, CHIP_R420},
+	{0x1002, 0x4A4A, CHIP_R420},
+	{0x1002, 0x4A4B, CHIP_R420},
+	{0x1002, 0x4A4C, CHIP_R420},
+	{0x1002, 0x4A4D, CHIP_R420},
+	{0x1002, 0x4A4E, CHIP_R420},
+	{0x1002, 0x4A4F, CHIP_R420},
+	{0x1002, 0x4A50, CHIP_R420},
+	{0x1002, 0x4A54, CHIP_R420},
+	{0x1002, 0x4B48, CHIP_R420},
+	{0x1002, 0x4B49, CHIP_R420},
+	{0x1002, 0x4B4A, CHIP_R420},
+	{0x1002, 0x4B4B, CHIP_R420},
+	{0x1002, 0x4B4C, CHIP_R420},
+	{0x1002, 0x4C57, CHIP_RV200},
+	{0x1002, 0x4C58, CHIP_RV200},
+	{0x1002, 0x4C59, CHIP_RV100},
+	{0x1002, 0x4C5A, CHIP_RV100},
+	{0x1002, 0x4C64, CHIP_RV250},
+	{0x1002, 0x4C66, CHIP_RV250},
+	{0x1002, 0x4C67, CHIP_RV250},
+	{0x1002, 0x4E44, CHIP_R300}, 
+	{0x1002, 0x4E45, CHIP_R300}, 
+	{0x1002, 0x4E46, CHIP_R300}, 
+	{0x1002, 0x4E47, CHIP_R300}, 
+	{0x1002, 0x4E48, CHIP_R350}, 
+	{0x1002, 0x4E49, CHIP_R350}, 
+	{0x1002, 0x4E4A, CHIP_R350}, 
+	{0x1002, 0x4E4B, CHIP_R350}, 
+	{0x1002, 0x4E50, CHIP_RV350},
+	{0x1002, 0x4E51, CHIP_RV350},
+	{0x1002, 0x4E52, CHIP_RV350},
+	{0x1002, 0x4E53, CHIP_RV350},
+	{0x1002, 0x4E54, CHIP_RV350},
+	{0x1002, 0x4E56, CHIP_RV350},
+	{0x1002, 0x5144, CHIP_R100},
+	{0x1002, 0x5145, CHIP_R100},
+	{0x1002, 0x5146, CHIP_R100},
+	{0x1002, 0x5147, CHIP_R100},
+	{0x1002, 0x5148, CHIP_R200}, 
+	{0x1002, 0x514C, CHIP_R200}, 
+	{0x1002, 0x514D, CHIP_R200}, 
+	{0x1002, 0x5157, CHIP_RV200}, 
+	{0x1002, 0x5158, CHIP_RV200}, 
+	{0x1002, 0x5159, CHIP_RV100}, 
+	{0x1002, 0x515A, CHIP_RV100}, 
+	{0x1002, 0x515E, CHIP_RV100},
+	{0x1002, 0x5460, CHIP_RV380},
+	{0x1002, 0x5462, CHIP_RV380},
+	{0x1002, 0x5464, CHIP_RV380},
+	{0x1002, 0x5657, CHIP_RV380},
+	{0x1002, 0x5548, CHIP_R423},
+	{0x1002, 0x5549, CHIP_R423},
+	{0x1002, 0x554A, CHIP_R423},
+	{0x1002, 0x554B, CHIP_R423},
+	{0x1002, 0x554C, CHIP_R423},
+	{0x1002, 0x554D, CHIP_R423},
+	{0x1002, 0x554E, CHIP_R423},
+	{0x1002, 0x554F, CHIP_R423},
+	{0x1002, 0x5550, CHIP_R423},
+	{0x1002, 0x5551, CHIP_R423},
+	{0x1002, 0x5552, CHIP_R423},
+	{0x1002, 0x5554, CHIP_R423},
+	{0x1002, 0x564A, CHIP_RV410},
+	{0x1002, 0x564B, CHIP_RV410},
+	{0x1002, 0x564F, CHIP_RV410},
+	{0x1002, 0x5652, CHIP_RV410},
+	{0x1002, 0x5653, CHIP_RV410},
+	{0x1002, 0x5834, CHIP_RS300},
+	{0x1002, 0x5835, CHIP_RS300},
+	{0x1002, 0x5954, CHIP_RS480},
+	{0x1002, 0x5955, CHIP_RS480},
+	{0x1002, 0x5974, CHIP_RS480},
+	{0x1002, 0x5975, CHIP_RS480},
+	{0x1002, 0x5960, CHIP_RV280}, 
+	{0x1002, 0x5961, CHIP_RV280}, 
+	{0x1002, 0x5962, CHIP_RV280}, 
+	{0x1002, 0x5964, CHIP_RV280}, 
+	{0x1002, 0x5965, CHIP_RV280},
+	{0x1002, 0x5969, CHIP_RV100},
+	{0x1002, 0x5a41, CHIP_RS400},
+	{0x1002, 0x5a42, CHIP_RS400},
+	{0x1002, 0x5a61, CHIP_RS400},
+	{0x1002, 0x5a62, CHIP_RS400},
+	{0x1002, 0x5b60, CHIP_RV380},
+	{0x1002, 0x5b62, CHIP_RV380},
+	{0x1002, 0x5b63, CHIP_RV380},
+	{0x1002, 0x5b64, CHIP_RV380},
+	{0x1002, 0x5b65, CHIP_RV380},
+	{0x1002, 0x5c61, CHIP_RV280},
+	{0x1002, 0x5c63, CHIP_RV280},
+	{0x1002, 0x5d48, CHIP_R423},
+	{0x1002, 0x5d49, CHIP_R423},
+	{0x1002, 0x5d4a, CHIP_R423},
+	{0x1002, 0x5d4c, CHIP_R423},
+	{0x1002, 0x5d4d, CHIP_R423},
+	{0x1002, 0x5d4e, CHIP_R423},
+	{0x1002, 0x5d4f, CHIP_R423},
+	{0x1002, 0x5d50, CHIP_R423},
+	{0x1002, 0x5d52, CHIP_R423},
+	{0x1002, 0x5d57, CHIP_R423},
+	{0x1002, 0x5e48, CHIP_RV410},
+	{0x1002, 0x5e4a, CHIP_RV410},
+	{0x1002, 0x5e4b, CHIP_RV410},
+	{0x1002, 0x5e4c, CHIP_RV410},
+	{0x1002, 0x5e4d, CHIP_RV410},
+	{0x1002, 0x5e4f, CHIP_RV410},
+	{0x1002, 0x6880, CHIP_CYPRESS},
+	{0x1002, 0x6888, CHIP_CYPRESS},
+	{0x1002, 0x6889, CHIP_CYPRESS},
+	{0x1002, 0x688A, CHIP_CYPRESS},
+	{0x1002, 0x6898, CHIP_CYPRESS},
+	{0x1002, 0x6899, CHIP_CYPRESS},
+	{0x1002, 0x689c, CHIP_HEMLOCK},
+	{0x1002, 0x689d, CHIP_HEMLOCK},
+	{0x1002, 0x689e, CHIP_CYPRESS},
+	{0x1002, 0x68a0, CHIP_JUNIPER},
+	{0x1002, 0x68a1, CHIP_JUNIPER},
+	{0x1002, 0x68a8, CHIP_JUNIPER},
+	{0x1002, 0x68a9, CHIP_JUNIPER},
+	{0x1002, 0x68b0, CHIP_JUNIPER},
+	{0x1002, 0x68b8, CHIP_JUNIPER},
+	{0x1002, 0x68b9, CHIP_JUNIPER},
+	{0x1002, 0x68be, CHIP_JUNIPER},
+	{0x1002, 0x68c0, CHIP_REDWOOD},
+	{0x1002, 0x68c1, CHIP_REDWOOD},
+	{0x1002, 0x68c8, CHIP_REDWOOD},
+	{0x1002, 0x68c9, CHIP_REDWOOD},
+	{0x1002, 0x68d8, CHIP_REDWOOD},
+	{0x1002, 0x68d9, CHIP_REDWOOD},
+	{0x1002, 0x68da, CHIP_REDWOOD},
+	{0x1002, 0x68de, CHIP_REDWOOD},
+	{0x1002, 0x68e0, CHIP_CEDAR},
+	{0x1002, 0x68e1, CHIP_CEDAR},
+	{0x1002, 0x68e4, CHIP_CEDAR},
+	{0x1002, 0x68e5, CHIP_CEDAR},
+	{0x1002, 0x68e8, CHIP_CEDAR},
+	{0x1002, 0x68e9, CHIP_CEDAR},
+	{0x1002, 0x68f1, CHIP_CEDAR},
+	{0x1002, 0x68f8, CHIP_CEDAR},
+	{0x1002, 0x68f9, CHIP_CEDAR},
+	{0x1002, 0x68fe, CHIP_CEDAR},
+	{0x1002, 0x7100, CHIP_R520},
+	{0x1002, 0x7101, CHIP_R520},
+	{0x1002, 0x7102, CHIP_R520},
+	{0x1002, 0x7103, CHIP_R520},
+	{0x1002, 0x7104, CHIP_R520},
+	{0x1002, 0x7105, CHIP_R520},
+	{0x1002, 0x7106, CHIP_R520},
+	{0x1002, 0x7108, CHIP_R520},
+	{0x1002, 0x7109, CHIP_R520},
+	{0x1002, 0x710A, CHIP_R520},
+	{0x1002, 0x710B, CHIP_R520},
+	{0x1002, 0x710C, CHIP_R520},
+	{0x1002, 0x710E, CHIP_R520},
+	{0x1002, 0x710F, CHIP_R520},
+	{0x1002, 0x7140, CHIP_RV515},
+	{0x1002, 0x7141, CHIP_RV515},
+	{0x1002, 0x7142, CHIP_RV515},
+	{0x1002, 0x7143, CHIP_RV515},
+	{0x1002, 0x7144, CHIP_RV515},
+	{0x1002, 0x7145, CHIP_RV515},
+	{0x1002, 0x7146, CHIP_RV515},
+	{0x1002, 0x7147, CHIP_RV515},
+	{0x1002, 0x7149, CHIP_RV515},
+	{0x1002, 0x714A, CHIP_RV515},
+	{0x1002, 0x714B, CHIP_RV515},
+	{0x1002, 0x714C, CHIP_RV515},
+	{0x1002, 0x714D, CHIP_RV515},
+	{0x1002, 0x714E, CHIP_RV515},
+	{0x1002, 0x714F, CHIP_RV515},
+	{0x1002, 0x7151, CHIP_RV515},
+	{0x1002, 0x7152, CHIP_RV515},
+	{0x1002, 0x7153, CHIP_RV515},
+	{0x1002, 0x715E, CHIP_RV515},
+	{0x1002, 0x715F, CHIP_RV515},
+	{0x1002, 0x7180, CHIP_RV515},
+	{0x1002, 0x7181, CHIP_RV515},
+	{0x1002, 0x7183, CHIP_RV515},
+	{0x1002, 0x7186, CHIP_RV515},
+	{0x1002, 0x7187, CHIP_RV515},
+	{0x1002, 0x7188, CHIP_RV515},
+	{0x1002, 0x718A, CHIP_RV515},
+	{0x1002, 0x718B, CHIP_RV515},
+	{0x1002, 0x718C, CHIP_RV515},
+	{0x1002, 0x718D, CHIP_RV515},
+	{0x1002, 0x718F, CHIP_RV515},
+	{0x1002, 0x7193, CHIP_RV515},
+	{0x1002, 0x7196, CHIP_RV515},
+	{0x1002, 0x719B, CHIP_RV515},
+	{0x1002, 0x719F, CHIP_RV515},
+	{0x1002, 0x71C0, CHIP_RV530},
+	{0x1002, 0x71C1, CHIP_RV530},
+	{0x1002, 0x71C2, CHIP_RV530},
+	{0x1002, 0x71C3, CHIP_RV530},
+	{0x1002, 0x71C4, CHIP_RV530},
+	{0x1002, 0x71C5, CHIP_RV530},
+	{0x1002, 0x71C6, CHIP_RV530},
+	{0x1002, 0x71C7, CHIP_RV530},
+	{0x1002, 0x71CD, CHIP_RV530},
+	{0x1002, 0x71CE, CHIP_RV530},
+	{0x1002, 0x71D2, CHIP_RV530},
+	{0x1002, 0x71D4, CHIP_RV530},
+	{0x1002, 0x71D5, CHIP_RV530},
+	{0x1002, 0x71D6, CHIP_RV530},
+	{0x1002, 0x71DA, CHIP_RV530},
+	{0x1002, 0x71DE, CHIP_RV530},
+	{0x1002, 0x7200, CHIP_RV515},
+	{0x1002, 0x7210, CHIP_RV515},
+	{0x1002, 0x7211, CHIP_RV515},
+	{0x1002, 0x7240, CHIP_R580},
+	{0x1002, 0x7243, CHIP_R580},
+	{0x1002, 0x7244, CHIP_R580},
+	{0x1002, 0x7245, CHIP_R580},
+	{0x1002, 0x7246, CHIP_R580},
+	{0x1002, 0x7247, CHIP_R580},
+	{0x1002, 0x7248, CHIP_R580},
+	{0x1002, 0x7249, CHIP_R580},
+	{0x1002, 0x724A, CHIP_R580},
+	{0x1002, 0x724B, CHIP_R580},
+	{0x1002, 0x724C, CHIP_R580},
+	{0x1002, 0x724D, CHIP_R580},
+	{0x1002, 0x724E, CHIP_R580},
+	{0x1002, 0x724F, CHIP_R580},
+	{0x1002, 0x7280, CHIP_RV570},
+	{0x1002, 0x7281, CHIP_RV560},
+	{0x1002, 0x7283, CHIP_RV560},
+	{0x1002, 0x7284, CHIP_R580},
+	{0x1002, 0x7287, CHIP_RV560},
+	{0x1002, 0x7288, CHIP_RV570},
+	{0x1002, 0x7289, CHIP_RV570},
+	{0x1002, 0x728B, CHIP_RV570},
+	{0x1002, 0x728C, CHIP_RV570},
+	{0x1002, 0x7290, CHIP_RV560},
+	{0x1002, 0x7291, CHIP_RV560},
+	{0x1002, 0x7293, CHIP_RV560},
+	{0x1002, 0x7297, CHIP_RV560},
+	{0x1002, 0x7834, CHIP_RS300},
+	{0x1002, 0x7835, CHIP_RS300},
+	{0x1002, 0x791e, CHIP_RS690},
+	{0x1002, 0x791f, CHIP_RS690},
+	{0x1002, 0x793f, CHIP_RS600},
+	{0x1002, 0x7941, CHIP_RS600},
+	{0x1002, 0x7942, CHIP_RS600},
+	{0x1002, 0x796c, CHIP_RS740},
+	{0x1002, 0x796d, CHIP_RS740},
+	{0x1002, 0x796e, CHIP_RS740},
+	{0x1002, 0x796f, CHIP_RS740},
+	{0x1002, 0x9400, CHIP_R600},
+	{0x1002, 0x9401, CHIP_R600},
+	{0x1002, 0x9402, CHIP_R600},
+	{0x1002, 0x9403, CHIP_R600},
+	{0x1002, 0x9405, CHIP_R600},
+	{0x1002, 0x940A, CHIP_R600},
+	{0x1002, 0x940B, CHIP_R600},
+	{0x1002, 0x940F, CHIP_R600},
+	{0x1002, 0x94A0, CHIP_RV740},
+	{0x1002, 0x94A1, CHIP_RV740},
+	{0x1002, 0x94A3, CHIP_RV740},
+	{0x1002, 0x94B1, CHIP_RV740},
+	{0x1002, 0x94B3, CHIP_RV740},
+	{0x1002, 0x94B4, CHIP_RV740},
+	{0x1002, 0x94B5, CHIP_RV740},
+	{0x1002, 0x94B9, CHIP_RV740},
+	{0x1002, 0x9440, CHIP_RV770},
+	{0x1002, 0x9441, CHIP_RV770},
+	{0x1002, 0x9442, CHIP_RV770},
+	{0x1002, 0x9443, CHIP_RV770},
+	{0x1002, 0x9444, CHIP_RV770},
+	{0x1002, 0x9446, CHIP_RV770},
+	{0x1002, 0x944A, CHIP_RV770},
+	{0x1002, 0x944B, CHIP_RV770},
+	{0x1002, 0x944C, CHIP_RV770},
+	{0x1002, 0x944E, CHIP_RV770},
+	{0x1002, 0x9450, CHIP_RV770},
+	{0x1002, 0x9452, CHIP_RV770},
+	{0x1002, 0x9456, CHIP_RV770},
+	{0x1002, 0x945A, CHIP_RV770},
+	{0x1002, 0x945B, CHIP_RV770},
+	{0x1002, 0x9460, CHIP_RV770},
+	{0x1002, 0x9462, CHIP_RV770},
+	{0x1002, 0x946A, CHIP_RV770},
+	{0x1002, 0x946B, CHIP_RV770},
+	{0x1002, 0x947A, CHIP_RV770},
+	{0x1002, 0x947B, CHIP_RV770},
+	{0x1002, 0x9480, CHIP_RV730},
+	{0x1002, 0x9487, CHIP_RV730},
+	{0x1002, 0x9488, CHIP_RV730},
+	{0x1002, 0x9489, CHIP_RV730},
+	{0x1002, 0x948F, CHIP_RV730},
+	{0x1002, 0x9490, CHIP_RV730},
+	{0x1002, 0x9491, CHIP_RV730},
+	{0x1002, 0x9495, CHIP_RV730},
+	{0x1002, 0x9498, CHIP_RV730},
+	{0x1002, 0x949C, CHIP_RV730},
+	{0x1002, 0x949E, CHIP_RV730},
+	{0x1002, 0x949F, CHIP_RV730},
+	{0x1002, 0x94C0, CHIP_RV610},
+	{0x1002, 0x94C1, CHIP_RV610},
+	{0x1002, 0x94C3, CHIP_RV610},
+	{0x1002, 0x94C4, CHIP_RV610},
+	{0x1002, 0x94C5, CHIP_RV610},
+	{0x1002, 0x94C6, CHIP_RV610},
+	{0x1002, 0x94C7, CHIP_RV610},
+	{0x1002, 0x94C8, CHIP_RV610},
+	{0x1002, 0x94C9, CHIP_RV610},
+	{0x1002, 0x94CB, CHIP_RV610},
+	{0x1002, 0x94CC, CHIP_RV610},
+	{0x1002, 0x94CD, CHIP_RV610},
+	{0x1002, 0x9500, CHIP_RV670},
+	{0x1002, 0x9501, CHIP_RV670},
+	{0x1002, 0x9504, CHIP_RV670},
+	{0x1002, 0x9505, CHIP_RV670},
+	{0x1002, 0x9506, CHIP_RV670},
+	{0x1002, 0x9507, CHIP_RV670},
+	{0x1002, 0x9508, CHIP_RV670},
+	{0x1002, 0x9509, CHIP_RV670},
+	{0x1002, 0x950F, CHIP_RV670},
+	{0x1002, 0x9511, CHIP_RV670},
+	{0x1002, 0x9515, CHIP_RV670},
+	{0x1002, 0x9517, CHIP_RV670},
+	{0x1002, 0x9519, CHIP_RV670},
+	{0x1002, 0x9540, CHIP_RV710},
+	{0x1002, 0x9541, CHIP_RV710},
+	{0x1002, 0x9542, CHIP_RV710},
+	{0x1002, 0x954E, CHIP_RV710},
+	{0x1002, 0x954F, CHIP_RV710},
+	{0x1002, 0x9552, CHIP_RV710},
+	{0x1002, 0x9553, CHIP_RV710},
+	{0x1002, 0x9555, CHIP_RV710},
+	{0x1002, 0x9557, CHIP_RV710},
+	{0x1002, 0x9580, CHIP_RV630},
+	{0x1002, 0x9581, CHIP_RV630},
+	{0x1002, 0x9583, CHIP_RV630},
+	{0x1002, 0x9586, CHIP_RV630},
+	{0x1002, 0x9587, CHIP_RV630},
+	{0x1002, 0x9588, CHIP_RV630},
+	{0x1002, 0x9589, CHIP_RV630},
+	{0x1002, 0x958A, CHIP_RV630},
+	{0x1002, 0x958B, CHIP_RV630},
+	{0x1002, 0x958C, CHIP_RV630},
+	{0x1002, 0x958D, CHIP_RV630},
+	{0x1002, 0x958E, CHIP_RV630},
+	{0x1002, 0x958F, CHIP_RV630},
+	{0x1002, 0x9590, CHIP_RV635},
+	{0x1002, 0x9591, CHIP_RV635},
+	{0x1002, 0x9593, CHIP_RV635},
+	{0x1002, 0x9595, CHIP_RV635},
+	{0x1002, 0x9596, CHIP_RV635},
+	{0x1002, 0x9597, CHIP_RV635},
+	{0x1002, 0x9598, CHIP_RV635},
+	{0x1002, 0x9599, CHIP_RV635},
+	{0x1002, 0x959B, CHIP_RV635},
+	{0x1002, 0x95C0, CHIP_RV620},
+	{0x1002, 0x95C2, CHIP_RV620},
+	{0x1002, 0x95C4, CHIP_RV620},
+	{0x1002, 0x95C5, CHIP_RV620},
+	{0x1002, 0x95C6, CHIP_RV620},
+	{0x1002, 0x95C7, CHIP_RV620},
+	{0x1002, 0x95C9, CHIP_RV620},
+	{0x1002, 0x95CC, CHIP_RV620},
+	{0x1002, 0x95CD, CHIP_RV620},
+	{0x1002, 0x95CE, CHIP_RV620},
+	{0x1002, 0x95CF, CHIP_RV620},
+	{0x1002, 0x9610, CHIP_RS780},
+	{0x1002, 0x9611, CHIP_RS780},
+	{0x1002, 0x9612, CHIP_RS780},
+	{0x1002, 0x9613, CHIP_RS780},
+	{0x1002, 0x9614, CHIP_RS780},
+	{0x1002, 0x9615, CHIP_RS780},
+	{0x1002, 0x9616, CHIP_RS780},
+	{0x1002, 0x9710, CHIP_RS880},
+	{0x1002, 0x9711, CHIP_RS880},
+	{0x1002, 0x9712, CHIP_RS880},
+	{0x1002, 0x9713, CHIP_RS880},
+	{0x1002, 0x9714, CHIP_RS880},
+	{0x1002, 0x9715, CHIP_RS880},
+	{0, 0},
+};
+
+unsigned radeon_family_from_device(unsigned device)
+{
+	unsigned i;
+
+	for (i = 0; ; i++) {
+		if (!radeon_pci_id[i].vendor)
+			return CHIP_UNKNOWN;
+		if (radeon_pci_id[i].device == device)
+			return radeon_pci_id[i].family;
+	}
+	return CHIP_UNKNOWN;
+}
+
+int radeon_is_family_compatible(unsigned family1, unsigned family2)
+{
+	switch (family1) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		switch (family2) {
+		case CHIP_R600:
+		case CHIP_RV610:
+		case CHIP_RV630:
+		case CHIP_RV670:
+		case CHIP_RV620:
+		case CHIP_RV635:
+		case CHIP_RS780:
+		case CHIP_RS880:
+		case CHIP_RV770:
+		case CHIP_RV730:
+		case CHIP_RV710:
+		case CHIP_RV740:
+			return 1;
+		default:
+			return 0;
+		}
+		break;
+	case CHIP_R100:
+	case CHIP_RV100:
+	case CHIP_RS100:
+	case CHIP_RV200:
+	case CHIP_RS200:
+	case CHIP_R200:
+	case CHIP_RV250:
+	case CHIP_RS300:
+	case CHIP_RV280:
+	case CHIP_R300:
+	case CHIP_R350:
+	case CHIP_RV350:
+	case CHIP_RV380:
+	case CHIP_R420:
+	case CHIP_R423:
+	case CHIP_RV410:
+	case CHIP_RS400:
+	case CHIP_RS480:
+	case CHIP_RS600:
+	case CHIP_RS690:
+	case CHIP_RS740:
+	case CHIP_RV515:
+	case CHIP_R520:
+	case CHIP_RV530:
+	case CHIP_RV560:
+	case CHIP_RV570:
+	case CHIP_R580:
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+	default:
+		return 0;
+	}
+}