diff options
| author | Keith Whitwell <[email protected]> | 2010-10-17 19:03:42 -0700 |
|---|---|---|
| committer | Keith Whitwell <[email protected]> | 2010-10-17 19:09:42 -0700 |
| commit | 0072acd447dc6be652e63752e50215c3105322c8 (patch) | |
| tree | 847d1763b54772d336a04e606f8248291c3092b7 /src/gallium/winsys/r600/drm | |
| parent | 543fb77ddece7e1806e8eaa0d65bb2a945ef9a75 (diff) | |
| parent | ca2b2ac131933b4171b519813df1aaa3a81621cd (diff) | |
Merge remote branch 'origin/master' into lp-setup-llvm
Conflicts:
src/gallium/drivers/llvmpipe/lp_setup_coef.c
src/gallium/drivers/llvmpipe/lp_setup_coef.h
src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c
src/gallium/drivers/llvmpipe/lp_setup_point.c
src/gallium/drivers/llvmpipe/lp_setup_tri.c
src/gallium/drivers/llvmpipe/lp_state_derived.c
src/gallium/drivers/llvmpipe/lp_state_fs.h
Diffstat (limited to 'src/gallium/winsys/r600/drm')
25 files changed, 2986 insertions, 3918 deletions
diff --git a/src/gallium/winsys/r600/drm/Makefile b/src/gallium/winsys/r600/drm/Makefile index 9d8dc8dc594..a396205f897 100644 --- a/src/gallium/winsys/r600/drm/Makefile +++ b/src/gallium/winsys/r600/drm/Makefile @@ -6,18 +6,14 @@ LIBNAME = r600winsys C_SOURCES = \ bof.c \ - r600_state.c \ - r600_state2.c \ - r600.c \ - radeon_ctx.c \ - radeon_draw.c \ - radeon_state.c \ + evergreen_hw_context.c \ radeon_bo.c \ + radeon_bo_pb.c \ radeon_pciid.c \ - radeon.c \ + r600.c \ + r600_bo.c \ r600_drm.c \ - radeon_ws_bo.c \ - radeon_bo_pb.c + r600_hw_context.c LIBRARY_INCLUDES = -I$(TOP)/src/gallium/drivers/r600 \ $(shell pkg-config libdrm --cflags-only-I) diff --git a/src/gallium/winsys/r600/drm/SConscript b/src/gallium/winsys/r600/drm/SConscript index 2f20d9f8957..cc053c06dd0 100644 --- a/src/gallium/winsys/r600/drm/SConscript +++ b/src/gallium/winsys/r600/drm/SConscript @@ -4,14 +4,14 @@ env = env.Clone() r600_sources = [ 'bof.c', - 'r600_state.c', - 'radeon_ctx.c', - 'radeon_draw.c', - 'radeon_state.c', + 'evergreen_hw_context.c', 'radeon_bo.c', + 'radeon_bo_pb.c', 'radeon_pciid.c', - 'radeon.c', - 'r600_drm.c' + 'r600.c', + 'r600_bo.c', + 'r600_drm.c', + 'r600_hw_context.c', ] env.ParseConfig('pkg-config --cflags libdrm_radeon') diff --git a/src/gallium/winsys/r600/drm/eg_states.h b/src/gallium/winsys/r600/drm/eg_states.h deleted file mode 100644 index c26ba6c6cd0..00000000000 --- a/src/gallium/winsys/r600/drm/eg_states.h +++ /dev/null @@ -1,449 +0,0 @@ -/* - * Copyright © 2009 Jerome Glisse <[email protected]> - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of version 2 of the GNU General Public License - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. - */ -#ifndef EG_STATES_H -#define EG_STATES_H - -static const struct radeon_register EG_names_CONFIG[] = { - {0x00008C00, 0, 0, "SQ_CONFIG"}, - {0x00009100, 0, 0, "SPI_CONFIG_CNTL"}, - {0x0000913C, 0, 0, "SPI_CONFIG_CNTL_1"}, - {0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"}, - {0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"}, - {0x00008C0C, 0, 0, "SQ_GPR_RESOURCE_MGMT_3"}, - {0x00008C18, 0, 0, "SQ_THREAD_RESOURCE_MGMT_1"}, - {0x00008C1C, 0, 0, "SQ_THREAD_RESOURCE_MGMT_2"}, - {0x00008C20, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"}, - {0x00008C24, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"}, - {0x00008C28, 0, 0, "SQ_STACK_RESOURCE_MGMT_3"}, - {0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"}, - {0x00008A14, 0, 0, "PA_CL_ENHANCE"}, - {0x00028838, 0, 0, "SQ_DYN_GPR_RESOURCE_LIMIT_1"}, - {0x000288EC, 0, 0, "SQ_LDS_ALLOC_PS"}, - {0x00028350, 0, 0, "SX_MISC"}, - {0x00028900, 0, 0, "SQ_ESGS_RING_ITEMSIZE"}, - {0x00028904, 0, 0, "SQ_GSVS_RING_ITEMSIZE"}, - {0x00028908, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"}, - {0x0002890C, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"}, - {0x00028910, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"}, - {0x00028914, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"}, - {0x0002891C, 0, 0, "SQ_GS_VERT_ITEMSIZE"}, - {0x00028920, 0, 0, "SQ_GS_VERT_ITEMSIZE_1"}, - {0x00028924, 0, 0, "SQ_GS_VERT_ITEMSIZE_2"}, - {0x00028928, 0, 0, "SQ_GS_VERT_ITEMSIZE_3"}, - {0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"}, - {0x00028A14, 0, 0, "VGT_HOS_CNTL"}, - {0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"}, - {0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"}, - {0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"}, - {0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"}, - {0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"}, - {0x00028A2C, 0, 0, "VGT_GROUP_DECR"}, - {0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"}, - {0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"}, - {0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"}, - {0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"}, - {0x00028A40, 0, 0, "VGT_GS_MODE"}, - {0x00028A48, 0, 0, "PA_SC_MODE_CNTL_0"}, - {0x00028A4C, 0, 0, "PA_SC_MODE_CNTL_1"}, - {0x00028AB4, 0, 0, "VGT_REUSE_OFF"}, - {0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"}, - {0x00028B54, 0, 0, "VGT_SHADER_STAGES_EN"}, - {0x00028B94, 0, 0, "VGT_STRMOUT_CONFIG"}, - {0x00028B98, 0, 0, "VGT_STRMOUT_BUFFER_CONFIG"}, -}; - -static const struct radeon_register EG_names_CB_CNTL[] = { - {0x00028238, 0, 0, "CB_TARGET_MASK"}, - {0x0002823C, 0, 0, "CB_SHADER_MASK"}, - {0x00028808, 0, 0, "CB_COLOR_CONTROL"}, - {0x00028C04, 0, 0, "PA_SC_AA_CONFIG"}, - {0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"}, - {0x00028C3C, 0, 0, "PA_SC_AA_MASK"}, -}; - -static const struct radeon_register EG_names_RASTERIZER[] = { - {0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"}, - {0x00028810, 0, 0, "PA_CL_CLIP_CNTL"}, - {0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"}, - {0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"}, - {0x00028820, 0, 0, "PA_CL_NANINF_CNTL"}, - {0x00028A00, 0, 0, "PA_SU_POINT_SIZE"}, - {0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"}, - {0x00028A08, 0, 0, "PA_SU_LINE_CNTL"}, - {0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"}, - {0x00028C00, 0, 0, "PA_SC_LINE_CNTL"}, - {0x00028C08, 0, 0, "PA_SU_VTX_CNTL"}, - {0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"}, - {0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"}, - {0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"}, - {0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"}, - {0x00028B78, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"}, - {0x00028B7C, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"}, - {0x00028B80, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"}, - {0x00028B84, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"}, - {0x00028B88, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"}, - {0x00028B8C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"}, -}; - -/* Viewport states are same as r600 */ -static const struct radeon_register EG_names_VIEWPORT[] = { - {0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"}, - {0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"}, - {0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"}, - {0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"}, - {0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"}, - {0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"}, - {0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"}, - {0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"}, - {0x00028818, 0, 0, "PA_CL_VTE_CNTL"}, -}; - -/* scissor is same as R600 */ -static const struct radeon_register EG_names_SCISSOR[] = { - {0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"}, - {0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"}, - {0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"}, - {0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"}, - {0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"}, - {0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"}, - {0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"}, - {0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"}, - {0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"}, - {0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"}, - {0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"}, - {0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"}, - {0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"}, - {0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"}, - {0x00028230, 0, 0, "PA_SC_EDGERULE"}, - {0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"}, - {0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"}, - {0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"}, - {0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"}, - {0x00028234, 0, 0, "PA_SU_HARDWARE_SCREEN_OFFSET"}, -}; - -/* same as r700 i.e. no blend control */ -static const struct radeon_register EG_names_BLEND[] = { - {0x00028414, 0, 0, "CB_BLEND_RED"}, - {0x00028418, 0, 0, "CB_BLEND_GREEN"}, - {0x0002841C, 0, 0, "CB_BLEND_BLUE"}, - {0x00028420, 0, 0, "CB_BLEND_ALPHA"}, - {0x00028780, 0, 0, "CB_BLEND0_CONTROL"}, - {0x00028784, 0, 0, "CB_BLEND1_CONTROL"}, - {0x00028788, 0, 0, "CB_BLEND2_CONTROL"}, - {0x0002878C, 0, 0, "CB_BLEND3_CONTROL"}, - {0x00028790, 0, 0, "CB_BLEND4_CONTROL"}, - {0x00028794, 0, 0, "CB_BLEND5_CONTROL"}, - {0x00028798, 0, 0, "CB_BLEND6_CONTROL"}, - {0x0002879C, 0, 0, "CB_BLEND7_CONTROL"}, -}; - -/* different */ -static const struct radeon_register EG_names_DSA[] = { - {0x00028028, 0, 0, "DB_STENCIL_CLEAR"}, - {0x0002802C, 0, 0, "DB_DEPTH_CLEAR"}, - {0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"}, - {0x00028430, 0, 0, "DB_STENCILREFMASK"}, - {0x00028434, 0, 0, "DB_STENCILREFMASK_BF"}, - {0x00028438, 0, 0, "SX_ALPHA_REF"}, - {0x000286DC, 0, 0, "SPI_FOG_CNTL"}, - {0x00028800, 0, 0, "DB_DEPTH_CONTROL"}, - {0x0002880C, 0, 0, "DB_SHADER_CONTROL"}, - {0x00028000, 0, 0, "DB_RENDER_CONTROL"}, - {0x0002800C, 0, 0, "DB_RENDER_OVERRIDE"}, - {0x00028010, 0, 0, "DB_RENDER_OVERRIDE2"}, - {0x00028AC0, 0, 0, "DB_SRESULTS_COMPARE_STATE0"}, - {0x00028AC4, 0, 0, "DB_SRESULTS_COMPARE_STATE1"}, - {0x00028AC8, 0, 0, "DB_PRELOAD_CONTROL"}, - {0x00028B70, 0, 0, "DB_ALPHA_TO_MASK"}, -}; - -/* different */ -static const struct radeon_register EG_names_VS_SHADER[] = { - {0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"}, - {0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"}, - {0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"}, - {0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"}, - {0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"}, - {0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"}, - {0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"}, - {0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"}, - {0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"}, - {0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"}, - {0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"}, - {0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"}, - {0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"}, - {0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"}, - {0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"}, - {0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"}, - {0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"}, - {0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"}, - {0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"}, - {0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"}, - {0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"}, - {0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"}, - {0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"}, - {0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"}, - {0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"}, - {0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"}, - {0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"}, - {0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"}, - {0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"}, - {0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"}, - {0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"}, - {0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"}, - {0x0002861C, 0, 0, "SPI_VS_OUT_ID_0"}, // all diff belwo - {0x00028620, 0, 0, "SPI_VS_OUT_ID_1"}, - {0x00028624, 0, 0, "SPI_VS_OUT_ID_2"}, - {0x00028628, 0, 0, "SPI_VS_OUT_ID_3"}, - {0x0002862C, 0, 0, "SPI_VS_OUT_ID_4"}, - {0x00028630, 0, 0, "SPI_VS_OUT_ID_5"}, - {0x00028634, 0, 0, "SPI_VS_OUT_ID_6"}, - {0x00028638, 0, 0, "SPI_VS_OUT_ID_7"}, - {0x0002863C, 0, 0, "SPI_VS_OUT_ID_8"}, - {0x00028640, 0, 0, "SPI_VS_OUT_ID_9"}, - {0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"}, - {0x0002885C, 1, 0, "SQ_PGM_START_VS"}, - {0x00028860, 0, 0, "SQ_PGM_RESOURCES_VS"}, - {0x00028864, 0, 0, "SQ_PGM_RESOURCES_2_VS"}, - {0x000288A4, 1, 1, "SQ_PGM_START_FS"}, - {0x000288A8, 0, 0, "SQ_PGM_RESOURCES_FS"}, -}; - -static const struct radeon_register EG_names_PS_SHADER[] = { - {0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"}, - {0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"}, - {0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"}, - {0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"}, - {0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"}, - {0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"}, - {0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"}, - {0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"}, - {0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"}, - {0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"}, - {0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"}, - {0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"}, - {0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"}, - {0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"}, - {0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"}, - {0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"}, - {0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"}, - {0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"}, - {0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"}, - {0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"}, - {0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"}, - {0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"}, - {0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"}, - {0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"}, - {0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"}, - {0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"}, - {0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"}, - {0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"}, - {0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"}, - {0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"}, - {0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"}, - {0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"}, - {0x000286C8, 0, 0, "SPI_THREAD_GROUPING"}, - {0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"}, - {0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"}, - {0x000286D8, 0, 0, "SPI_INPUT_Z"}, - {0x000286E0, 0, 0, "SPI_BARYC_CNTL"}, - {0x000286E4, 0, 0, "SPI_PS_IN_CONTROL_2"}, - {0x000286E8, 0, 0, "SPI_COMPUTE_INPUT_CNTL"}, - {0x00028840, 1, 0, "SQ_PGM_START_PS"}, // diff - {0x00028844, 0, 0, "SQ_PGM_RESOURCES_PS"}, // diff - {0x00028848, 0, 0, "SQ_PGM_RESOURCES_2_PS"}, // diff - {0x0002884C, 0, 0, "SQ_PGM_EXPORTS_PS"}, // diff -}; - -/* different */ -static const struct radeon_register EG_names_UCP[] = { - {0x000285BC, 0, 0, "PA_CL_UCP0_X"}, - {0x000285C0, 0, 0, "PA_CL_UCP0_Y"}, - {0x000285C4, 0, 0, "PA_CL_UCP0_Z"}, - {0x000285C8, 0, 0, "PA_CL_UCP0_W"}, - {0x000285CC, 0, 0, "PA_CL_UCP1_X"}, - {0x000285D0, 0, 0, "PA_CL_UCP1_Y"}, - {0x000285D4, 0, 0, "PA_CL_UCP1_Z"}, - {0x000285D8, 0, 0, "PA_CL_UCP1_W"}, - {0x000285DC, 0, 0, "PA_CL_UCP2_X"}, - {0x000285E0, 0, 0, "PA_CL_UCP2_Y"}, - {0x000285E4, 0, 0, "PA_CL_UCP2_Z"}, - {0x000285E8, 0, 0, "PA_CL_UCP2_W"}, - {0x000285EC, 0, 0, "PA_CL_UCP3_X"}, - {0x000285F0, 0, 0, "PA_CL_UCP3_Y"}, - {0x000285F4, 0, 0, "PA_CL_UCP3_Z"}, - {0x000285F8, 0, 0, "PA_CL_UCP3_W"}, - {0x000285FC, 0, 0, "PA_CL_UCP4_X"}, - {0x00028600, 0, 0, "PA_CL_UCP4_Y"}, - {0x00028604, 0, 0, "PA_CL_UCP4_Z"}, - {0x00028608, 0, 0, "PA_CL_UCP4_W"}, - {0x0002860C, 0, 0, "PA_CL_UCP5_X"}, - {0x00028610, 0, 0, "PA_CL_UCP5_Y"}, - {0x00028614, 0, 0, "PA_CL_UCP5_Z"}, - {0x0002861C, 0, 0, "PA_CL_UCP5_W"}, -}; - -static const struct radeon_register EG_names_VS_CBUF[] = { - {0x00028180, 0, 0, "ALU_CONST_BUFFER_SIZE_VS_0"}, - {0x00028980, 1, 0, "ALU_CONST_CACHE_VS_0"}, -}; - -static const struct radeon_register EG_names_PS_CBUF[] = { - {0x00028140, 0, 0, "ALU_CONST_BUFFER_SIZE_PS_0"}, - {0x00028940, 1, 0, "ALU_CONST_CACHE_PS_0"}, -}; - -static const struct radeon_register EG_names_PS_RESOURCE[] = { - {0x00030000, 0, 0, "RESOURCE0_WORD0"}, - {0x00030004, 0, 0, "RESOURCE0_WORD1"}, - {0x00030008, 0, 0, "RESOURCE0_WORD2"}, - {0x0003000C, 0, 0, "RESOURCE0_WORD3"}, - {0x00030010, 0, 0, "RESOURCE0_WORD4"}, - {0x00030014, 0, 0, "RESOURCE0_WORD5"}, - {0x00030018, 0, 0, "RESOURCE0_WORD6"}, - {0x0003001c, 0, 0, "RESOURCE0_WORD7"}, -}; - -static const struct radeon_register EG_names_VS_RESOURCE[] = { - {0x00031600, 0, 0, "RESOURCE160_WORD0"}, - {0x00031604, 0, 0, "RESOURCE160_WORD1"}, - {0x00031608, 0, 0, "RESOURCE160_WORD2"}, - {0x0003160C, 0, 0, "RESOURCE160_WORD3"}, - {0x00031610, 0, 0, "RESOURCE160_WORD4"}, - {0x00031614, 0, 0, "RESOURCE160_WORD5"}, - {0x00031618, 0, 0, "RESOURCE160_WORD6"}, - {0x0003161c, 0, 0, "RESOURCE160_WORD7"}, -}; - -static const struct radeon_register EG_names_FS_RESOURCE[] = { - {0x0003A300, 0, 0, "RESOURCE320_WORD0"}, - {0x0003A304, 0, 0, "RESOURCE320_WORD1"}, - {0x0003A308, 0, 0, "RESOURCE320_WORD2"}, - {0x0003A30C, 0, 0, "RESOURCE320_WORD3"}, - {0x0003A310, 0, 0, "RESOURCE320_WORD4"}, - {0x0003A314, 0, 0, "RESOURCE320_WORD5"}, - {0x0003A318, 0, 0, "RESOURCE320_WORD6"}, - {0x0003A31C, 0, 0, "RESOURCE320_WORD7"}, -}; - -static const struct radeon_register EG_names_GS_RESOURCE[] = { - {0x0003A4C0, 0, 0, "RESOURCE336_WORD0"}, - {0x0003A4C4, 0, 0, "RESOURCE336_WORD1"}, - {0x0003A4C8, 0, 0, "RESOURCE336_WORD2"}, - {0x0003A4CC, 0, 0, "RESOURCE336_WORD3"}, - {0x0003A4D0, 0, 0, "RESOURCE336_WORD4"}, - {0x0003A4D4, 0, 0, "RESOURCE336_WORD5"}, - {0x0003A4D8, 0, 0, "RESOURCE336_WORD6"}, - {0x0003A4DC, 0, 0, "RESOURCE336_WORD7"}, -}; - -static const struct radeon_register EG_names_PS_SAMPLER[] = { - {0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"}, - {0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"}, - {0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"}, -}; - -static const struct radeon_register EG_names_VS_SAMPLER[] = { - {0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"}, - {0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"}, - {0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"}, -}; - -static const struct radeon_register EG_names_GS_SAMPLER[] = { - {0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"}, - {0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"}, - {0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"}, -}; - -static const struct radeon_register EG_names_PS_SAMPLER_BORDER[] = { - {0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"}, - {0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"}, - {0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"}, - {0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"}, -}; - -static const struct radeon_register EG_names_VS_SAMPLER_BORDER[] = { - {0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"}, - {0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"}, - {0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"}, - {0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"}, -}; - -static const struct radeon_register EG_names_GS_SAMPLER_BORDER[] = { - {0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"}, - {0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"}, - {0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"}, - {0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"}, -}; - -static const struct radeon_register EG_names_CB[] = { - {0x00028C60, 1, 0, "CB_COLOR0_BASE"}, - {0x00028C64, 0, 0, "CB_COLOR0_PITCH"}, - {0x00028C68, 0, 0, "CB_COLOR0_SLICE"}, - {0x00028C6C, 0, 0, "CB_COLOR0_VIEW"}, - {0x00028C70, 1, 0, "CB_COLOR0_INFO"}, - {0x00028C74, 0, 0, "CB_COLOR0_ATTRIB"}, - {0x00028C78, 0, 0, "CB_COLOR0_DIM"}, -}; - -/* different - TODO */ -static const struct radeon_register EG_names_DB[] = { - {0x00028014, 1, 0, "DB_HTILE_DATA_BASE"}, - {0x00028040, 1, 0, "DB_Z_INFO"}, - {0x00028044, 0, 0, "DB_STENCIL_INFO"}, - {0x00028058, 0, 0, "DB_DEPTH_SIZE"}, - {0x0002805C, 0, 0, "DB_DEPTH_SLICE"}, - {0x00028008, 0, 0, "DB_DEPTH_VIEW"}, - {0x00028ABC, 0, 0, "DB_HTILE_SURFACE"}, - {0x00028048, 1, 0, "DB_Z_READ_BASE"}, - {0x0002804C, 1, 0, "DB_STENCIL_READ_BASE"}, - {0x00028050, 1, 0, "DB_Z_WRITE_BASE"}, - {0x00028054, 1, 0, "DB_STENCIL_WRITE_BASE"}, -}; - -static const struct radeon_register EG_names_VGT[] = { - {0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"}, //s - {0x00028400, 0, 0, "VGT_MAX_VTX_INDX"}, //s - {0x00028404, 0, 0, "VGT_MIN_VTX_INDX"}, //s - {0x00028408, 0, 0, "VGT_INDX_OFFSET"}, //s - {0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"}, //s - {0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"}, //s - {0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"}, //s - {0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"}, //s - {0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"}, //s - {0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"}, //s -}; - -static const struct radeon_register EG_names_DRAW[] = { - {0x00008970, 0, 0, "VGT_NUM_INDICES"}, - {0x000287E4, 0, 0, "VGT_DMA_BASE_HI"}, //same - {0x000287E8, 1, 0, "VGT_DMA_BASE"}, //same - {0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"}, //same -}; - -static const struct radeon_register EG_names_VGT_EVENT[] = { - {0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"}, //done -}; - -static const struct radeon_register EG_names_CB_FLUSH[] = { -}; - -static const struct radeon_register EG_names_DB_FLUSH[] = { -}; - -#endif diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c new file mode 100644 index 00000000000..7f21b53ace0 --- /dev/null +++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c @@ -0,0 +1,919 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <errno.h> +#include <stdint.h> +#include <string.h> +#include <stdlib.h> +#include <assert.h> +#include "xf86drm.h" +#include "r600.h" +#include "evergreend.h" +#include "radeon_drm.h" +#include "bof.h" +#include "pipe/p_compiler.h" +#include "util/u_inlines.h" +#include "util/u_memory.h" +#include <pipebuffer/pb_bufmgr.h> +#include "r600_priv.h" + +#define GROUP_FORCE_NEW_BLOCK 0 + +static const struct r600_reg evergreen_config_reg_list[] = { + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008A14_PA_CL_ENHANCE, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C20_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C24_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C28_SQ_STACK_RESOURCE_MGMT_3, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_009100_SPI_CONFIG_CNTL, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_00913C_SPI_CONFIG_CNTL_1, 0, 0, 0}, +}; + +static const struct r600_reg evergreen_ctl_const_list[] = { + {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, + {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, +}; + +static const struct r600_reg evergreen_context_reg_list[] = { + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028000_DB_RENDER_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028004_DB_COUNT_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028008_DB_DEPTH_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028014_DB_HTILE_DATA_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028040_DB_Z_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028044_DB_STENCIL_INFO, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028048_DB_Z_READ_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02804C_DB_STENCIL_READ_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028050_DB_Z_WRITE_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028054_DB_STENCIL_WRITE_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028058_DB_DEPTH_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02805C_DB_DEPTH_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285BC_PA_CL_UCP0_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C0_PA_CL_UCP0_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C4_PA_CL_UCP0_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C8_PA_CL_UCP0_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285CC_PA_CL_UCP1_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D0_PA_CL_UCP1_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D4_PA_CL_UCP1_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D8_PA_CL_UCP1_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285DC_PA_CL_UCP2_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E0_PA_CL_UCP2_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E4_PA_CL_UCP2_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E8_PA_CL_UCP2_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285EC_PA_CL_UCP3_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F0_PA_CL_UCP3_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F4_PA_CL_UCP3_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F8_PA_CL_UCP3_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285FC_PA_CL_UCP4_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028600_PA_CL_UCP4_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028604_PA_CL_UCP4_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028608_PA_CL_UCP4_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02860C_PA_CL_UCP5_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028610_PA_CL_UCP5_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028614_PA_CL_UCP5_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028618_PA_CL_UCP5_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_5, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_6, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_7, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028640_SPI_VS_OUT_ID_9, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E0_SPI_BARYC_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02885C_SQ_PGM_START_VS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_START_FS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028ABC_DB_HTILE_SURFACE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C3C_PA_SC_AA_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C60_CB_COLOR0_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C64_CB_COLOR0_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C68_CB_COLOR0_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C6C_CB_COLOR0_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C70_CB_COLOR0_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C74_CB_COLOR0_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C78_CB_COLOR0_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C9C_CB_COLOR1_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA0_CB_COLOR1_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA4_CB_COLOR1_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA8_CB_COLOR1_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CAC_CB_COLOR1_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CB0_CB_COLOR1_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CB4_CB_COLOR1_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CD8_CB_COLOR2_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CDC_CB_COLOR2_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE0_CB_COLOR2_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE4_CB_COLOR2_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE8_CB_COLOR2_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CEC_CB_COLOR2_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CF0_CB_COLOR2_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D14_CB_COLOR3_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D18_CB_COLOR3_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D1C_CB_COLOR3_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D20_CB_COLOR3_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D24_CB_COLOR3_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D28_CB_COLOR3_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D2C_CB_COLOR3_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D50_CB_COLOR4_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D54_CB_COLOR4_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D58_CB_COLOR4_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D5C_CB_COLOR4_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D60_CB_COLOR4_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D64_CB_COLOR4_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D68_CB_COLOR4_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D8C_CB_COLOR5_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D90_CB_COLOR5_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D94_CB_COLOR5_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D98_CB_COLOR5_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D9C_CB_COLOR5_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DA0_CB_COLOR5_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DA4_CB_COLOR5_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DC8_CB_COLOR6_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DCC_CB_COLOR6_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD0_CB_COLOR6_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD4_CB_COLOR6_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD8_CB_COLOR6_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DDC_CB_COLOR6_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DE0_CB_COLOR6_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E04_CB_COLOR7_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E08_CB_COLOR7_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E0C_CB_COLOR7_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E10_CB_COLOR7_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E14_CB_COLOR7_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E18_CB_COLOR7_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E1C_CB_COLOR7_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E40_CB_COLOR8_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E44_CB_COLOR8_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E48_CB_COLOR8_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E4C_CB_COLOR8_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E50_CB_COLOR8_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E54_CB_COLOR8_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E58_CB_COLOR8_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E5C_CB_COLOR9_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E60_CB_COLOR9_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E64_CB_COLOR9_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E68_CB_COLOR9_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E6C_CB_COLOR9_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E70_CB_COLOR9_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E74_CB_COLOR9_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E78_CB_COLOR10_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E7C_CB_COLOR10_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E80_CB_COLOR10_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E84_CB_COLOR10_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E88_CB_COLOR10_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E8C_CB_COLOR10_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E90_CB_COLOR10_DIM, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E94_CB_COLOR11_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E98_CB_COLOR11_PITCH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E9C_CB_COLOR11_SLICE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA0_CB_COLOR11_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA4_CB_COLOR11_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA8_CB_COLOR11_ATTRIB, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EAC_CB_COLOR11_DIM, 0, 0, 0}, +}; + +/* SHADER RESOURCE R600/R700 */ +static int evergreen_state_resource_init(struct r600_context *ctx, u32 offset) +{ + struct r600_reg r600_shader_resource[] = { + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030000_RESOURCE0_WORD0, 0, 0, 0}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030004_RESOURCE0_WORD1, 0, 0, 0}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030008_RESOURCE0_WORD2, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_03000C_RESOURCE0_WORD3, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030010_RESOURCE0_WORD4, 0, 0, 0}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030014_RESOURCE0_WORD5, 0, 0, 0}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030018_RESOURCE0_WORD6, 0, 0, 0}, + {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_03001C_RESOURCE0_WORD7, 0, 0, 0}, + }; + unsigned nreg = Elements(r600_shader_resource); + + for (int i = 0; i < nreg; i++) { + r600_shader_resource[i].offset += offset; + } + return r600_context_add_block(ctx, r600_shader_resource, nreg); +} + +/* SHADER SAMPLER R600/R700 */ +static int r600_state_sampler_init(struct r600_context *ctx, u32 offset) +{ + struct r600_reg r600_shader_sampler[] = { + {PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, + {PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, + {PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, + }; + unsigned nreg = Elements(r600_shader_sampler); + + for (int i = 0; i < nreg; i++) { + r600_shader_sampler[i].offset += offset; + } + return r600_context_add_block(ctx, r600_shader_sampler, nreg); +} + +/* SHADER SAMPLER BORDER R600/R700 */ +static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 offset, unsigned id) +{ + struct r600_reg r600_shader_sampler_border[] = { + {PKT3_SET_CONFIG_REG, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, 0, R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, 0, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, 0, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, 0, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, + }; + unsigned nreg = Elements(r600_shader_sampler_border); + unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C; + struct r600_range *range; + struct r600_block *block; + int r; + + for (int i = 0; i < nreg; i++) { + r600_shader_sampler_border[i].offset -= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX; + r600_shader_sampler_border[i].offset += fake_offset; + } + r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg); + if (r) { + return r; + } + /* set proper offset */ + range = &ctx->range[CTX_RANGE_ID(ctx, r600_shader_sampler_border[0].offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, r600_shader_sampler_border[0].offset)]; + block->pm4[1] = (offset - EVERGREEN_CONFIG_REG_OFFSET) >> 2; + return 0; +} + +static int evergreen_loop_const_init(struct r600_context *ctx, u32 offset) +{ + unsigned nreg = 32; + struct r600_reg r600_loop_consts[32]; + int i; + + for (i = 0; i < nreg; i++) { + r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST; + r600_loop_consts[i].offset_base = EVERGREEN_LOOP_CONST_OFFSET; + r600_loop_consts[i].offset = EVERGREEN_LOOP_CONST_OFFSET + ((offset + i) * 4); + r600_loop_consts[i].need_bo = 0; + r600_loop_consts[i].flush_flags = 0; + } + return r600_context_add_block(ctx, r600_loop_consts, nreg); +} + +int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon) +{ + int r; + + memset(ctx, 0, sizeof(struct r600_context)); + ctx->radeon = radeon; + LIST_INITHEAD(&ctx->query_list); + + /* initialize hash */ + ctx->hash_size = 19; + ctx->hash_shift = 11; + for (int i = 0; i < 256; i++) { + ctx->range[i].start_offset = i << ctx->hash_shift; + ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1; + ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*)); + if (ctx->range[i].blocks == NULL) { + return -ENOMEM; + } + } + + /* add blocks */ + r = r600_context_add_block(ctx, evergreen_config_reg_list, + Elements(evergreen_config_reg_list)); + if (r) + goto out_err; + r = r600_context_add_block(ctx, evergreen_context_reg_list, + Elements(evergreen_context_reg_list)); + if (r) + goto out_err; + r = r600_context_add_block(ctx, evergreen_ctl_const_list, + Elements(evergreen_ctl_const_list)); + if (r) + goto out_err; + + + /* PS SAMPLER */ + for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) { + r = r600_state_sampler_init(ctx, offset); + if (r) + goto out_err; + } + /* VS SAMPLER */ + for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) { + r = r600_state_sampler_init(ctx, offset); + if (r) + goto out_err; + } + /* PS SAMPLER BORDER */ + for (int j = 0; j < 18; j++) { + r = evergreen_state_sampler_border_init(ctx, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, j); + if (r) + goto out_err; + } + /* VS SAMPLER BORDER */ + for (int j = 0; j < 18; j++) { + r = evergreen_state_sampler_border_init(ctx, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, j); + if (r) + goto out_err; + } + /* PS RESOURCE */ + for (int j = 0, offset = 0; j < 176; j++, offset += 0x20) { + r = evergreen_state_resource_init(ctx, offset); + if (r) + goto out_err; + } + /* VS RESOURCE */ + for (int j = 0, offset = 0x1600; j < 160; j++, offset += 0x20) { + r = evergreen_state_resource_init(ctx, offset); + if (r) + goto out_err; + } + + /* PS loop const */ + evergreen_loop_const_init(ctx, 0); + /* VS loop const */ + evergreen_loop_const_init(ctx, 32); + + /* setup block table */ + ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); + for (int i = 0, c = 0; i < 256; i++) { + for (int j = 0; j < (1 << ctx->hash_shift); j++) { + if (ctx->range[i].blocks[j]) { + assert(c < ctx->nblocks); + ctx->blocks[c++] = ctx->range[i].blocks[j]; + j += (ctx->range[i].blocks[j]->nreg << 2) - 1; + } + } + } + + /* allocate cs variables */ + ctx->nreloc = RADEON_CTX_MAX_PM4; + ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc)); + if (ctx->reloc == NULL) { + r = -ENOMEM; + goto out_err; + } + ctx->bo = calloc(ctx->nreloc, sizeof(void *)); + if (ctx->bo == NULL) { + r = -ENOMEM; + goto out_err; + } + ctx->pm4_ndwords = RADEON_CTX_MAX_PM4; + ctx->pm4 = calloc(ctx->pm4_ndwords, 4); + if (ctx->pm4 == NULL) { + r = -ENOMEM; + goto out_err; + } + /* save 16dwords space for fence mecanism */ + ctx->pm4_ndwords -= 16; + + r = r600_context_init_fence(ctx); + if (r) { + goto out_err; + } + + /* init dirty list */ + LIST_INITHEAD(&ctx->dirty); + return 0; +out_err: + r600_context_fini(ctx); + return r; +} + +static inline void evergreen_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + if (state == NULL) { + block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); + r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); + LIST_DELINIT(&block->list); + return; + } + block->reg[0] = state->regs[0].value; + block->reg[1] = state->regs[1].value; + block->reg[2] = state->regs[2].value; + block->reg[3] = state->regs[3].value; + block->reg[4] = state->regs[4].value; + block->reg[5] = state->regs[5].value; + block->reg[6] = state->regs[6].value; + block->reg[7] = state->regs[7].value; + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); + r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); + if (state->regs[0].bo) { + /* VERTEX RESOURCE, we preted there is 2 bo to relocate so + * we have single case btw VERTEX & TEXTURE resource + */ + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo); + r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo); + } else { + /* TEXTURE RESOURCE */ + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo); + r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo); + } + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x20 * rid; + + evergreen_context_pipe_state_set_resource(ctx, state, offset); +} + +void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x1600 + 0x20 * rid; + + evergreen_context_pipe_state_set_resource(ctx, state, offset); +} + +static inline void evergreen_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + if (state == NULL) { + block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + LIST_DELINIT(&block->list); + return; + } + block->reg[0] = state->regs[0].value; + block->reg[1] = state->regs[1].value; + block->reg[2] = state->regs[2].value; + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset, unsigned id) +{ + unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C; + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, fake_offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, fake_offset)]; + if (state == NULL) { + block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + LIST_DELINIT(&block->list); + return; + } + if (state->nregs <= 3) { + return; + } + block->reg[0] = id; + block->reg[1] = state->regs[3].value; + block->reg[2] = state->regs[4].value; + block->reg[3] = state->regs[5].value; + block->reg[4] = state->regs[6].value; + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) +{ + unsigned offset; + + offset = 0x0003C000 + id * 0xc; + evergreen_context_pipe_state_set_sampler(ctx, state, offset); + evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, id); +} + +void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) +{ + unsigned offset; + + offset = 0x0003C0D8 + id * 0xc; + evergreen_context_pipe_state_set_sampler(ctx, state, offset); + evergreen_context_pipe_state_set_sampler_border(ctx, state, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, id); +} + + +void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw) +{ + struct r600_bo *cb[12]; + struct r600_bo *db; + unsigned ndwords = 9, flush; + struct r600_block *dirty_block = NULL; + struct r600_block *next_block; + + if (draw->indices) { + ndwords = 13; + /* make sure there is enough relocation space before scheduling draw */ + if (ctx->creloc >= (ctx->nreloc - 1)) { + r600_context_flush(ctx); + } + } + + /* find number of color buffer */ + db = r600_context_reg_bo(ctx, R_028048_DB_Z_READ_BASE); + cb[0] = r600_context_reg_bo(ctx, R_028C60_CB_COLOR0_BASE); + cb[1] = r600_context_reg_bo(ctx, R_028C9C_CB_COLOR1_BASE); + cb[2] = r600_context_reg_bo(ctx, R_028CD8_CB_COLOR2_BASE); + cb[3] = r600_context_reg_bo(ctx, R_028D14_CB_COLOR3_BASE); + cb[4] = r600_context_reg_bo(ctx, R_028D50_CB_COLOR4_BASE); + cb[5] = r600_context_reg_bo(ctx, R_028D8C_CB_COLOR5_BASE); + cb[6] = r600_context_reg_bo(ctx, R_028DC8_CB_COLOR6_BASE); + cb[7] = r600_context_reg_bo(ctx, R_028E04_CB_COLOR7_BASE); + cb[8] = r600_context_reg_bo(ctx, R_028E40_CB_COLOR8_BASE); + cb[9] = r600_context_reg_bo(ctx, R_028E5C_CB_COLOR9_BASE); + cb[10] = r600_context_reg_bo(ctx, R_028E78_CB_COLOR10_BASE); + cb[11] = r600_context_reg_bo(ctx, R_028E94_CB_COLOR11_BASE); + for (int i = 0; i < 12; i++) { + if (cb[i]) { + ndwords += 7; + } + } + if (db) + ndwords += 7; + + /* queries need some special values */ + if (ctx->num_query_running) { + r600_context_reg(ctx, + R_028004_DB_COUNT_CONTROL, + S_028004_PERFECT_ZPASS_COUNTS(1), + S_028004_PERFECT_ZPASS_COUNTS(1)); + r600_context_reg(ctx, + R_02800C_DB_RENDER_OVERRIDE, + S_02800C_NOOP_CULL_DISABLE(1), + S_02800C_NOOP_CULL_DISABLE(1)); + } + + if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) { + /* need to flush */ + r600_context_flush(ctx); + } + /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */ + if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) { + R600_ERR("context is too big to be scheduled\n"); + return; + } + + /* enough room to copy packet */ + LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty,list) { + r600_context_block_emit_dirty(ctx, dirty_block); + } + + /* draw packet */ + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0); + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0); + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances; + if (draw->indices) { + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3); + ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices); + ctx->pm4[ctx->pm4_cdwords++] = 0; + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices; + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = 0; + r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices); + } else { + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1); + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices; + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; + } + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0); + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; + + /* flush color buffer */ + for (int i = 0; i < 12; i++) { + if (cb[i]) { + if (i > 7) { + flush = (S_0085F0_CB8_DEST_BASE_ENA(1) << (i - 8)) | + S_0085F0_CB_ACTION_ENA(1); + } else { + flush = (S_0085F0_CB0_DEST_BASE_ENA(1) << i) | + S_0085F0_CB_ACTION_ENA(1); + } + r600_context_bo_flush(ctx, flush, 0, cb[i]); + } + } + if (db) { + r600_context_bo_flush(ctx, + S_0085F0_DB_ACTION_ENA(1) | + S_0085F0_DB_DEST_BASE_ENA(1), + 0, db); + } + + /* all dirty state have been scheduled in current cs */ + ctx->pm4_dirty_cdwords = 0; +} + +static inline void evergreen_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + block->reg[0] = state->regs[0].value; + block->reg[1] = state->regs[1].value; + block->reg[2] = state->regs[2].value; + block->reg[3] = state->regs[3].value; + block->reg[4] = state->regs[4].value; + block->reg[5] = state->regs[5].value; + block->reg[6] = state->regs[6].value; + block->reg[7] = state->regs[7].value; + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); + r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); + if (state->regs[0].bo) { + /* VERTEX RESOURCE, we preted there is 2 bo to relocate so + * we have single case btw VERTEX & TEXTURE resource + */ + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo); + r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo); + } else { + /* TEXTURE RESOURCE */ + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo); + r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo); + } + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_030000_RESOURCE0_WORD0 + 0x20 * rid; + + evergreen_resource_set(ctx, state, offset); +} + +void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_030000_RESOURCE0_WORD0 + 0x1600 + 0x20 * rid; + + evergreen_resource_set(ctx, state, offset); +} diff --git a/src/gallium/winsys/r600/drm/gen_eg_states.py b/src/gallium/winsys/r600/drm/gen_eg_states.py deleted file mode 100644 index b2e5b2203a4..00000000000 --- a/src/gallium/winsys/r600/drm/gen_eg_states.py +++ /dev/null @@ -1,39 +0,0 @@ -import os -import re - -def main(): - fileIN = open('eg_states.h', 'r') - line = fileIN.readline() - next_is_reg = False - count = 0 - - print "/* This file is autogenerated from eg_states.h - do not edit directly */" - print "/* autogenerating script is gen_eg_states.py */" - print "" - while line: - if line[0:2] == "};": - if next_is_reg == True: - print "#define " + name + "_SIZE\t\t", count - print "#define " + name + "_PM4 128\t\t" - next_is_reg = False - count = 0 - print "" - - if line[0:6] == "static": - name = line.rstrip("\n") - cline = name.split() - name = cline[4].split('[') - name = name[0].replace("_names", "") - print "/* " + name + " */" - next_is_reg = True - elif next_is_reg == True: - reg = line.split(); - reg = reg[3].replace("},", "") - reg = reg.replace("\"", "") - print "#define " + name + "__" + reg + "\t\t", count - count = count + 1 - - line = fileIN.readline() - -if __name__ == "__main__": - main() diff --git a/src/gallium/winsys/r600/drm/gen_r600_states.py b/src/gallium/winsys/r600/drm/gen_r600_states.py deleted file mode 100644 index 9bd5ab20825..00000000000 --- a/src/gallium/winsys/r600/drm/gen_r600_states.py +++ /dev/null @@ -1,39 +0,0 @@ -import os -import re - -def main(): - fileIN = open('r600_states.h', 'r') - line = fileIN.readline() - next_is_reg = False - count = 0 - - print "/* This file is autogenerated from r600_states.h - do not edit directly */" - print "/* autogenerating script is gen_r600_states.py */" - print "" - while line: - if line[0:2] == "};": - if next_is_reg == True: - print "#define " + name + "_SIZE\t\t", count - print "#define " + name + "_PM4 128\t\t" - next_is_reg = False - count = 0 - print "" - - if line[0:6] == "static": - name = line.rstrip("\n") - cline = name.split() - name = cline[4].split('[') - name = name[0].replace("_names", "") - print "/* " + name + " */" - next_is_reg = True - elif next_is_reg == True: - reg = line.split(); - reg = reg[3].replace("},", "") - reg = reg.replace("\"", "") - print "#define " + name + "__" + reg + "\t\t", count - count = count + 1 - - line = fileIN.readline() - -if __name__ == "__main__": - main() diff --git a/src/gallium/winsys/r600/drm/r600.c b/src/gallium/winsys/r600/drm/r600.c index af9b9187ab1..0a4d2e791db 100644 --- a/src/gallium/winsys/r600/drm/r600.c +++ b/src/gallium/winsys/r600/drm/r600.c @@ -25,6 +25,9 @@ */ #include "xf86drm.h" #include "radeon_drm.h" +#include "pipe/p_compiler.h" +#include "util/u_inlines.h" +#include <pipebuffer/pb_bufmgr.h> #include "r600_priv.h" enum radeon_family r600_get_family(struct radeon *r600) @@ -32,6 +35,16 @@ enum radeon_family r600_get_family(struct radeon *r600) return r600->family; } +enum chip_class r600_get_family_class(struct radeon *radeon) +{ + return radeon->chip_class; +} + +struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon) +{ + return &radeon->tiling_info; +} + static int r600_get_device(struct radeon *r600) { struct drm_radeon_info info; @@ -117,6 +130,37 @@ struct radeon *r600_new(int fd, unsigned device) R600_ERR("unknown or unsupported chipset 0x%04X\n", r600->device); break; } + + /* setup class */ + switch (r600->family) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + r600->chip_class = R600; + break; + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + r600->chip_class = R700; + break; + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + r600->chip_class = EVERGREEN; + break; + default: + R600_ERR("unknown or unsupported chipset 0x%04X\n", r600->device); + break; + } + return r600; } diff --git a/src/gallium/winsys/r600/drm/r600_bo.c b/src/gallium/winsys/r600/drm/r600_bo.c new file mode 100644 index 00000000000..9498f3a82ea --- /dev/null +++ b/src/gallium/winsys/r600/drm/r600_bo.c @@ -0,0 +1,122 @@ +/* + * Copyright 2010 Dave Airlie + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Dave Airlie + */ +#include <pipe/p_compiler.h> +#include <pipe/p_screen.h> +#include <pipebuffer/pb_bufmgr.h> +#include "r600_priv.h" + +struct r600_bo *r600_bo(struct radeon *radeon, + unsigned size, unsigned alignment, unsigned usage) +{ + struct r600_bo *ws_bo = calloc(1, sizeof(struct r600_bo)); + struct pb_desc desc; + struct pb_manager *man; + + desc.alignment = alignment; + desc.usage = usage; + ws_bo->size = size; + + if (usage & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) + man = radeon->cman; + else + man = radeon->kman; + + ws_bo->pb = man->create_buffer(man, size, &desc); + if (ws_bo->pb == NULL) { + free(ws_bo); + return NULL; + } + + pipe_reference_init(&ws_bo->reference, 1); + return ws_bo; +} + +struct r600_bo *r600_bo_handle(struct radeon *radeon, + unsigned handle) +{ + struct r600_bo *ws_bo = calloc(1, sizeof(struct r600_bo)); + struct radeon_bo *bo; + + ws_bo->pb = radeon_bo_pb_create_buffer_from_handle(radeon->kman, handle); + if (!ws_bo->pb) { + free(ws_bo); + return NULL; + } + bo = radeon_bo_pb_get_bo(ws_bo->pb); + ws_bo->size = bo->size; + pipe_reference_init(&ws_bo->reference, 1); + return ws_bo; +} + +void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx) +{ + return pb_map(bo->pb, usage, ctx); +} + +void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo) +{ + pb_unmap(bo->pb); +} + +static void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo) +{ + if (bo->pb) + pb_reference(&bo->pb, NULL); + free(bo); +} + +void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, + struct r600_bo *src) +{ + struct r600_bo *old = *dst; + + if (pipe_reference(&(*dst)->reference, &src->reference)) { + r600_bo_destroy(radeon, old); + } + *dst = src; +} + +unsigned r600_bo_get_handle(struct r600_bo *pb_bo) +{ + struct radeon_bo *bo; + + bo = radeon_bo_pb_get_bo(pb_bo->pb); + if (!bo) + return 0; + + return bo->handle; +} + +unsigned r600_bo_get_size(struct r600_bo *pb_bo) +{ + struct radeon_bo *bo; + + bo = radeon_bo_pb_get_bo(pb_bo->pb); + if (!bo) + return 0; + + return bo->size; +} diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c index 7a1a762f540..c9de95ffc02 100644 --- a/src/gallium/winsys/r600/drm/r600_drm.c +++ b/src/gallium/winsys/r600/drm/r600_drm.c @@ -25,14 +25,231 @@ * Corbin Simpson <[email protected]> * Joakim Sindholt <[email protected]> */ +#include <stdio.h> +#include <errno.h> #include <sys/ioctl.h> #include "util/u_inlines.h" #include "util/u_debug.h" -#include "radeon_priv.h" +#include <pipebuffer/pb_bufmgr.h> +#include "r600.h" +#include "r600_priv.h" #include "r600_drm_public.h" +#include "xf86drm.h" +#include "radeon_drm.h" + +#ifndef RADEON_INFO_TILING_CONFIG +#define RADEON_INFO_TILING_CONFIG 0x6 +#endif +static int radeon_get_device(struct radeon *radeon) +{ + struct drm_radeon_info info; + int r; + + radeon->device = 0; + info.request = RADEON_INFO_DEVICE_ID; + info.value = (uintptr_t)&radeon->device; + r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info, + sizeof(struct drm_radeon_info)); + return r; +} + +static int radeon_drm_get_tiling(struct radeon *radeon) +{ + struct drm_radeon_info info; + int r; + uint32_t tiling_config; + + info.request = RADEON_INFO_TILING_CONFIG; + info.value = (uintptr_t)&tiling_config; + r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info, + sizeof(struct drm_radeon_info)); + + if (r) + return r; + + switch ((tiling_config & 0xe) >> 1) { + case 0: + radeon->tiling_info.num_channels = 1; + break; + case 1: + radeon->tiling_info.num_channels = 2; + break; + case 2: + radeon->tiling_info.num_channels = 4; + break; + case 3: + radeon->tiling_info.num_channels = 8; + break; + default: + return -EINVAL; + } + + switch ((tiling_config & 0x30) >> 4) { + case 0: + radeon->tiling_info.num_banks = 4; + break; + case 1: + radeon->tiling_info.num_banks = 8; + break; + default: + return -EINVAL; + + } + switch ((tiling_config & 0xc0) >> 6) { + case 0: + radeon->tiling_info.group_bytes = 256; + break; + case 1: + radeon->tiling_info.group_bytes = 512; + break; + default: + return -EINVAL; + } + return 0; +} + +struct radeon *radeon_new(int fd, unsigned device) +{ + struct radeon *radeon; + int r; + + radeon = calloc(1, sizeof(*radeon)); + if (radeon == NULL) { + return NULL; + } + radeon->fd = fd; + radeon->device = device; + radeon->refcount = 1; + if (fd >= 0) { + r = radeon_get_device(radeon); + if (r) { + fprintf(stderr, "Failed to get device id\n"); + return radeon_decref(radeon); + } + } + radeon->family = radeon_family_from_device(radeon->device); + if (radeon->family == CHIP_UNKNOWN) { + fprintf(stderr, "Unknown chipset 0x%04X\n", radeon->device); + return radeon_decref(radeon); + } + switch (radeon->family) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + break; + case CHIP_R100: + case CHIP_RV100: + case CHIP_RS100: + case CHIP_RV200: + case CHIP_RS200: + case CHIP_R200: + case CHIP_RV250: + case CHIP_RS300: + case CHIP_RV280: + case CHIP_R300: + case CHIP_R350: + case CHIP_RV350: + case CHIP_RV380: + case CHIP_R420: + case CHIP_R423: + case CHIP_RV410: + case CHIP_RS400: + case CHIP_RS480: + case CHIP_RS600: + case CHIP_RS690: + case CHIP_RS740: + case CHIP_RV515: + case CHIP_R520: + case CHIP_RV530: + case CHIP_RV560: + case CHIP_RV570: + case CHIP_R580: + default: + fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n", + __func__, radeon->device); + break; + } + + /* setup class */ + switch (radeon->family) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + radeon->chip_class = R600; + break; + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + radeon->chip_class = R700; + break; + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + radeon->chip_class = EVERGREEN; + break; + default: + fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n", + __func__, radeon->device); + break; + } + + if (radeon->chip_class == R600 || radeon->chip_class == R700) { + if (radeon_drm_get_tiling(radeon)) + return NULL; + } + radeon->kman = radeon_bo_pbmgr_create(radeon); + if (!radeon->kman) + return NULL; + radeon->cman = pb_cache_manager_create(radeon->kman, 100000); + if (!radeon->cman) + return NULL; + return radeon; +} struct radeon *r600_drm_winsys_create(int drmfd) { return radeon_new(drmfd, 0); } +struct radeon *radeon_decref(struct radeon *radeon) +{ + if (radeon == NULL) + return NULL; + if (--radeon->refcount > 0) { + return NULL; + } + + if (radeon->cman) + radeon->cman->destroy(radeon->cman); + + if (radeon->kman) + radeon->kman->destroy(radeon->kman); + + if (radeon->fd >= 0) + drmClose(radeon->fd); + + free(radeon); + return NULL; +} diff --git a/src/gallium/winsys/r600/drm/r600_drm_public.h b/src/gallium/winsys/r600/drm/r600_drm_public.h index 84f2dce437a..cfce8df9c2c 100644 --- a/src/gallium/winsys/r600/drm/r600_drm_public.h +++ b/src/gallium/winsys/r600/drm/r600_drm_public.h @@ -1,4 +1,28 @@ - +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ #ifndef R600_DRM_PUBLIC_H #define R600_DRM_PUBLIC_H diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c new file mode 100644 index 00000000000..2521ff96473 --- /dev/null +++ b/src/gallium/winsys/r600/drm/r600_hw_context.c @@ -0,0 +1,1362 @@ +/* + * Copyright 2010 Jerome Glisse <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <errno.h> +#include <stdint.h> +#include <string.h> +#include <stdlib.h> +#include <assert.h> +#include "xf86drm.h" +#include "r600.h" +#include "r600d.h" +#include "radeon_drm.h" +#include "bof.h" +#include "pipe/p_compiler.h" +#include "util/u_inlines.h" +#include "util/u_memory.h" +#include <pipebuffer/pb_bufmgr.h> +#include "r600_priv.h" + +#define GROUP_FORCE_NEW_BLOCK 0 + +int r600_context_init_fence(struct r600_context *ctx) +{ + ctx->fence = 1; + ctx->fence_bo = r600_bo(ctx->radeon, 4096, 0, 0); + if (ctx->fence_bo == NULL) { + return -ENOMEM; + } + ctx->cfence = r600_bo_map(ctx->radeon, ctx->fence_bo, PB_USAGE_UNSYNCHRONIZED, NULL); + *ctx->cfence = 0; + LIST_INITHEAD(&ctx->fenced_bo); + return 0; +} + +static void INLINE r600_context_update_fenced_list(struct r600_context *ctx) +{ + for (int i = 0; i < ctx->creloc; i++) { + if (!LIST_IS_EMPTY(&ctx->bo[i]->fencedlist)) + LIST_DELINIT(&ctx->bo[i]->fencedlist); + LIST_ADDTAIL(&ctx->bo[i]->fencedlist, &ctx->fenced_bo); + ctx->bo[i]->fence = ctx->fence; + ctx->bo[i]->ctx = ctx; + } +} + +static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsigned fence) +{ + struct radeon_bo *bo = NULL; + struct radeon_bo *tmp; + + LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &ctx->fenced_bo, fencedlist) { + if (bo->fence <= *ctx->cfence) { + LIST_DELINIT(&bo->fencedlist); + bo->fence = 0; + } else { + bo->fence = fence; + } + } +} + +int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg) +{ + struct r600_block *block; + struct r600_range *range; + int offset; + + for (unsigned i = 0, n = 0; i < nreg; i += n) { + u32 j; + + /* ignore new block balise */ + if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) { + n = 1; + continue; + } + + /* register that need relocation are in their own group */ + /* find number of consecutive registers */ + n = 0; + offset = reg[i].offset; + while (reg[i + n].offset == offset) { + n++; + offset += 4; + if ((n + i) >= nreg) + break; + if (n >= (R600_BLOCK_MAX_REG - 2)) + break; + } + + /* allocate new block */ + block = calloc(1, sizeof(struct r600_block)); + if (block == NULL) { + return -ENOMEM; + } + ctx->nblocks++; + for (int j = 0; j < n; j++) { + range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)]; + range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block; + } + + /* initialize block */ + block->start_offset = reg[i].offset; + block->pm4[block->pm4_ndwords++] = PKT3(reg[i].opcode, n); + block->pm4[block->pm4_ndwords++] = (block->start_offset - reg[i].offset_base) >> 2; + block->reg = &block->pm4[block->pm4_ndwords]; + block->pm4_ndwords += n; + block->nreg = n; + LIST_INITHEAD(&block->list); + + for (j = 0; j < n; j++) { + if (reg[i+j].need_bo) { + block->nbo++; + assert(block->nbo < R600_BLOCK_MAX_BO); + block->pm4_bo_index[j] = block->nbo; + block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0); + block->pm4[block->pm4_ndwords++] = 0x00000000; + block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags; + block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask; + block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1; + } + } + for (j = 0; j < n; j++) { + if (reg[i+j].flush_flags) { + block->pm4_flush_ndwords += 7; + } + } + /* check that we stay in limit */ + assert(block->pm4_ndwords < R600_BLOCK_MAX_REG); + } + return 0; +} + +/* R600/R700 configuration */ +static const struct r600_reg r600_config_reg_list[] = { + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009508_TA_CNTL_AUX, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009714_VC_ENHANCE, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009830_DB_DEBUG, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0, 0}, +}; + +static const struct r600_reg r600_ctl_const_list[] = { + {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, + {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, +}; + +static const struct r600_reg r600_context_reg_list[] = { + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB0_VGT_STRMOUT_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028040_CB_COLOR0_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028060_CB_COLOR0_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028080_CB_COLOR0_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E0_CB_COLOR0_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C0_CB_COLOR0_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028100_CB_COLOR0_MASK, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028044_CB_COLOR1_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028064_CB_COLOR1_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028084_CB_COLOR1_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E4_CB_COLOR1_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C4_CB_COLOR1_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028104_CB_COLOR1_MASK, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028048_CB_COLOR2_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028068_CB_COLOR2_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028088_CB_COLOR2_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E8_CB_COLOR2_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C8_CB_COLOR2_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028108_CB_COLOR2_MASK, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02804C_CB_COLOR3_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02806C_CB_COLOR3_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02808C_CB_COLOR3_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280EC_CB_COLOR3_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280CC_CB_COLOR3_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02810C_CB_COLOR3_MASK, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028050_CB_COLOR4_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028070_CB_COLOR4_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028090_CB_COLOR4_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F0_CB_COLOR4_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D0_CB_COLOR4_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028110_CB_COLOR4_MASK, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028054_CB_COLOR5_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028074_CB_COLOR5_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028094_CB_COLOR5_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F4_CB_COLOR5_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D4_CB_COLOR5_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028114_CB_COLOR5_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028058_CB_COLOR6_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028078_CB_COLOR6_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028098_CB_COLOR6_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F8_CB_COLOR6_FRAG, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D8_CB_COLOR6_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028118_CB_COLOR6_MASK, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02805C_CB_COLOR7_BASE, 1, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, 1, 0, 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02807C_CB_COLOR7_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02809C_CB_COLOR7_VIEW, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280FC_CB_COLOR7_FRAG, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280DC_CB_COLOR7_TILE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02811C_CB_COLOR7_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028120_CB_CLEAR_RED, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028124_CB_CLEAR_GREEN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028128_CB_CLEAR_BLUE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02812C_CB_CLEAR_ALPHA, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028424_CB_FOG_RED, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028428_CB_FOG_GREEN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02842C_CB_FOG_BLUE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0287A0_CB_SHADER_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028804_CB_BLEND_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C34_CB_CLRCMP_SRC, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C38_CB_CLRCMP_DST, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C3C_CB_CLRCMP_MSK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C48_PA_SC_AA_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02800C_DB_DEPTH_BASE, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028000_DB_DEPTH_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028004_DB_DEPTH_VIEW, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028010_DB_DEPTH_INFO, 1, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D0C_DB_RENDER_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D24_DB_HTILE_SURFACE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E20_PA_CL_UCP0_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E24_PA_CL_UCP0_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E28_PA_CL_UCP0_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E2C_PA_CL_UCP0_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E30_PA_CL_UCP1_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E34_PA_CL_UCP1_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E38_PA_CL_UCP1_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E3C_PA_CL_UCP1_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E40_PA_CL_UCP2_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E44_PA_CL_UCP2_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E48_PA_CL_UCP2_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E4C_PA_CL_UCP2_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E50_PA_CL_UCP3_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E54_PA_CL_UCP3_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E58_PA_CL_UCP3_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E5C_PA_CL_UCP3_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E60_PA_CL_UCP4_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E64_PA_CL_UCP4_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E68_PA_CL_UCP4_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E6C_PA_CL_UCP4_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E70_PA_CL_UCP5_X, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E74_PA_CL_UCP5_Y, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E78_PA_CL_UCP5_Z, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E7C_PA_CL_UCP5_W, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028614_SPI_VS_OUT_ID_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028618_SPI_VS_OUT_ID_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_4, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_5, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_7, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_8, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_9, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028858_SQ_PGM_START_VS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028894_SQ_PGM_START_FS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, 1, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0}, + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0}, +}; + +/* SHADER RESOURCE R600/R700 */ +static int r600_state_resource_init(struct r600_context *ctx, u32 offset) +{ + struct r600_reg r600_shader_resource[] = { + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038000_RESOURCE0_WORD0, 0, 0, 0}, + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038004_RESOURCE0_WORD1, 0, 0, 0}, + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038008_RESOURCE0_WORD2, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_03800C_RESOURCE0_WORD3, 1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038010_RESOURCE0_WORD4, 0, 0, 0}, + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038014_RESOURCE0_WORD5, 0, 0, 0}, + {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038018_RESOURCE0_WORD6, 0, 0, 0}, + }; + unsigned nreg = Elements(r600_shader_resource); + + for (int i = 0; i < nreg; i++) { + r600_shader_resource[i].offset += offset; + } + return r600_context_add_block(ctx, r600_shader_resource, nreg); +} + +/* SHADER SAMPLER R600/R700 */ +static int r600_state_sampler_init(struct r600_context *ctx, u32 offset) +{ + struct r600_reg r600_shader_sampler[] = { + {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, + {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, + {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, + }; + unsigned nreg = Elements(r600_shader_sampler); + + for (int i = 0; i < nreg; i++) { + r600_shader_sampler[i].offset += offset; + } + return r600_context_add_block(ctx, r600_shader_sampler, nreg); +} + +/* SHADER SAMPLER BORDER R600/R700 */ +static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset) +{ + struct r600_reg r600_shader_sampler_border[] = { + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, + {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, + }; + unsigned nreg = Elements(r600_shader_sampler_border); + + for (int i = 0; i < nreg; i++) { + r600_shader_sampler_border[i].offset += offset; + } + return r600_context_add_block(ctx, r600_shader_sampler_border, nreg); +} + +static int r600_loop_const_init(struct r600_context *ctx, u32 offset) +{ + unsigned nreg = 32; + struct r600_reg r600_loop_consts[32]; + int i; + + for (i = 0; i < nreg; i++) { + r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST; + r600_loop_consts[i].offset_base = R600_LOOP_CONST_OFFSET; + r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4); + r600_loop_consts[i].need_bo = 0; + r600_loop_consts[i].flush_flags = 0; + r600_loop_consts[i].flush_mask = 0; + } + return r600_context_add_block(ctx, r600_loop_consts, nreg); +} + +/* initialize */ +void r600_context_fini(struct r600_context *ctx) +{ + struct r600_block *block; + struct r600_range *range; + + for (int i = 0; i < 256; i++) { + for (int j = 0; j < (1 << ctx->hash_shift); j++) { + block = ctx->range[i].blocks[j]; + if (block) { + for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) { + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + range->blocks[CTX_BLOCK_ID(ctx, offset)] = NULL; + } + free(block); + } + } + free(ctx->range[i].blocks); + } + free(ctx->reloc); + free(ctx->pm4); + if (ctx->fence_bo) { + r600_bo_reference(ctx->radeon, &ctx->fence_bo, NULL); + } + memset(ctx, 0, sizeof(struct r600_context)); +} + +int r600_context_init(struct r600_context *ctx, struct radeon *radeon) +{ + int r; + + memset(ctx, 0, sizeof(struct r600_context)); + ctx->radeon = radeon; + LIST_INITHEAD(&ctx->query_list); + + /* initialize hash */ + ctx->hash_size = 19; + ctx->hash_shift = 11; + for (int i = 0; i < 256; i++) { + ctx->range[i].start_offset = i << ctx->hash_shift; + ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1; + ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*)); + if (ctx->range[i].blocks == NULL) { + return -ENOMEM; + } + } + + /* add blocks */ + r = r600_context_add_block(ctx, r600_config_reg_list, + Elements(r600_config_reg_list)); + if (r) + goto out_err; + r = r600_context_add_block(ctx, r600_context_reg_list, + Elements(r600_context_reg_list)); + if (r) + goto out_err; + r = r600_context_add_block(ctx, r600_ctl_const_list, + Elements(r600_ctl_const_list)); + if (r) + goto out_err; + + /* PS SAMPLER BORDER */ + for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) { + r = r600_state_sampler_border_init(ctx, offset); + if (r) + goto out_err; + } + + /* VS SAMPLER BORDER */ + for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) { + r = r600_state_sampler_border_init(ctx, offset); + if (r) + goto out_err; + } + /* PS SAMPLER */ + for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) { + r = r600_state_sampler_init(ctx, offset); + if (r) + goto out_err; + } + /* VS SAMPLER */ + for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) { + r = r600_state_sampler_init(ctx, offset); + if (r) + goto out_err; + } + /* PS RESOURCE */ + for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) { + r = r600_state_resource_init(ctx, offset); + if (r) + goto out_err; + } + /* VS RESOURCE */ + for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) { + r = r600_state_resource_init(ctx, offset); + if (r) + goto out_err; + } + + /* PS loop const */ + r600_loop_const_init(ctx, 0); + /* VS loop const */ + r600_loop_const_init(ctx, 32); + + /* setup block table */ + ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); + for (int i = 0, c = 0; i < 256; i++) { + for (int j = 0, add; j < (1 << ctx->hash_shift); j++) { + if (ctx->range[i].blocks[j]) { + add = 1; + for (int k = 0; k < c; k++) { + if (ctx->blocks[k] == ctx->range[i].blocks[j]) { + add = 0; + break; + } + } + if (add) { + assert(c < ctx->nblocks); + ctx->blocks[c++] = ctx->range[i].blocks[j]; + j += (ctx->range[i].blocks[j]->nreg << 2) - 1; + } + } + } + } + + /* allocate cs variables */ + ctx->nreloc = RADEON_CTX_MAX_PM4; + ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc)); + if (ctx->reloc == NULL) { + r = -ENOMEM; + goto out_err; + } + ctx->bo = calloc(ctx->nreloc, sizeof(void *)); + if (ctx->bo == NULL) { + r = -ENOMEM; + goto out_err; + } + ctx->pm4_ndwords = RADEON_CTX_MAX_PM4; + ctx->pm4 = calloc(ctx->pm4_ndwords, 4); + if (ctx->pm4 == NULL) { + r = -ENOMEM; + goto out_err; + } + /* save 16dwords space for fence mecanism */ + ctx->pm4_ndwords -= 16; + + r = r600_context_init_fence(ctx); + if (r) { + goto out_err; + } + + /* init dirty list */ + LIST_INITHEAD(&ctx->dirty); + return 0; +out_err: + r600_context_fini(ctx); + return r; +} + +void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags, + unsigned flush_mask, struct r600_bo *rbo) +{ + struct radeon_bo *bo; + + bo = r600_bo_get_bo(rbo); + /* if bo has already been flush */ + if (!(bo->last_flush ^ flush_flags)) { + bo->last_flush &= flush_mask; + return; + } + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3); + ctx->pm4[ctx->pm4_cdwords++] = flush_flags; + ctx->pm4[ctx->pm4_cdwords++] = (bo->size + 255) >> 8; + ctx->pm4[ctx->pm4_cdwords++] = 0x00000000; + ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = bo->reloc_id; + bo->last_flush = (bo->last_flush | flush_flags) & flush_mask; +} + +void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo) +{ + struct radeon_bo *bo; + + bo = r600_bo_get_bo(rbo); + assert(bo != NULL); + if (bo->reloc) { + *pm4 = bo->reloc_id; + return; + } + bo->reloc = &ctx->reloc[ctx->creloc]; + bo->reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4; + ctx->reloc[ctx->creloc].handle = bo->handle; + ctx->reloc[ctx->creloc].read_domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; + ctx->reloc[ctx->creloc].write_domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM; + ctx->reloc[ctx->creloc].flags = 0; + radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo); + ctx->creloc++; + /* set PKT3 to point to proper reloc */ + *pm4 = bo->reloc_id; +} + +void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state) +{ + struct r600_range *range; + struct r600_block *block; + + for (int i = 0; i < state->nregs; i++) { + unsigned id; + + range = &ctx->range[CTX_RANGE_ID(ctx, state->regs[i].offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, state->regs[i].offset)]; + id = (state->regs[i].offset - block->start_offset) >> 2; + block->reg[id] &= ~state->regs[i].mask; + block->reg[id] |= state->regs[i].value; + if (block->pm4_bo_index[id]) { + /* find relocation */ + id = block->pm4_bo_index[id]; + r600_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo); + } + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } + } +} + +static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + if (state == NULL) { + block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); + r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); + LIST_DELINIT(&block->list); + return; + } + block->reg[0] = state->regs[0].value; + block->reg[1] = state->regs[1].value; + block->reg[2] = state->regs[2].value; + block->reg[3] = state->regs[3].value; + block->reg[4] = state->regs[4].value; + block->reg[5] = state->regs[5].value; + block->reg[6] = state->regs[6].value; + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); + r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); + if (state->regs[0].bo) { + /* VERTEX RESOURCE, we preted there is 2 bo to relocate so + * we have single case btw VERTEX & TEXTURE resource + */ + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo); + r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo); + } else { + /* TEXTURE RESOURCE */ + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo); + r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo); + } + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid; + + r600_context_pipe_state_set_resource(ctx, state, offset); +} + +void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) +{ + unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid; + + r600_context_pipe_state_set_resource(ctx, state, offset); +} + +static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + if (state == NULL) { + block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + LIST_DELINIT(&block->list); + return; + } + block->reg[0] = state->regs[0].value; + block->reg[1] = state->regs[1].value; + block->reg[2] = state->regs[2].value; + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + if (state == NULL) { + block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + LIST_DELINIT(&block->list); + return; + } + if (state->nregs <= 3) { + return; + } + block->reg[0] = state->regs[3].value; + block->reg[1] = state->regs[4].value; + block->reg[2] = state->regs[5].value; + block->reg[3] = state->regs[6].value; + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) +{ + unsigned offset; + + offset = 0x0003C000 + id * 0xc; + r600_context_pipe_state_set_sampler(ctx, state, offset); + offset = 0x0000A400 + id * 0x10; + r600_context_pipe_state_set_sampler_border(ctx, state, offset); +} + +void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) +{ + unsigned offset; + + offset = 0x0003C0D8 + id * 0xc; + r600_context_pipe_state_set_sampler(ctx, state, offset); + offset = 0x0000A600 + id * 0x10; + r600_context_pipe_state_set_sampler_border(ctx, state, offset); +} + +struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset) +{ + struct r600_range *range; + struct r600_block *block; + unsigned id; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + offset -= block->start_offset; + id = block->pm4_bo_index[offset >> 2]; + if (block->reloc[id].bo) { + return block->reloc[id].bo; + } + return NULL; +} + +void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw) +{ + struct r600_bo *cb[8]; + struct r600_bo *db; + unsigned ndwords = 9; + struct r600_block *dirty_block = NULL; + struct r600_block *next_block; + + if (draw->indices) { + ndwords = 13; + /* make sure there is enough relocation space before scheduling draw */ + if (ctx->creloc >= (ctx->nreloc - 1)) { + r600_context_flush(ctx); + } + } + + /* find number of color buffer */ + db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE); + cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE); + cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE); + cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE); + cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE); + cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE); + cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE); + cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE); + cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE); + for (int i = 0; i < 8; i++) { + if (cb[i]) { + ndwords += 7; + } + } + if (db) + ndwords += 7; + + /* queries need some special values */ + if (ctx->num_query_running) { + if (ctx->radeon->family >= CHIP_RV770) { + r600_context_reg(ctx, + R_028D0C_DB_RENDER_CONTROL, + S_028D0C_R700_PERFECT_ZPASS_COUNTS(1), + S_028D0C_R700_PERFECT_ZPASS_COUNTS(1)); + } + r600_context_reg(ctx, + R_028D10_DB_RENDER_OVERRIDE, + S_028D10_NOOP_CULL_DISABLE(1), + S_028D10_NOOP_CULL_DISABLE(1)); + } + + if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) { + /* need to flush */ + r600_context_flush(ctx); + } + /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */ + if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) { + R600_ERR("context is too big to be scheduled\n"); + return; + } + + /* enough room to copy packet */ + LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty,list) { + r600_context_block_emit_dirty(ctx, dirty_block); + } + + /* draw packet */ + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0); + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0); + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances; + if (draw->indices) { + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3); + ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset + r600_bo_offset(draw->indices); + ctx->pm4[ctx->pm4_cdwords++] = 0; + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices; + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = 0; + r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices); + } else { + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1); + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices; + ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; + } + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0); + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; + + /* flush color buffer */ + for (int i = 0; i < 8; i++) { + if (cb[i]) { + r600_context_bo_flush(ctx, + (S_0085F0_CB0_DEST_BASE_ENA(1) << i) | + S_0085F0_CB_ACTION_ENA(1), + 0, cb[i]); + } + } + if (db) { + r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1), 0, db); + } + + /* all dirty state have been scheduled in current cs */ + ctx->pm4_dirty_cdwords = 0; +} + +void r600_context_flush(struct r600_context *ctx) +{ + struct drm_radeon_cs drmib; + struct drm_radeon_cs_chunk chunks[2]; + uint64_t chunk_array[2]; + unsigned fence; + int r; + + if (!ctx->pm4_cdwords) + return; + + /* suspend queries */ + r600_context_queries_suspend(ctx); + + radeon_bo_pbmgr_flush_maps(ctx->radeon->kman); + + /* emit fence */ + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4); + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT | (5 << 8); + ctx->pm4[ctx->pm4_cdwords++] = 0; + ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24); + ctx->pm4[ctx->pm4_cdwords++] = ctx->fence; + ctx->pm4[ctx->pm4_cdwords++] = 0; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = 0; + r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], ctx->fence_bo); + +#if 1 + /* emit cs */ + drmib.num_chunks = 2; + drmib.chunks = (uint64_t)(uintptr_t)chunk_array; + chunks[0].chunk_id = RADEON_CHUNK_ID_IB; + chunks[0].length_dw = ctx->pm4_cdwords; + chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4; + chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS; + chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4; + chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc; + chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0]; + chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1]; + r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib, + sizeof(struct drm_radeon_cs)); +#endif + + r600_context_update_fenced_list(ctx); + + fence = ctx->fence + 1; + if (fence < ctx->fence) { + /* wrap around */ + fence = 1; + r600_context_fence_wraparound(ctx, fence); + } + ctx->fence = fence; + + /* restart */ + for (int i = 0; i < ctx->creloc; i++) { + ctx->bo[i]->reloc = NULL; + ctx->bo[i]->last_flush = 0; + radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL); + } + ctx->creloc = 0; + ctx->pm4_dirty_cdwords = 0; + ctx->pm4_cdwords = 0; + + /* resume queries */ + r600_context_queries_resume(ctx); + + /* set all valid group as dirty so they get reemited on + * next draw command + */ + for (int i = 0; i < ctx->nblocks; i++) { + if (ctx->blocks[i]->status & R600_BLOCK_STATUS_ENABLED) { + if(!(ctx->blocks[i]->status & R600_BLOCK_STATUS_DIRTY)) { + LIST_ADDTAIL(&ctx->blocks[i]->list,&ctx->dirty); + } + ctx->pm4_dirty_cdwords += ctx->blocks[i]->pm4_ndwords + ctx->blocks[i]->pm4_flush_ndwords; + ctx->blocks[i]->status |= R600_BLOCK_STATUS_DIRTY; + } + } +} + +void r600_context_dump_bof(struct r600_context *ctx, const char *file) +{ + bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root; + unsigned i; + + root = device_id = bcs = blob = array = bo = size = handle = NULL; + root = bof_object(); + if (root == NULL) + goto out_err; + device_id = bof_int32(ctx->radeon->device); + if (device_id == NULL) + goto out_err; + if (bof_object_set(root, "device_id", device_id)) + goto out_err; + bof_decref(device_id); + device_id = NULL; + /* dump relocs */ + blob = bof_blob(ctx->creloc * 16, ctx->reloc); + if (blob == NULL) + goto out_err; + if (bof_object_set(root, "reloc", blob)) + goto out_err; + bof_decref(blob); + blob = NULL; + /* dump cs */ + blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4); + if (blob == NULL) + goto out_err; + if (bof_object_set(root, "pm4", blob)) + goto out_err; + bof_decref(blob); + blob = NULL; + /* dump bo */ + array = bof_array(); + if (array == NULL) + goto out_err; + for (i = 0; i < ctx->creloc; i++) { + struct radeon_bo *rbo = ctx->bo[i]; + bo = bof_object(); + if (bo == NULL) + goto out_err; + size = bof_int32(rbo->size); + if (size == NULL) + goto out_err; + if (bof_object_set(bo, "size", size)) + goto out_err; + bof_decref(size); + size = NULL; + handle = bof_int32(rbo->handle); + if (handle == NULL) + goto out_err; + if (bof_object_set(bo, "handle", handle)) + goto out_err; + bof_decref(handle); + handle = NULL; + radeon_bo_map(ctx->radeon, rbo); + blob = bof_blob(rbo->size, rbo->data); + radeon_bo_unmap(ctx->radeon, rbo); + if (blob == NULL) + goto out_err; + if (bof_object_set(bo, "data", blob)) + goto out_err; + bof_decref(blob); + blob = NULL; + if (bof_array_append(array, bo)) + goto out_err; + bof_decref(bo); + bo = NULL; + } + if (bof_object_set(root, "bo", array)) + goto out_err; + bof_dump_file(root, file); +out_err: + bof_decref(blob); + bof_decref(array); + bof_decref(bo); + bof_decref(size); + bof_decref(handle); + bof_decref(device_id); + bof_decref(root); +} + +static void r600_query_result(struct r600_context *ctx, struct r600_query *query) +{ + u64 start, end; + u32 *results; + int i; + + results = r600_bo_map(ctx->radeon, query->buffer, 0, NULL); + for (i = 0; i < query->num_results; i += 4) { + start = (u64)results[i] | (u64)results[i + 1] << 32; + end = (u64)results[i + 2] | (u64)results[i + 3] << 32; + if ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL)) { + query->result += end - start; + } + } + r600_bo_unmap(ctx->radeon, query->buffer); + query->num_results = 0; +} + +void r600_query_begin(struct r600_context *ctx, struct r600_query *query) +{ + /* query request needs 6 dwords for begin + 6 dwords for end */ + if ((12 + ctx->pm4_cdwords) > ctx->pm4_ndwords) { + /* need to flush */ + r600_context_flush(ctx); + } + + /* if query buffer is full force a flush */ + if (query->num_results >= ((query->buffer_size >> 2) - 2)) { + r600_context_flush(ctx); + r600_query_result(ctx, query); + } + + /* emit begin query */ + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2); + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE; + ctx->pm4[ctx->pm4_cdwords++] = query->num_results + r600_bo_offset(query->buffer); + ctx->pm4[ctx->pm4_cdwords++] = 0; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = 0; + r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer); + + query->state |= R600_QUERY_STATE_STARTED; + query->state ^= R600_QUERY_STATE_ENDED; + ctx->num_query_running++; +} + +void r600_query_end(struct r600_context *ctx, struct r600_query *query) +{ + /* emit begin query */ + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2); + ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE; + ctx->pm4[ctx->pm4_cdwords++] = query->num_results + 8 + r600_bo_offset(query->buffer); + ctx->pm4[ctx->pm4_cdwords++] = 0; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = 0; + r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], query->buffer); + + query->num_results += 16; + query->state ^= R600_QUERY_STATE_STARTED; + query->state |= R600_QUERY_STATE_ENDED; + ctx->num_query_running--; +} + +struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type) +{ + struct r600_query *query; + + if (query_type != PIPE_QUERY_OCCLUSION_COUNTER) + return NULL; + + query = calloc(1, sizeof(struct r600_query)); + if (query == NULL) + return NULL; + + query->type = query_type; + query->buffer_size = 4096; + + query->buffer = r600_bo(ctx->radeon, query->buffer_size, 1, 0); + if (!query->buffer) { + free(query); + return NULL; + } + + LIST_ADDTAIL(&query->list, &ctx->query_list); + + return query; +} + +void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query) +{ + r600_bo_reference(ctx->radeon, &query->buffer, NULL); + LIST_DELINIT(&query->list); + free(query); +} + +boolean r600_context_query_result(struct r600_context *ctx, + struct r600_query *query, + boolean wait, void *vresult) +{ + uint64_t *result = (uint64_t*)vresult; + + if (query->num_results) { + r600_context_flush(ctx); + } + r600_query_result(ctx, query); + *result = query->result; + query->result = 0; + return TRUE; +} + +void r600_context_queries_suspend(struct r600_context *ctx) +{ + struct r600_query *query; + + LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) { + if (query->state & R600_QUERY_STATE_STARTED) { + r600_query_end(ctx, query); + query->state |= R600_QUERY_STATE_SUSPENDED; + } + } +} + +void r600_context_queries_resume(struct r600_context *ctx) +{ + struct r600_query *query; + + LIST_FOR_EACH_ENTRY(query, &ctx->query_list, list) { + if (query->state & R600_QUERY_STATE_SUSPENDED) { + r600_query_begin(ctx, query); + query->state ^= R600_QUERY_STATE_SUSPENDED; + } + } +} diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h index 7a9025ad3c2..08e243b00d0 100644 --- a/src/gallium/winsys/r600/drm/r600_priv.h +++ b/src/gallium/winsys/r600/drm/r600_priv.h @@ -30,27 +30,152 @@ #include <stdint.h> #include <stdlib.h> #include <assert.h> +#include <pipebuffer/pb_bufmgr.h> +#include "util/u_double_list.h" #include "r600.h" - struct radeon { int fd; int refcount; unsigned device; unsigned family; + enum chip_class chip_class; + struct pb_manager *kman; /* kernel bo manager */ + struct pb_manager *cman; /* cached bo manager */ + struct r600_tiling_info tiling_info; }; struct radeon *r600_new(int fd, unsigned device); void r600_delete(struct radeon *r600); struct r600_reg { - unsigned need_bo; - unsigned flush_flags; - unsigned offset; + unsigned opcode; + unsigned offset_base; + unsigned offset; + unsigned need_bo; + unsigned flush_flags; + unsigned flush_mask; +}; + +struct radeon_bo { + struct pipe_reference reference; + unsigned handle; + unsigned size; + unsigned alignment; + unsigned map_count; + void *data; + struct list_head fencedlist; + unsigned fence; + struct r600_context *ctx; + boolean shared; + struct r600_reloc *reloc; + unsigned reloc_id; + unsigned last_flush; +}; + +struct r600_bo { + struct pipe_reference reference; + struct pb_buffer *pb; + unsigned size; }; /* radeon_pciid.c */ unsigned radeon_family_from_device(unsigned device); +/* r600_drm.c */ +struct radeon *radeon_decref(struct radeon *radeon); + +/* radeon_bo.c */ +struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, + unsigned size, unsigned alignment, void *ptr); +void radeon_bo_reference(struct radeon *radeon, struct radeon_bo **dst, + struct radeon_bo *src); +int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo); +int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain); +void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr); +int radeon_bo_fencelist(struct radeon *radeon, struct radeon_bo **bolist, uint32_t num_bo); + + +/* radeon_bo_pb.c */ +struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf); +struct pb_manager *radeon_bo_pbmgr_create(struct radeon *radeon); +struct pb_buffer *radeon_bo_pb_create_buffer_from_handle(struct pb_manager *_mgr, + uint32_t handle); + +/* r600_hw_context.c */ +int r600_context_init_fence(struct r600_context *ctx); +void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo); +void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags, + unsigned flush_mask, struct r600_bo *rbo); +struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset); +int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg); + +/* r600_bo.c */ +unsigned r600_bo_get_handle(struct r600_bo *bo); +unsigned r600_bo_get_size(struct r600_bo *bo); +static INLINE struct radeon_bo *r600_bo_get_bo(struct r600_bo *bo) +{ + return radeon_bo_pb_get_bo(bo->pb); +} + +#define CTX_RANGE_ID(ctx, offset) (((offset) >> (ctx)->hash_shift) & 255) +#define CTX_BLOCK_ID(ctx, offset) ((offset) & ((1 << (ctx)->hash_shift) - 1)) + +static void inline r600_context_reg(struct r600_context *ctx, + unsigned offset, unsigned value, + unsigned mask) +{ + struct r600_range *range; + struct r600_block *block; + unsigned id; + + range = &ctx->range[CTX_RANGE_ID(ctx, offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; + id = (offset - block->start_offset) >> 2; + block->reg[id] &= ~mask; + block->reg[id] |= value; + if (!(block->status & R600_BLOCK_STATUS_DIRTY)) { + ctx->pm4_dirty_cdwords += block->pm4_ndwords; + block->status |= R600_BLOCK_STATUS_ENABLED; + block->status |= R600_BLOCK_STATUS_DIRTY; + LIST_ADDTAIL(&block->list,&ctx->dirty); + } +} + +static inline void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block) +{ + int id; + + for (int j = 0; j < block->nreg; j++) { + if (block->pm4_bo_index[j]) { + /* find relocation */ + id = block->pm4_bo_index[j]; + r600_context_bo_reloc(ctx, + &block->pm4[block->reloc[id].bo_pm4_index], + block->reloc[id].bo); + r600_context_bo_flush(ctx, + block->reloc[id].flush_flags, + block->reloc[id].flush_mask, + block->reloc[id].bo); + } + } + memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, block->pm4_ndwords * 4); + ctx->pm4_cdwords += block->pm4_ndwords; + block->status ^= R600_BLOCK_STATUS_DIRTY; + LIST_DELINIT(&block->list); +} + +static inline int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo) +{ + bo->map_count++; + return 0; +} + +static inline void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo) +{ + bo->map_count--; + assert(bo->map_count >= 0); +} + #endif diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c deleted file mode 100644 index b04885a85f7..00000000000 --- a/src/gallium/winsys/r600/drm/r600_state.c +++ /dev/null @@ -1,658 +0,0 @@ -/* - * Copyright 2010 Jerome Glisse <[email protected]> - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jerome Glisse - */ -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <errno.h> -#include "radeon_priv.h" -#include "r600d.h" - -#include "util/u_memory.h" - -static int r600_state_pm4_resource(struct radeon_state *state); -static int r600_state_pm4_cb0(struct radeon_state *state); -static int r600_state_pm4_vgt(struct radeon_state *state); -static int r600_state_pm4_db(struct radeon_state *state); -static int r600_state_pm4_shader(struct radeon_state *state); -static int r600_state_pm4_draw(struct radeon_state *state); -static int r600_state_pm4_config(struct radeon_state *state); -static int r600_state_pm4_generic(struct radeon_state *state); -static int r600_state_pm4_query_begin(struct radeon_state *state); -static int r600_state_pm4_query_end(struct radeon_state *state); -static int r700_state_pm4_config(struct radeon_state *state); -static int r600_state_pm4_db_flush(struct radeon_state *state); -static int r600_state_pm4_cb_flush(struct radeon_state *state); - -static int eg_state_pm4_vgt(struct radeon_state *state); - -#include "r600_states.h" -#include "eg_states.h" - - -#define SUB_NONE(param) { { 0, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } } -#define SUB_PS(param) { R600_SHADER_PS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } -#define SUB_VS(param) { R600_SHADER_VS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } -#define SUB_GS(param) { R600_SHADER_GS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } -#define SUB_FS(param) { R600_SHADER_FS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } - -#define EG_SUB_NONE(param) { { 0, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) } } -#define EG_SUB_PS(param) { R600_SHADER_PS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) } -#define EG_SUB_VS(param) { R600_SHADER_VS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) } -#define EG_SUB_GS(param) { R600_SHADER_GS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) } -#define EG_SUB_FS(param) { R600_SHADER_FS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) } - -/* some of these are overriden at runtime for R700 */ -struct radeon_stype_info r600_stypes[] = { - { R600_STATE_CONFIG, 1, 0, r600_state_pm4_config, SUB_NONE(CONFIG), }, - { R600_STATE_CB_CNTL, 1, 0, r600_state_pm4_generic, SUB_NONE(CB_CNTL) }, - { R600_STATE_RASTERIZER, 1, 0, r600_state_pm4_generic, SUB_NONE(RASTERIZER) }, - { R600_STATE_VIEWPORT, 1, 0, r600_state_pm4_generic, SUB_NONE(VIEWPORT) }, - { R600_STATE_SCISSOR, 1, 0, r600_state_pm4_generic, SUB_NONE(SCISSOR) }, - { R600_STATE_BLEND, 1, 0, r600_state_pm4_generic, SUB_NONE(BLEND), }, - { R600_STATE_DSA, 1, 0, r600_state_pm4_generic, SUB_NONE(DSA), }, - { R600_STATE_SHADER, 1, 0, r600_state_pm4_shader, { SUB_PS(PS_SHADER), SUB_VS(VS_SHADER) } }, - { R600_STATE_CBUF, 1, 0, r600_state_pm4_shader, { SUB_PS(PS_CBUF), SUB_VS(VS_CBUF) } }, - { R600_STATE_CONSTANT, 256, 0x10, r600_state_pm4_generic, { SUB_PS(PS_CONSTANT), SUB_VS(VS_CONSTANT) } }, - { R600_STATE_RESOURCE, 160, 0x1c, r600_state_pm4_resource, { SUB_PS(PS_RESOURCE), SUB_VS(VS_RESOURCE), SUB_GS(GS_RESOURCE), SUB_FS(FS_RESOURCE)} }, - { R600_STATE_SAMPLER, 18, 0xc, r600_state_pm4_generic, { SUB_PS(PS_SAMPLER), SUB_VS(VS_SAMPLER), SUB_GS(GS_SAMPLER) } }, - { R600_STATE_SAMPLER_BORDER, 18, 0x10, r600_state_pm4_generic, { SUB_PS(PS_SAMPLER_BORDER), SUB_VS(VS_SAMPLER_BORDER), SUB_GS(GS_SAMPLER_BORDER) } }, - { R600_STATE_CB0, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB0) }, - { R600_STATE_CB1, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB1) }, - { R600_STATE_CB2, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB2) }, - { R600_STATE_CB3, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB3) }, - { R600_STATE_CB4, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB4) }, - { R600_STATE_CB5, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB5) }, - { R600_STATE_CB6, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB6) }, - { R600_STATE_CB7, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB7) }, - { R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, SUB_NONE(VGT_EVENT) }, - { R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, SUB_NONE(VGT_EVENT) }, - { R600_STATE_DB, 1, 0, r600_state_pm4_db, SUB_NONE(DB) }, - { R600_STATE_UCP, 1, 0, r600_state_pm4_generic, SUB_NONE(UCP) }, - { R600_STATE_VGT, 1, 0, r600_state_pm4_vgt, SUB_NONE(VGT) }, - { R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, SUB_NONE(DRAW) }, - { R600_STATE_CB_FLUSH, 1, 0, r600_state_pm4_cb_flush, SUB_NONE(CB_FLUSH) }, - { R600_STATE_DB_FLUSH, 1, 0, r600_state_pm4_db_flush, SUB_NONE(DB_FLUSH) }, -}; -#define STYPES_SIZE Elements(r600_stypes) - -struct radeon_stype_info eg_stypes[] = { - { R600_STATE_CONFIG, 1, 0, r700_state_pm4_config, EG_SUB_NONE(CONFIG), }, - { R600_STATE_CB_CNTL, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB_CNTL) }, - { R600_STATE_RASTERIZER, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(RASTERIZER) }, - { R600_STATE_VIEWPORT, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(VIEWPORT) }, - { R600_STATE_SCISSOR, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(SCISSOR) }, - { R600_STATE_BLEND, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(BLEND), }, - { R600_STATE_DSA, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(DSA), }, - { R600_STATE_SHADER, 1, 0, r600_state_pm4_shader, { EG_SUB_PS(PS_SHADER), EG_SUB_VS(VS_SHADER) } }, - { R600_STATE_CBUF, 1, 0, r600_state_pm4_shader, { EG_SUB_PS(PS_CBUF), EG_SUB_VS(VS_CBUF) } }, - { R600_STATE_RESOURCE, 176, 0x20, r600_state_pm4_resource, { EG_SUB_PS(PS_RESOURCE), EG_SUB_VS(VS_RESOURCE), EG_SUB_GS(GS_RESOURCE), EG_SUB_FS(FS_RESOURCE)} }, - { R600_STATE_SAMPLER, 18, 0xc, r600_state_pm4_generic, { EG_SUB_PS(PS_SAMPLER), EG_SUB_VS(VS_SAMPLER), EG_SUB_GS(GS_SAMPLER) } }, - { R600_STATE_SAMPLER_BORDER, 18, 0x10, r600_state_pm4_generic, { EG_SUB_PS(PS_SAMPLER_BORDER), EG_SUB_VS(VS_SAMPLER_BORDER), EG_SUB_GS(GS_SAMPLER_BORDER) } }, - { R600_STATE_CB0, 11, 0x3c, r600_state_pm4_generic, EG_SUB_NONE(CB) }, - { R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, EG_SUB_NONE(VGT_EVENT) }, - { R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, EG_SUB_NONE(VGT_EVENT) }, - { R600_STATE_DB, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(DB) }, - { R600_STATE_UCP, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(UCP) }, - { R600_STATE_VGT, 1, 0, eg_state_pm4_vgt, EG_SUB_NONE(VGT) }, - { R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, EG_SUB_NONE(DRAW) }, - { R600_STATE_CB_FLUSH, 1, 0, r600_state_pm4_cb_flush, EG_SUB_NONE(CB_FLUSH) }, - { R600_STATE_DB_FLUSH, 1, 0, r600_state_pm4_db_flush, EG_SUB_NONE(DB_FLUSH) }, - -}; -#define EG_STYPES_SIZE Elements(eg_stypes) - -static const struct radeon_register *get_regs(struct radeon_state *state) -{ - return state->stype->reginfo[state->shader_index].regs; -} - -/* - * r600/r700 state functions - */ -static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg) -{ - const struct radeon_register *regs = get_regs(state); - unsigned i; - int r; - - if (!offset) { - fprintf(stderr, "%s invalid register for state %d %d\n", - __func__, state->stype->stype, id); - return -EINVAL; - } - if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) { - state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, nreg); - state->pm4[state->cpm4++] = (offset - R600_CONFIG_REG_OFFSET) >> 2; - for (i = 0; i < nreg; i++) { - state->pm4[state->cpm4++] = state->states[id + i]; - } - for (i = 0; i < nreg; i++) { - if (regs[id + i].need_reloc) { - state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); - r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id); - if (r) - return r; - state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[regs[id + i].bo_id]); - } - } - return 0; - } - if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) { - state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONTEXT_REG, nreg); - state->pm4[state->cpm4++] = (offset - R600_CONTEXT_REG_OFFSET) >> 2; - for (i = 0; i < nreg; i++) { - state->pm4[state->cpm4++] = state->states[id + i]; - } - for (i = 0; i < nreg; i++) { - if (regs[id + i].need_reloc) { - state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); - r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id); - if (r) - return r; - state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[regs[id + i].bo_id]); - } - } - return 0; - } - if (offset >= R600_ALU_CONST_OFFSET && offset < R600_ALU_CONST_END) { - state->pm4[state->cpm4++] = PKT3(PKT3_SET_ALU_CONST, nreg); - state->pm4[state->cpm4++] = (offset - R600_ALU_CONST_OFFSET) >> 2; - for (i = 0; i < nreg; i++) { - state->pm4[state->cpm4++] = state->states[id + i]; - } - return 0; - } - if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) { - state->pm4[state->cpm4++] = PKT3(PKT3_SET_SAMPLER, nreg); - state->pm4[state->cpm4++] = (offset - R600_SAMPLER_OFFSET) >> 2; - for (i = 0; i < nreg; i++) { - state->pm4[state->cpm4++] = state->states[id + i]; - } - return 0; - } - fprintf(stderr, "%s unsupported offset 0x%08X\n", __func__, offset); - return -EINVAL; -} - -static int eg_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg) -{ - const struct radeon_register *regs = get_regs(state); - unsigned i; - int r; - - if (!offset) { - fprintf(stderr, "%s invalid register for state %d %d\n", - __func__, state->stype->stype, id); - return -EINVAL; - } - if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) { - state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, nreg); - state->pm4[state->cpm4++] = (offset - R600_CONFIG_REG_OFFSET) >> 2; - for (i = 0; i < nreg; i++) { - state->pm4[state->cpm4++] = state->states[id + i]; - } - for (i = 0; i < nreg; i++) { - if (regs[id + i].need_reloc) { - state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); - r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id); - if (r) - return r; - state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[regs[id + i].bo_id]); - } - } - return 0; - } - if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) { - state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONTEXT_REG, nreg); - state->pm4[state->cpm4++] = (offset - R600_CONTEXT_REG_OFFSET) >> 2; - for (i = 0; i < nreg; i++) { - state->pm4[state->cpm4++] = state->states[id + i]; - } - for (i = 0; i < nreg; i++) { - if (regs[id + i].need_reloc) { - state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); - r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id); - if (r) - return r; - state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[regs[id + i].bo_id]); - } - } - return 0; - } - if (offset >= EG_RESOURCE_OFFSET && offset < EG_RESOURCE_END) { - state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, nreg); - state->pm4[state->cpm4++] = (offset - EG_RESOURCE_OFFSET) >> 2; - for (i = 0; i < nreg; i++) { - state->pm4[state->cpm4++] = state->states[id + i]; - } - return 0; - } - if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) { - state->pm4[state->cpm4++] = PKT3(PKT3_SET_SAMPLER, nreg); - state->pm4[state->cpm4++] = (offset - R600_SAMPLER_OFFSET) >> 2; - for (i = 0; i < nreg; i++) { - state->pm4[state->cpm4++] = state->states[id + i]; - } - return 0; - } - fprintf(stderr, "%s unsupported offset 0x%08X\n", __func__, offset); - return -EINVAL; -} - - -static int r600_state_pm4_generic(struct radeon_state *state) -{ - const struct radeon_register *regs = get_regs(state); - unsigned i, offset, nreg, coffset, loffset, soffset; - unsigned start; - int r; - - if (!state->nstates) - return 0; - soffset = state->id * state->stype->stride; - offset = loffset = regs[0].offset + soffset; - start = 0; - for (i = 1, nreg = 1; i < state->nstates; i++) { - coffset = regs[i].offset + soffset; - if (coffset == (loffset + 4)) { - nreg++; - loffset = coffset; - } else { - if (state->radeon->family >= CHIP_CEDAR) - r = eg_state_pm4_bytecode(state, offset, start, nreg); - else - r = r600_state_pm4_bytecode(state, offset, start, nreg); - if (r) { - fprintf(stderr, "%s invalid 0x%08X %d\n", __func__, start, nreg); - return r; - } - offset = loffset = coffset; - nreg = 1; - start = i; - } - } - if (state->radeon->family >= CHIP_CEDAR) - r = eg_state_pm4_bytecode(state, offset, start, nreg); - else - r = r600_state_pm4_bytecode(state, offset, start, nreg); - return r; -} - -static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags, int bufs_are_cbs) -{ - unsigned i, j, add, size; - - state->nreloc = 0; - for (i = 0; i < state->nbo; i++) { - for (j = 0, add = 1; j < state->nreloc; j++) { - if (state->bo[state->reloc_bo_id[j]] == state->bo[i]) { - add = 0; - break; - } - } - if (add) { - state->reloc_bo_id[state->nreloc++] = i; - } - } - for (i = 0; i < state->nreloc; i++) { - size = (radeon_ws_bo_get_size(state->bo[state->reloc_bo_id[i]]) + 255) >> 8; - state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_SYNC, 3); - if (bufs_are_cbs) - flags |= S_0085F0_CB0_DEST_BASE_ENA(1 << i); - state->pm4[state->cpm4++] = flags; - state->pm4[state->cpm4++] = size; - state->pm4[state->cpm4++] = 0x00000000; - state->pm4[state->cpm4++] = 0x0000000A; - state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); - state->reloc_pm4_id[i] = state->cpm4; - state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[state->reloc_bo_id[i]]); - } -} - -static int r600_state_pm4_cb0(struct radeon_state *state) -{ - int r; - - r = r600_state_pm4_generic(state); - if (r) - return r; - state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0); - state->pm4[state->cpm4++] = 0x00000002; - return 0; -} - -static int r600_state_pm4_db(struct radeon_state *state) -{ - int r; - - r = r600_state_pm4_generic(state); - if (r) - return r; - state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0); - state->pm4[state->cpm4++] = 0x00000001; - return 0; -} - -static int r600_state_pm4_config(struct radeon_state *state) -{ - state->pm4[state->cpm4++] = PKT3(PKT3_START_3D_CMDBUF, 0); - state->pm4[state->cpm4++] = 0x00000000; - state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1); - state->pm4[state->cpm4++] = 0x80000000; - state->pm4[state->cpm4++] = 0x80000000; - state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0); - state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; - state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1); - state->pm4[state->cpm4++] = 0x00000010; - state->pm4[state->cpm4++] = 0x00028000; - return r600_state_pm4_generic(state); -} - -static int r600_state_pm4_query_begin(struct radeon_state *state) -{ - int r; - - state->cpm4 = 0; - state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2); - state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE; - state->pm4[state->cpm4++] = state->states[0]; - state->pm4[state->cpm4++] = 0x0; - state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); - r = radeon_state_reloc(state, state->cpm4, 0); - if (r) - return r; - state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[0]); - return 0; -} - -static int r600_state_pm4_query_end(struct radeon_state *state) -{ - int r; - - state->cpm4 = 0; - state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2); - state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE; - state->pm4[state->cpm4++] = state->states[0]; - state->pm4[state->cpm4++] = 0x0; - state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); - r = radeon_state_reloc(state, state->cpm4, 0); - if (r) - return r; - state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[0]); - return 0; -} - -static int r700_state_pm4_config(struct radeon_state *state) -{ - state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1); - state->pm4[state->cpm4++] = 0x80000000; - state->pm4[state->cpm4++] = 0x80000000; - state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0); - state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; - state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1); - state->pm4[state->cpm4++] = 0x00000010; - state->pm4[state->cpm4++] = 0x00028000; - return r600_state_pm4_generic(state); -} - -static int r600_state_pm4_shader(struct radeon_state *state) -{ - r600_state_pm4_with_flush(state, S_0085F0_SH_ACTION_ENA(1), 0); - return r600_state_pm4_generic(state); -} - -static int eg_state_pm4_vgt(struct radeon_state *state) -{ - int r; - r = eg_state_pm4_bytecode(state, R_028400_VGT_MAX_VTX_INDX, EG_VGT__VGT_MAX_VTX_INDX, 1); - if (r) - return r; - r = eg_state_pm4_bytecode(state, R_028404_VGT_MIN_VTX_INDX, EG_VGT__VGT_MIN_VTX_INDX, 1); - if (r) - return r; - r = eg_state_pm4_bytecode(state, R_028408_VGT_INDX_OFFSET, EG_VGT__VGT_INDX_OFFSET, 1); - if (r) - return r; - r = eg_state_pm4_bytecode(state, R_008958_VGT_PRIMITIVE_TYPE, EG_VGT__VGT_PRIMITIVE_TYPE, 1); - if (r) - return r; - state->pm4[state->cpm4++] = PKT3(PKT3_INDEX_TYPE, 0); - state->pm4[state->cpm4++] = state->states[EG_VGT__VGT_DMA_INDEX_TYPE]; - state->pm4[state->cpm4++] = PKT3(PKT3_NUM_INSTANCES, 0); - state->pm4[state->cpm4++] = state->states[EG_VGT__VGT_DMA_NUM_INSTANCES]; - return 0; -} - -static int r600_state_pm4_vgt(struct radeon_state *state) -{ - int r; - - r = r600_state_pm4_bytecode(state, R_028400_VGT_MAX_VTX_INDX, R600_VGT__VGT_MAX_VTX_INDX, 1); - if (r) - return r; - r = r600_state_pm4_bytecode(state, R_028404_VGT_MIN_VTX_INDX, R600_VGT__VGT_MIN_VTX_INDX, 1); - if (r) - return r; - r = r600_state_pm4_bytecode(state, R_028408_VGT_INDX_OFFSET, R600_VGT__VGT_INDX_OFFSET, 1); - if (r) - return r; - r = r600_state_pm4_bytecode(state, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX, 1); - if (r) - return r; - r = r600_state_pm4_bytecode(state, R_008958_VGT_PRIMITIVE_TYPE, R600_VGT__VGT_PRIMITIVE_TYPE, 1); - if (r) - return r; - state->pm4[state->cpm4++] = PKT3(PKT3_INDEX_TYPE, 0); - state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_INDEX_TYPE]; - state->pm4[state->cpm4++] = PKT3(PKT3_NUM_INSTANCES, 0); - state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_NUM_INSTANCES]; - return 0; -} - -static int r600_state_pm4_draw(struct radeon_state *state) -{ - int r; - - if (state->nbo) { - state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX, 3); - state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DMA_BASE]; - state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DMA_BASE_HI]; - state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES]; - state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR]; - state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); - r = radeon_state_reloc(state, state->cpm4, 0); - if (r) - return r; - state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[0]); - } else { - state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1); - state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES]; - state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR]; - } - state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0); - state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; - - return 0; -} - -static int r600_state_pm4_cb_flush(struct radeon_state *state) -{ - if (!state->nbo) - return 0; - - r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1), 1); - - return 0; -} - -static int r600_state_pm4_db_flush(struct radeon_state *state) -{ - if (!state->nbo) - return 0; - - r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) | - S_0085F0_DB_DEST_BASE_ENA(1), 0); - - return 0; -} - -static int r600_state_pm4_resource(struct radeon_state *state) -{ - u32 flags, type, nbo, offset, soffset; - int r, nres; - const struct radeon_register *regs = get_regs(state); - - soffset = state->id * state->stype->stride; - if (state->radeon->family >= CHIP_CEDAR) - type = G_038018_TYPE(state->states[7]); - else - type = G_038018_TYPE(state->states[6]); - - switch (type) { - case 2: - flags = S_0085F0_TC_ACTION_ENA(1); - nbo = 2; - break; - case 3: - flags = S_0085F0_VC_ACTION_ENA(1); - nbo = 1; - break; - default: - return 0; - } - if (state->nbo != nbo) { - fprintf(stderr, "%s need %d bo got %d\n", __func__, nbo, state->nbo); - return -EINVAL; - } - r600_state_pm4_with_flush(state, flags, 0); - offset = regs[0].offset + soffset; - if (state->radeon->family >= CHIP_CEDAR) - nres = 8; - else - nres = 7; - state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, nres); - if (state->radeon->family >= CHIP_CEDAR) - state->pm4[state->cpm4++] = (offset - EG_RESOURCE_OFFSET) >> 2; - else - state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2; - state->pm4[state->cpm4++] = state->states[0]; - state->pm4[state->cpm4++] = state->states[1]; - state->pm4[state->cpm4++] = state->states[2]; - state->pm4[state->cpm4++] = state->states[3]; - state->pm4[state->cpm4++] = state->states[4]; - state->pm4[state->cpm4++] = state->states[5]; - state->pm4[state->cpm4++] = state->states[6]; - if (state->radeon->family >= CHIP_CEDAR) - state->pm4[state->cpm4++] = state->states[7]; - - state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); - r = radeon_state_reloc(state, state->cpm4, 0); - if (r) - return r; - state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[0]); - if (type == 2) { - state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); - r = radeon_state_reloc(state, state->cpm4, 1); - if (r) - return r; - state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[1]); - } - return 0; -} - - -static void r600_modify_type_array(struct radeon *radeon) -{ - int i; - switch (radeon->family) { - case CHIP_RV770: - case CHIP_RV730: - case CHIP_RV710: - case CHIP_RV740: - break; - default: - return; - } - - /* r700 needs some mods */ - for (i = 0; i < radeon->nstype; i++) { - struct radeon_stype_info *info = &radeon->stype[i]; - - switch(info->stype) { - case R600_STATE_CONFIG: - info->pm4 = r700_state_pm4_config; - break; - case R600_STATE_CB0: - info->pm4 = r600_state_pm4_generic; - break; - case R600_STATE_DB: - info->pm4 = r600_state_pm4_generic; - break; - }; - } -} - -static void build_types_array(struct radeon *radeon, struct radeon_stype_info *types, int size) -{ - int i, j; - int id = 0; - - for (i = 0; i < size; i++) { - types[i].base_id = id; - types[i].npm4 = 128; - if (types[i].reginfo[0].shader_type == 0) { - id += types[i].num; - } else { - for (j = 0; j < R600_SHADER_MAX; j++) { - if (types[i].reginfo[j].shader_type) - id += types[i].num; - } - } - } - radeon->max_states = id; - radeon->stype = types; - radeon->nstype = size; -} - -static void r600_build_types_array(struct radeon *radeon) -{ - build_types_array(radeon, r600_stypes, STYPES_SIZE); - r600_modify_type_array(radeon); -} - -static void eg_build_types_array(struct radeon *radeon) -{ - build_types_array(radeon, eg_stypes, EG_STYPES_SIZE); -} - -int r600_init(struct radeon *radeon) -{ - if (radeon->family >= CHIP_CEDAR) - eg_build_types_array(radeon); - else - r600_build_types_array(radeon); - return 0; -} diff --git a/src/gallium/winsys/r600/drm/r600_state2.c b/src/gallium/winsys/r600/drm/r600_state2.c deleted file mode 100644 index b3d618748d1..00000000000 --- a/src/gallium/winsys/r600/drm/r600_state2.c +++ /dev/null @@ -1,1056 +0,0 @@ -/* - * Copyright 2010 Jerome Glisse <[email protected]> - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jerome Glisse - */ -#include <errno.h> -#include <stdint.h> -#include <string.h> -#include <stdlib.h> -#include <assert.h> -#include "xf86drm.h" -#include "r600.h" -#include "r600d.h" -#include "r600_priv.h" -#include "radeon_drm.h" -#include "bof.h" -#include "pipe/p_compiler.h" -#include "util/u_inlines.h" -#include <pipebuffer/pb_bufmgr.h> - -struct radeon_ws_bo { - struct pipe_reference reference; - struct pb_buffer *pb; -}; - -struct radeon_bo { - struct pipe_reference reference; - unsigned handle; - unsigned size; - unsigned alignment; - unsigned map_count; - void *data; -}; -struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf); -int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo); -void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo); - -unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *pb_bo); - -static int r600_group_id_register_offset(unsigned offset) -{ - if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) { - return R600_GROUP_CONFIG; - } - if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) { - return R600_GROUP_CONTEXT; - } - if (offset >= R600_ALU_CONST_OFFSET && offset < R600_ALU_CONST_END) { - return R600_GROUP_ALU_CONST; - } - if (offset >= R600_RESOURCE_OFFSET && offset < R600_RESOURCE_END) { - return R600_GROUP_RESOURCE; - } - if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) { - return R600_GROUP_SAMPLER; - } - if (offset >= R600_CTL_CONST_OFFSET && offset < R600_CTL_CONST_END) { - return R600_GROUP_CTL_CONST; - } - if (offset >= R600_LOOP_CONST_OFFSET && offset < R600_LOOP_CONST_END) { - return R600_GROUP_LOOP_CONST; - } - if (offset >= R600_BOOL_CONST_OFFSET && offset < R600_BOOL_CONST_END) { - return R600_GROUP_BOOL_CONST; - } - return -1; -} - -static int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg) -{ - struct r600_group_block *block, *tmp; - struct r600_group *group; - int group_id, id; - - for (unsigned i = 0, n = 0; i < nreg; i += n) { - u32 j, r; - /* find number of consecutive registers */ - for (j = i + 1, r = reg[i].offset + 4, n = 1; j < (nreg - i); j++, n++, r+=4) { - if (r != reg[j].offset) { - break; - } - } - - /* find into which group this block is */ - group_id = r600_group_id_register_offset(reg[i].offset); - assert(group_id >= 0); - group = &ctx->groups[group_id]; - - /* allocate new block */ - tmp = realloc(group->blocks, (group->nblocks + 1) * sizeof(struct r600_group_block)); - if (tmp == NULL) { - return -ENOMEM; - } - group->blocks = tmp; - block = &group->blocks[group->nblocks++]; - for (int j = 0; j < n; j++) { - group->offset_block_id[((reg[i].offset - group->start_offset) >> 2) + j] = group->nblocks - 1; - } - - /* initialize block */ - memset(block, 0, sizeof(struct r600_group_block)); - block->start_offset = reg[i].offset; - block->pm4_ndwords = n; - block->nreg = n; - for (j = 0; j < n; j++) { - if (reg[i+j].need_bo) { - block->nbo++; - assert(block->nbo < R600_BLOCK_MAX_BO); - block->pm4_bo_index[j] = block->nbo; - block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0); - block->pm4[block->pm4_ndwords++] = 0x00000000; - block->reloc[block->nbo].bo_pm4_index[block->reloc[block->nbo].nreloc++] = block->pm4_ndwords - 1; - } - } - for (j = 0; j < n; j++) { - if (reg[i+j].flush_flags) { - block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_SYNC, 3); - block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags; - block->pm4[block->pm4_ndwords++] = 0xFFFFFFFF; - block->pm4[block->pm4_ndwords++] = 0x00000000; - block->pm4[block->pm4_ndwords++] = 0x0000000A; - block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0); - block->pm4[block->pm4_ndwords++] = 0x00000000; - id = block->pm4_bo_index[j]; - block->reloc[id].bo_pm4_index[block->reloc[id].nreloc++] = block->pm4_ndwords - 1; - } - } - /* check that we stay in limit */ - assert(block->pm4_ndwords < R600_BLOCK_MAX_REG); - } - return 0; -} - -static int r600_group_init(struct r600_group *group, unsigned start_offset, unsigned end_offset) -{ - group->start_offset = start_offset; - group->end_offset = end_offset; - group->nblocks = 0; - group->blocks = NULL; - group->offset_block_id = calloc((end_offset - start_offset) >> 2, sizeof(unsigned)); - if (group->offset_block_id == NULL) - return -ENOMEM; - return 0; -} - -static void r600_group_fini(struct r600_group *group) -{ - free(group->offset_block_id); - free(group->blocks); -} - -/* R600/R700 configuration */ -static const struct r600_reg r600_reg_list[] = { - {0, 0, R_008C00_SQ_CONFIG}, - {0, 0, R_008C04_SQ_GPR_RESOURCE_MGMT_1}, - {0, 0, R_008C08_SQ_GPR_RESOURCE_MGMT_2}, - {0, 0, R_008C0C_SQ_THREAD_RESOURCE_MGMT}, - {0, 0, R_008C10_SQ_STACK_RESOURCE_MGMT_1}, - {0, 0, R_008C14_SQ_STACK_RESOURCE_MGMT_2}, - {0, 0, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ}, - {0, 0, R_009508_TA_CNTL_AUX}, - {0, 0, R_009714_VC_ENHANCE}, - {0, 0, R_009830_DB_DEBUG}, - {0, 0, R_009838_DB_WATERMARKS}, - {0, 0, R_028350_SX_MISC}, - {0, 0, R_0286C8_SPI_THREAD_GROUPING}, - {0, 0, R_0288A8_SQ_ESGS_RING_ITEMSIZE}, - {0, 0, R_0288AC_SQ_GSVS_RING_ITEMSIZE}, - {0, 0, R_0288B0_SQ_ESTMP_RING_ITEMSIZE}, - {0, 0, R_0288B4_SQ_GSTMP_RING_ITEMSIZE}, - {0, 0, R_0288B8_SQ_VSTMP_RING_ITEMSIZE}, - {0, 0, R_0288BC_SQ_PSTMP_RING_ITEMSIZE}, - {0, 0, R_0288C0_SQ_FBUF_RING_ITEMSIZE}, - {0, 0, R_0288C4_SQ_REDUC_RING_ITEMSIZE}, - {0, 0, R_0288C8_SQ_GS_VERT_ITEMSIZE}, - {0, 0, R_028A10_VGT_OUTPUT_PATH_CNTL}, - {0, 0, R_028A14_VGT_HOS_CNTL}, - {0, 0, R_028A18_VGT_HOS_MAX_TESS_LEVEL}, - {0, 0, R_028A1C_VGT_HOS_MIN_TESS_LEVEL}, - {0, 0, R_028A20_VGT_HOS_REUSE_DEPTH}, - {0, 0, R_028A24_VGT_GROUP_PRIM_TYPE}, - {0, 0, R_028A28_VGT_GROUP_FIRST_DECR}, - {0, 0, R_028A2C_VGT_GROUP_DECR}, - {0, 0, R_028A30_VGT_GROUP_VECT_0_CNTL}, - {0, 0, R_028A34_VGT_GROUP_VECT_1_CNTL}, - {0, 0, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL}, - {0, 0, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL}, - {0, 0, R_028A40_VGT_GS_MODE}, - {0, 0, R_028A4C_PA_SC_MODE_CNTL}, - {0, 0, R_028AB0_VGT_STRMOUT_EN}, - {0, 0, R_028AB4_VGT_REUSE_OFF}, - {0, 0, R_028AB8_VGT_VTX_CNT_EN}, - {0, 0, R_028B20_VGT_STRMOUT_BUFFER_EN}, - {0, 0, R_028028_DB_STENCIL_CLEAR}, - {0, 0, R_02802C_DB_DEPTH_CLEAR}, - {1, 0, R_028040_CB_COLOR0_BASE}, - {0, 0, R_0280A0_CB_COLOR0_INFO}, - {0, 0, R_028060_CB_COLOR0_SIZE}, - {0, 0, R_028080_CB_COLOR0_VIEW}, - {1, 0, R_0280E0_CB_COLOR0_FRAG}, - {1, 0, R_0280C0_CB_COLOR0_TILE}, - {0, 0, R_028100_CB_COLOR0_MASK}, - {1, 0, R_028044_CB_COLOR1_BASE}, - {0, 0, R_0280A4_CB_COLOR1_INFO}, - {0, 0, R_028064_CB_COLOR1_SIZE}, - {0, 0, R_028084_CB_COLOR1_VIEW}, - {1, 0, R_0280E4_CB_COLOR1_FRAG}, - {1, 0, R_0280C4_CB_COLOR1_TILE}, - {0, 0, R_028104_CB_COLOR1_MASK}, - {1, 0, R_028048_CB_COLOR2_BASE}, - {0, 0, R_0280A8_CB_COLOR2_INFO}, - {0, 0, R_028068_CB_COLOR2_SIZE}, - {0, 0, R_028088_CB_COLOR2_VIEW}, - {1, 0, R_0280E8_CB_COLOR2_FRAG}, - {1, 0, R_0280C8_CB_COLOR2_TILE}, - {0, 0, R_028108_CB_COLOR2_MASK}, - {1, 0, R_02804C_CB_COLOR3_BASE}, - {0, 0, R_0280AC_CB_COLOR3_INFO}, - {0, 0, R_02806C_CB_COLOR3_SIZE}, - {0, 0, R_02808C_CB_COLOR3_VIEW}, - {1, 0, R_0280EC_CB_COLOR3_FRAG}, - {1, 0, R_0280CC_CB_COLOR3_TILE}, - {0, 0, R_02810C_CB_COLOR3_MASK}, - {1, 0, R_028050_CB_COLOR4_BASE}, - {0, 0, R_0280B0_CB_COLOR4_INFO}, - {0, 0, R_028070_CB_COLOR4_SIZE}, - {0, 0, R_028090_CB_COLOR4_VIEW}, - {1, 0, R_0280F0_CB_COLOR4_FRAG}, - {1, 0, R_0280D0_CB_COLOR4_TILE}, - {0, 0, R_028110_CB_COLOR4_MASK}, - {1, 0, R_028054_CB_COLOR5_BASE}, - {0, 0, R_0280B4_CB_COLOR5_INFO}, - {0, 0, R_028074_CB_COLOR5_SIZE}, - {0, 0, R_028094_CB_COLOR5_VIEW}, - {1, 0, R_0280F4_CB_COLOR5_FRAG}, - {1, 0, R_0280D4_CB_COLOR5_TILE}, - {0, 0, R_028114_CB_COLOR5_MASK}, - {1, 0, R_028058_CB_COLOR6_BASE}, - {0, 0, R_0280B8_CB_COLOR6_INFO}, - {0, 0, R_028078_CB_COLOR6_SIZE}, - {0, 0, R_028098_CB_COLOR6_VIEW}, - {1, 0, R_0280F8_CB_COLOR6_FRAG}, - {1, 0, R_0280D8_CB_COLOR6_TILE}, - {0, 0, R_028118_CB_COLOR6_MASK}, - {1, 0, R_02805C_CB_COLOR7_BASE}, - {0, 0, R_0280BC_CB_COLOR7_INFO}, - {0, 0, R_02807C_CB_COLOR7_SIZE}, - {0, 0, R_02809C_CB_COLOR7_VIEW}, - {1, 0, R_0280FC_CB_COLOR7_FRAG}, - {1, 0, R_0280DC_CB_COLOR7_TILE}, - {0, 0, R_02811C_CB_COLOR7_MASK}, - {0, 0, R_028120_CB_CLEAR_RED}, - {0, 0, R_028124_CB_CLEAR_GREEN}, - {0, 0, R_028128_CB_CLEAR_BLUE}, - {0, 0, R_02812C_CB_CLEAR_ALPHA}, - {0, 0, R_02823C_CB_SHADER_MASK}, - {0, 0, R_028238_CB_TARGET_MASK}, - {0, 0, R_028410_SX_ALPHA_TEST_CONTROL}, - {0, 0, R_028414_CB_BLEND_RED}, - {0, 0, R_028418_CB_BLEND_GREEN}, - {0, 0, R_02841C_CB_BLEND_BLUE}, - {0, 0, R_028420_CB_BLEND_ALPHA}, - {0, 0, R_028424_CB_FOG_RED}, - {0, 0, R_028428_CB_FOG_GREEN}, - {0, 0, R_02842C_CB_FOG_BLUE}, - {0, 0, R_028430_DB_STENCILREFMASK}, - {0, 0, R_028434_DB_STENCILREFMASK_BF}, - {0, 0, R_028438_SX_ALPHA_REF}, - {0, 0, R_0286DC_SPI_FOG_CNTL}, - {0, 0, R_0286E0_SPI_FOG_FUNC_SCALE}, - {0, 0, R_0286E4_SPI_FOG_FUNC_BIAS}, - {0, 0, R_028780_CB_BLEND0_CONTROL}, - {0, 0, R_028784_CB_BLEND1_CONTROL}, - {0, 0, R_028788_CB_BLEND2_CONTROL}, - {0, 0, R_02878C_CB_BLEND3_CONTROL}, - {0, 0, R_028790_CB_BLEND4_CONTROL}, - {0, 0, R_028794_CB_BLEND5_CONTROL}, - {0, 0, R_028798_CB_BLEND6_CONTROL}, - {0, 0, R_02879C_CB_BLEND7_CONTROL}, - {0, 0, R_0287A0_CB_SHADER_CONTROL}, - {0, 0, R_028800_DB_DEPTH_CONTROL}, - {0, 0, R_028804_CB_BLEND_CONTROL}, - {0, 0, R_028808_CB_COLOR_CONTROL}, - {0, 0, R_02880C_DB_SHADER_CONTROL}, - {0, 0, R_028C04_PA_SC_AA_CONFIG}, - {0, 0, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX}, - {0, 0, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX}, - {0, 0, R_028C30_CB_CLRCMP_CONTROL}, - {0, 0, R_028C34_CB_CLRCMP_SRC}, - {0, 0, R_028C38_CB_CLRCMP_DST}, - {0, 0, R_028C3C_CB_CLRCMP_MSK}, - {0, 0, R_028C48_PA_SC_AA_MASK}, - {0, 0, R_028D2C_DB_SRESULTS_COMPARE_STATE1}, - {0, 0, R_028D44_DB_ALPHA_TO_MASK}, - {1, 0, R_02800C_DB_DEPTH_BASE}, - {0, 0, R_028000_DB_DEPTH_SIZE}, - {0, 0, R_028004_DB_DEPTH_VIEW}, - {0, 0, R_028010_DB_DEPTH_INFO}, - {0, 0, R_028D0C_DB_RENDER_CONTROL}, - {0, 0, R_028D10_DB_RENDER_OVERRIDE}, - {0, 0, R_028D24_DB_HTILE_SURFACE}, - {0, 0, R_028D30_DB_PRELOAD_CONTROL}, - {0, 0, R_028D34_DB_PREFETCH_LIMIT}, - {0, 0, R_028030_PA_SC_SCREEN_SCISSOR_TL}, - {0, 0, R_028034_PA_SC_SCREEN_SCISSOR_BR}, - {0, 0, R_028200_PA_SC_WINDOW_OFFSET}, - {0, 0, R_028204_PA_SC_WINDOW_SCISSOR_TL}, - {0, 0, R_028208_PA_SC_WINDOW_SCISSOR_BR}, - {0, 0, R_02820C_PA_SC_CLIPRECT_RULE}, - {0, 0, R_028210_PA_SC_CLIPRECT_0_TL}, - {0, 0, R_028214_PA_SC_CLIPRECT_0_BR}, - {0, 0, R_028218_PA_SC_CLIPRECT_1_TL}, - {0, 0, R_02821C_PA_SC_CLIPRECT_1_BR}, - {0, 0, R_028220_PA_SC_CLIPRECT_2_TL}, - {0, 0, R_028224_PA_SC_CLIPRECT_2_BR}, - {0, 0, R_028228_PA_SC_CLIPRECT_3_TL}, - {0, 0, R_02822C_PA_SC_CLIPRECT_3_BR}, - {0, 0, R_028230_PA_SC_EDGERULE}, - {0, 0, R_028240_PA_SC_GENERIC_SCISSOR_TL}, - {0, 0, R_028244_PA_SC_GENERIC_SCISSOR_BR}, - {0, 0, R_028250_PA_SC_VPORT_SCISSOR_0_TL}, - {0, 0, R_028254_PA_SC_VPORT_SCISSOR_0_BR}, - {0, 0, R_0282D0_PA_SC_VPORT_ZMIN_0}, - {0, 0, R_0282D4_PA_SC_VPORT_ZMAX_0}, - {0, 0, R_02843C_PA_CL_VPORT_XSCALE_0}, - {0, 0, R_028440_PA_CL_VPORT_XOFFSET_0}, - {0, 0, R_028444_PA_CL_VPORT_YSCALE_0}, - {0, 0, R_028448_PA_CL_VPORT_YOFFSET_0}, - {0, 0, R_02844C_PA_CL_VPORT_ZSCALE_0}, - {0, 0, R_028450_PA_CL_VPORT_ZOFFSET_0}, - {0, 0, R_0286D4_SPI_INTERP_CONTROL_0}, - {0, 0, R_028810_PA_CL_CLIP_CNTL}, - {0, 0, R_028814_PA_SU_SC_MODE_CNTL}, - {0, 0, R_028818_PA_CL_VTE_CNTL}, - {0, 0, R_02881C_PA_CL_VS_OUT_CNTL}, - {0, 0, R_028820_PA_CL_NANINF_CNTL}, - {0, 0, R_028A00_PA_SU_POINT_SIZE}, - {0, 0, R_028A04_PA_SU_POINT_MINMAX}, - {0, 0, R_028A08_PA_SU_LINE_CNTL}, - {0, 0, R_028A0C_PA_SC_LINE_STIPPLE}, - {0, 0, R_028A48_PA_SC_MPASS_PS_CNTL}, - {0, 0, R_028C00_PA_SC_LINE_CNTL}, - {0, 0, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ}, - {0, 0, R_028C10_PA_CL_GB_VERT_DISC_ADJ}, - {0, 0, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ}, - {0, 0, R_028C18_PA_CL_GB_HORZ_DISC_ADJ}, - {0, 0, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL}, - {0, 0, R_028DFC_PA_SU_POLY_OFFSET_CLAMP}, - {0, 0, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE}, - {0, 0, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET}, - {0, 0, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE}, - {0, 0, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET}, - {0, 0, R_028E20_PA_CL_UCP0_X}, - {0, 0, R_028E24_PA_CL_UCP0_Y}, - {0, 0, R_028E28_PA_CL_UCP0_Z}, - {0, 0, R_028E2C_PA_CL_UCP0_W}, - {0, 0, R_028E30_PA_CL_UCP1_X}, - {0, 0, R_028E34_PA_CL_UCP1_Y}, - {0, 0, R_028E38_PA_CL_UCP1_Z}, - {0, 0, R_028E3C_PA_CL_UCP1_W}, - {0, 0, R_028E40_PA_CL_UCP2_X}, - {0, 0, R_028E44_PA_CL_UCP2_Y}, - {0, 0, R_028E48_PA_CL_UCP2_Z}, - {0, 0, R_028E4C_PA_CL_UCP2_W}, - {0, 0, R_028E50_PA_CL_UCP3_X}, - {0, 0, R_028E54_PA_CL_UCP3_Y}, - {0, 0, R_028E58_PA_CL_UCP3_Z}, - {0, 0, R_028E5C_PA_CL_UCP3_W}, - {0, 0, R_028E60_PA_CL_UCP4_X}, - {0, 0, R_028E64_PA_CL_UCP4_Y}, - {0, 0, R_028E68_PA_CL_UCP4_Z}, - {0, 0, R_028E6C_PA_CL_UCP4_W}, - {0, 0, R_028E70_PA_CL_UCP5_X}, - {0, 0, R_028E74_PA_CL_UCP5_Y}, - {0, 0, R_028E78_PA_CL_UCP5_Z}, - {0, 0, R_028E7C_PA_CL_UCP5_W}, - {0, 0, R_028380_SQ_VTX_SEMANTIC_0}, - {0, 0, R_028384_SQ_VTX_SEMANTIC_1}, - {0, 0, R_028388_SQ_VTX_SEMANTIC_2}, - {0, 0, R_02838C_SQ_VTX_SEMANTIC_3}, - {0, 0, R_028390_SQ_VTX_SEMANTIC_4}, - {0, 0, R_028394_SQ_VTX_SEMANTIC_5}, - {0, 0, R_028398_SQ_VTX_SEMANTIC_6}, - {0, 0, R_02839C_SQ_VTX_SEMANTIC_7}, - {0, 0, R_0283A0_SQ_VTX_SEMANTIC_8}, - {0, 0, R_0283A4_SQ_VTX_SEMANTIC_9}, - {0, 0, R_0283A8_SQ_VTX_SEMANTIC_10}, - {0, 0, R_0283AC_SQ_VTX_SEMANTIC_11}, - {0, 0, R_0283B0_SQ_VTX_SEMANTIC_12}, - {0, 0, R_0283B4_SQ_VTX_SEMANTIC_13}, - {0, 0, R_0283B8_SQ_VTX_SEMANTIC_14}, - {0, 0, R_0283BC_SQ_VTX_SEMANTIC_15}, - {0, 0, R_0283C0_SQ_VTX_SEMANTIC_16}, - {0, 0, R_0283C4_SQ_VTX_SEMANTIC_17}, - {0, 0, R_0283C8_SQ_VTX_SEMANTIC_18}, - {0, 0, R_0283CC_SQ_VTX_SEMANTIC_19}, - {0, 0, R_0283D0_SQ_VTX_SEMANTIC_20}, - {0, 0, R_0283D4_SQ_VTX_SEMANTIC_21}, - {0, 0, R_0283D8_SQ_VTX_SEMANTIC_22}, - {0, 0, R_0283DC_SQ_VTX_SEMANTIC_23}, - {0, 0, R_0283E0_SQ_VTX_SEMANTIC_24}, - {0, 0, R_0283E4_SQ_VTX_SEMANTIC_25}, - {0, 0, R_0283E8_SQ_VTX_SEMANTIC_26}, - {0, 0, R_0283EC_SQ_VTX_SEMANTIC_27}, - {0, 0, R_0283F0_SQ_VTX_SEMANTIC_28}, - {0, 0, R_0283F4_SQ_VTX_SEMANTIC_29}, - {0, 0, R_0283F8_SQ_VTX_SEMANTIC_30}, - {0, 0, R_0283FC_SQ_VTX_SEMANTIC_31}, - {0, 0, R_028614_SPI_VS_OUT_ID_0}, - {0, 0, R_028618_SPI_VS_OUT_ID_1}, - {0, 0, R_02861C_SPI_VS_OUT_ID_2}, - {0, 0, R_028620_SPI_VS_OUT_ID_3}, - {0, 0, R_028624_SPI_VS_OUT_ID_4}, - {0, 0, R_028628_SPI_VS_OUT_ID_5}, - {0, 0, R_02862C_SPI_VS_OUT_ID_6}, - {0, 0, R_028630_SPI_VS_OUT_ID_7}, - {0, 0, R_028634_SPI_VS_OUT_ID_8}, - {0, 0, R_028638_SPI_VS_OUT_ID_9}, - {0, 0, R_0286C4_SPI_VS_OUT_CONFIG}, - {1, 0, R_028858_SQ_PGM_START_VS}, - {0, S_0085F0_SH_ACTION_ENA(1), R_028868_SQ_PGM_RESOURCES_VS}, - {1, 0, R_028894_SQ_PGM_START_FS}, - {0, S_0085F0_SH_ACTION_ENA(1), R_0288A4_SQ_PGM_RESOURCES_FS}, - {0, 0, R_0288D0_SQ_PGM_CF_OFFSET_VS}, - {0, 0, R_0288DC_SQ_PGM_CF_OFFSET_FS}, - {0, 0, R_028644_SPI_PS_INPUT_CNTL_0}, - {0, 0, R_028648_SPI_PS_INPUT_CNTL_1}, - {0, 0, R_02864C_SPI_PS_INPUT_CNTL_2}, - {0, 0, R_028650_SPI_PS_INPUT_CNTL_3}, - {0, 0, R_028654_SPI_PS_INPUT_CNTL_4}, - {0, 0, R_028658_SPI_PS_INPUT_CNTL_5}, - {0, 0, R_02865C_SPI_PS_INPUT_CNTL_6}, - {0, 0, R_028660_SPI_PS_INPUT_CNTL_7}, - {0, 0, R_028664_SPI_PS_INPUT_CNTL_8}, - {0, 0, R_028668_SPI_PS_INPUT_CNTL_9}, - {0, 0, R_02866C_SPI_PS_INPUT_CNTL_10}, - {0, 0, R_028670_SPI_PS_INPUT_CNTL_11}, - {0, 0, R_028674_SPI_PS_INPUT_CNTL_12}, - {0, 0, R_028678_SPI_PS_INPUT_CNTL_13}, - {0, 0, R_02867C_SPI_PS_INPUT_CNTL_14}, - {0, 0, R_028680_SPI_PS_INPUT_CNTL_15}, - {0, 0, R_028684_SPI_PS_INPUT_CNTL_16}, - {0, 0, R_028688_SPI_PS_INPUT_CNTL_17}, - {0, 0, R_02868C_SPI_PS_INPUT_CNTL_18}, - {0, 0, R_028690_SPI_PS_INPUT_CNTL_19}, - {0, 0, R_028694_SPI_PS_INPUT_CNTL_20}, - {0, 0, R_028698_SPI_PS_INPUT_CNTL_21}, - {0, 0, R_02869C_SPI_PS_INPUT_CNTL_22}, - {0, 0, R_0286A0_SPI_PS_INPUT_CNTL_23}, - {0, 0, R_0286A4_SPI_PS_INPUT_CNTL_24}, - {0, 0, R_0286A8_SPI_PS_INPUT_CNTL_25}, - {0, 0, R_0286AC_SPI_PS_INPUT_CNTL_26}, - {0, 0, R_0286B0_SPI_PS_INPUT_CNTL_27}, - {0, 0, R_0286B4_SPI_PS_INPUT_CNTL_28}, - {0, 0, R_0286B8_SPI_PS_INPUT_CNTL_29}, - {0, 0, R_0286BC_SPI_PS_INPUT_CNTL_30}, - {0, 0, R_0286C0_SPI_PS_INPUT_CNTL_31}, - {0, 0, R_0286CC_SPI_PS_IN_CONTROL_0}, - {0, 0, R_0286D0_SPI_PS_IN_CONTROL_1}, - {0, 0, R_0286D8_SPI_INPUT_Z}, - {1, S_0085F0_SH_ACTION_ENA(1), R_028840_SQ_PGM_START_PS}, - {0, 0, R_028850_SQ_PGM_RESOURCES_PS}, - {0, 0, R_028854_SQ_PGM_EXPORTS_PS}, - {0, 0, R_0288CC_SQ_PGM_CF_OFFSET_PS}, - {0, 0, R_008958_VGT_PRIMITIVE_TYPE}, - {0, 0, R_028400_VGT_MAX_VTX_INDX}, - {0, 0, R_028404_VGT_MIN_VTX_INDX}, - {0, 0, R_028408_VGT_INDX_OFFSET}, - {0, 0, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX}, - {0, 0, R_028A84_VGT_PRIMITIVEID_EN}, - {0, 0, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN}, - {0, 0, R_028AA0_VGT_INSTANCE_STEP_RATE_0}, - {0, 0, R_028AA4_VGT_INSTANCE_STEP_RATE_1}, -}; - -/* SHADER CONSTANT R600/R700 */ -static int r600_state_constant_init(struct r600_context *ctx, u32 offset) -{ - struct r600_reg r600_shader_constant[] = { - {0, 0, R_030000_SQ_ALU_CONSTANT0_0}, - {0, 0, R_030004_SQ_ALU_CONSTANT1_0}, - {0, 0, R_030008_SQ_ALU_CONSTANT2_0}, - {0, 0, R_03000C_SQ_ALU_CONSTANT3_0}, - }; - unsigned nreg = sizeof(r600_shader_constant)/sizeof(struct r600_reg); - - for (int i = 0; i < nreg; i++) { - r600_shader_constant[i].offset += offset; - } - return r600_context_add_block(ctx, r600_shader_constant, nreg); -} - -/* SHADER RESOURCE R600/R700 */ -static int r600_state_resource_init(struct r600_context *ctx, u32 offset) -{ - struct r600_reg r600_shader_resource[] = { - {0, 0, R_038000_RESOURCE0_WORD0}, - {0, 0, R_038004_RESOURCE0_WORD1}, - {1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), R_038008_RESOURCE0_WORD2}, - {1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), R_03800C_RESOURCE0_WORD3}, - {0, 0, R_038010_RESOURCE0_WORD4}, - {0, 0, R_038014_RESOURCE0_WORD5}, - {0, 0, R_038018_RESOURCE0_WORD6}, - }; - unsigned nreg = sizeof(r600_shader_resource)/sizeof(struct r600_reg); - - for (int i = 0; i < nreg; i++) { - r600_shader_resource[i].offset += offset; - } - return r600_context_add_block(ctx, r600_shader_resource, nreg); -} - -/* SHADER SAMPLER R600/R700 */ -static int r600_state_sampler_init(struct r600_context *ctx, u32 offset) -{ - struct r600_reg r600_shader_sampler[] = { - {0, 0, R_03C000_SQ_TEX_SAMPLER_WORD0_0}, - {0, 0, R_03C004_SQ_TEX_SAMPLER_WORD1_0}, - {0, 0, R_03C008_SQ_TEX_SAMPLER_WORD2_0}, - }; - unsigned nreg = sizeof(r600_shader_sampler)/sizeof(struct r600_reg); - - for (int i = 0; i < nreg; i++) { - r600_shader_sampler[i].offset += offset; - } - return r600_context_add_block(ctx, r600_shader_sampler, nreg); -} - -/* SHADER SAMPLER BORDER R600/R700 */ -static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset) -{ - struct r600_reg r600_shader_sampler_border[] = { - {0, 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED}, - {0, 0, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN}, - {0, 0, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE}, - {0, 0, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA}, - }; - unsigned nreg = sizeof(r600_shader_sampler_border)/sizeof(struct r600_reg); - - for (int i = 0; i < nreg; i++) { - r600_shader_sampler_border[i].offset += offset; - } - return r600_context_add_block(ctx, r600_shader_sampler_border, nreg); -} - -/* initialize */ -void r600_context_fini(struct r600_context *ctx) -{ - for (int i = 0; i < ctx->ngroups; i++) { - r600_group_fini(&ctx->groups[i]); - } - free(ctx->reloc); - free(ctx->pm4); - memset(ctx, 0, sizeof(struct r600_context)); -} - -int r600_context_init(struct r600_context *ctx, struct radeon *radeon) -{ - int r; - - memset(ctx, 0, sizeof(struct r600_context)); - ctx->radeon = radeon; - /* initialize groups */ - r = r600_group_init(&ctx->groups[R600_GROUP_CONFIG], R600_CONFIG_REG_OFFSET, R600_CONFIG_REG_END); - if (r) { - goto out_err; - } - r = r600_group_init(&ctx->groups[R600_GROUP_CTL_CONST], R600_CTL_CONST_OFFSET, R600_CTL_CONST_END); - if (r) { - goto out_err; - } - r = r600_group_init(&ctx->groups[R600_GROUP_LOOP_CONST], R600_LOOP_CONST_OFFSET, R600_LOOP_CONST_END); - if (r) { - goto out_err; - } - r = r600_group_init(&ctx->groups[R600_GROUP_BOOL_CONST], R600_BOOL_CONST_OFFSET, R600_BOOL_CONST_END); - if (r) { - goto out_err; - } - r = r600_group_init(&ctx->groups[R600_GROUP_SAMPLER], R600_SAMPLER_OFFSET, R600_SAMPLER_END); - if (r) { - goto out_err; - } - r = r600_group_init(&ctx->groups[R600_GROUP_RESOURCE], R600_RESOURCE_OFFSET, R600_RESOURCE_END); - if (r) { - goto out_err; - } - r = r600_group_init(&ctx->groups[R600_GROUP_ALU_CONST], R600_ALU_CONST_OFFSET, R600_ALU_CONST_END); - if (r) { - goto out_err; - } - r = r600_group_init(&ctx->groups[R600_GROUP_CONTEXT], R600_CONTEXT_REG_OFFSET, R600_CONTEXT_REG_END); - if (r) { - goto out_err; - } - ctx->ngroups = R600_NGROUPS; - - /* add blocks */ - r = r600_context_add_block(ctx, r600_reg_list, sizeof(r600_reg_list)/sizeof(struct r600_reg)); - if (r) - goto out_err; - - /* PS SAMPLER BORDER */ - for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) { - r = r600_state_sampler_border_init(ctx, offset); - if (r) - goto out_err; - } - - /* VS SAMPLER BORDER */ - for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) { - r = r600_state_sampler_border_init(ctx, offset); - if (r) - goto out_err; - } - /* PS SAMPLER */ - for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) { - r = r600_state_sampler_init(ctx, offset); - if (r) - goto out_err; - } - /* VS SAMPLER */ - for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) { - r = r600_state_sampler_init(ctx, offset); - if (r) - goto out_err; - } - /* PS RESOURCE */ - for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) { - r = r600_state_resource_init(ctx, offset); - if (r) - goto out_err; - } - /* VS RESOURCE */ - for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) { - r = r600_state_resource_init(ctx, offset); - if (r) - goto out_err; - } - /* PS CONSTANT */ - for (int j = 0, offset = 0; j < 256; j++, offset += 0x10) { - r = r600_state_constant_init(ctx, offset); - if (r) - goto out_err; - } - /* VS CONSTANT */ - for (int j = 0, offset = 0x1000; j < 256; j++, offset += 0x10) { - r = r600_state_constant_init(ctx, offset); - if (r) - goto out_err; - } - - /* allocate cs variables */ - ctx->nreloc = RADEON_CTX_MAX_PM4; - ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc)); - if (ctx->reloc == NULL) { - r = -ENOMEM; - goto out_err; - } - ctx->bo = calloc(ctx->nreloc, sizeof(void *)); - if (ctx->bo == NULL) { - r = -ENOMEM; - goto out_err; - } - ctx->pm4_ndwords = RADEON_CTX_MAX_PM4; - ctx->pm4 = calloc(ctx->pm4_ndwords, 4); - if (ctx->pm4 == NULL) { - r = -ENOMEM; - goto out_err; - } - return 0; -out_err: - r600_context_fini(ctx); - return r; -} - -static void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct radeon_ws_bo *bo) -{ - int i, reloc_id; - unsigned handle = radeon_ws_bo_get_handle(bo); - - assert(bo != NULL); - for (i = 0, reloc_id = -1; i < ctx->creloc; i++) { - if (ctx->reloc[i].handle == handle) { - reloc_id = i * sizeof(struct r600_reloc) / 4; - /* set PKT3 to point to proper reloc */ - *pm4 = reloc_id; - } - } - if (reloc_id == -1) { - /* add new relocation */ - if (ctx->creloc >= ctx->nreloc) { - r600_context_flush(ctx); - } - reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4; - ctx->reloc[ctx->creloc].handle = handle; - ctx->reloc[ctx->creloc].read_domain = RADEON_GEM_DOMAIN_GTT; - ctx->reloc[ctx->creloc].write_domain = RADEON_GEM_DOMAIN_GTT; - ctx->reloc[ctx->creloc].flags = 0; - radeon_ws_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo); - ctx->creloc++; - /* set PKT3 to point to proper reloc */ - *pm4 = reloc_id; - } -} - -void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state) -{ - struct r600_group *group; - struct r600_group_block *block; - - for (int i = 0; i < state->nregs; i++) { - unsigned id; - group = &ctx->groups[state->regs[i].group_id]; - id = group->offset_block_id[(state->regs[i].offset - group->start_offset) >> 2]; - block = &group->blocks[id]; - id = (state->regs[i].offset - block->start_offset) >> 2; - block->pm4[id] &= ~state->regs[i].mask; - block->pm4[id] |= state->regs[i].value; - if (block->pm4_bo_index[id]) { - /* find relocation */ - id = block->pm4_bo_index[id]; - radeon_ws_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo); - for (int j = 0; j < block->reloc[id].nreloc; j++) { - r600_context_bo_reloc(ctx, &block->pm4[block->reloc[id].bo_pm4_index[j]], - block->reloc[id].bo); - } - } - block->status |= R600_BLOCK_STATUS_ENABLED; - block->status |= R600_BLOCK_STATUS_DIRTY; - ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords; - } -} - -static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) -{ - struct r600_group_block *block; - unsigned id; - - offset -= ctx->groups[R600_GROUP_RESOURCE].start_offset; - id = ctx->groups[R600_GROUP_RESOURCE].offset_block_id[offset >> 2]; - block = &ctx->groups[R600_GROUP_RESOURCE].blocks[id]; - block->pm4[0] = state->regs[0].value; - block->pm4[1] = state->regs[1].value; - block->pm4[2] = state->regs[2].value; - block->pm4[3] = state->regs[3].value; - block->pm4[4] = state->regs[4].value; - block->pm4[5] = state->regs[5].value; - block->pm4[6] = state->regs[6].value; - radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, block->reloc[1].bo); - radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, block->reloc[2].bo); - if (state->regs[0].bo) { - /* VERTEX RESOURCE, we preted there is 2 bo to relocate so - * we have single case btw VERTEX & TEXTURE resource - */ - radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo); - radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo); - } else { - /* TEXTURE RESOURCE */ - radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo); - radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo); - } - r600_context_bo_reloc(ctx, &block->pm4[block->reloc[1].bo_pm4_index[0]], block->reloc[1].bo); - r600_context_bo_reloc(ctx, &block->pm4[block->reloc[2].bo_pm4_index[0]], block->reloc[2].bo); - block->status |= R600_BLOCK_STATUS_ENABLED; - block->status |= R600_BLOCK_STATUS_DIRTY; - ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords; -} - -void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) -{ - unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid; - - r600_context_pipe_state_set_resource(ctx, state, offset); -} - -void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) -{ - unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid; - - r600_context_pipe_state_set_resource(ctx, state, offset); -} - -static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) -{ - struct r600_group_block *block; - unsigned id; - - offset -= ctx->groups[R600_GROUP_SAMPLER].start_offset; - id = ctx->groups[R600_GROUP_SAMPLER].offset_block_id[offset >> 2]; - block = &ctx->groups[R600_GROUP_SAMPLER].blocks[id]; - block->pm4[0] = state->regs[0].value; - block->pm4[1] = state->regs[1].value; - block->pm4[2] = state->regs[2].value; - block->status |= R600_BLOCK_STATUS_ENABLED; - block->status |= R600_BLOCK_STATUS_DIRTY; - ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords; -} - -static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) -{ - struct r600_group_block *block; - unsigned id; - - offset -= ctx->groups[R600_GROUP_CONFIG].start_offset; - id = ctx->groups[R600_GROUP_CONFIG].offset_block_id[offset >> 2]; - block = &ctx->groups[R600_GROUP_CONFIG].blocks[id]; - block->pm4[0] = state->regs[3].value; - block->pm4[1] = state->regs[4].value; - block->pm4[2] = state->regs[5].value; - block->pm4[3] = state->regs[6].value; - block->status |= R600_BLOCK_STATUS_ENABLED; - block->status |= R600_BLOCK_STATUS_DIRTY; - ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords; -} - -void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) -{ - unsigned offset; - - offset = 0x0003C000 + id * 0xc; - r600_context_pipe_state_set_sampler(ctx, state, offset); - if (state->nregs > 3) { - offset = 0x0000A400 + id * 0x10; - r600_context_pipe_state_set_sampler_border(ctx, state, offset); - } -} - -void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) -{ - unsigned offset; - - offset = 0x0003C0D8 + id * 0xc; - r600_context_pipe_state_set_sampler(ctx, state, offset); - if (state->nregs > 3) { - offset = 0x0000A600 + id * 0x10; - r600_context_pipe_state_set_sampler_border(ctx, state, offset); - } -} - -static inline void r600_context_group_emit_dirty(struct r600_context *ctx, struct r600_group *group, unsigned opcode) -{ - for (int i = 0; i < group->nblocks; i++) { - struct r600_group_block *block = &group->blocks[i]; - if (block->status & R600_BLOCK_STATUS_DIRTY) { - ctx->pm4[ctx->pm4_cdwords++] = PKT3(opcode, block->nreg); - ctx->pm4[ctx->pm4_cdwords++] = (block->start_offset - group->start_offset) >> 2; - memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, block->pm4_ndwords * 4); - ctx->pm4_cdwords += block->pm4_ndwords; - block->status ^= R600_BLOCK_STATUS_DIRTY; - } - } -} - -void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw) -{ - unsigned ndwords = 9; - - if (draw->indices) { - ndwords = 13; - /* make sure there is enough relocation space before scheduling draw */ - if (ctx->creloc >= (ctx->nreloc - 1)) { - r600_context_flush(ctx); - } - } - if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) { - /* need to flush */ - r600_context_flush(ctx); - } - /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */ - if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) { - R600_ERR("context is too big to be scheduled\n"); - return; - } - /* Ok we enough room to copy packet */ - r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_CONFIG], PKT3_SET_CONFIG_REG); - r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_CONTEXT], PKT3_SET_CONTEXT_REG); - r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_ALU_CONST], PKT3_SET_ALU_CONST); - r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_SAMPLER], PKT3_SET_SAMPLER); - r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_RESOURCE], PKT3_SET_RESOURCE); - /* draw packet */ - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0); - ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type; - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0); - ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances; - if (draw->indices) { - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3); - ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset; - ctx->pm4[ctx->pm4_cdwords++] = 0; - ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices; - ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); - ctx->pm4[ctx->pm4_cdwords++] = 0; - r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices); - } else { - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1); - ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices; - ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator; - } - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0); - ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; -} - -void r600_context_flush(struct r600_context *ctx) -{ - struct drm_radeon_cs drmib; - struct drm_radeon_cs_chunk chunks[2]; - uint64_t chunk_array[2]; - struct r600_group_block *block; - int r; - - if (!ctx->pm4_cdwords) - return; - -#if 1 - /* emit cs */ - drmib.num_chunks = 2; - drmib.chunks = (uint64_t)(uintptr_t)chunk_array; - chunks[0].chunk_id = RADEON_CHUNK_ID_IB; - chunks[0].length_dw = ctx->pm4_cdwords; - chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4; - chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS; - chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4; - chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc; - chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0]; - chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1]; - r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib, - sizeof(struct drm_radeon_cs)); -#endif - /* restart */ - for (int i = 0; i < ctx->creloc; i++) { - radeon_ws_bo_reference(ctx->radeon, &ctx->bo[i], NULL); - } - ctx->creloc = 0; - ctx->pm4_dirty_cdwords = 0; - ctx->pm4_cdwords = 0; - for (int i = 0; i < ctx->ngroups; i++) { - for (int j = 0; j < ctx->groups[i].nblocks; j++) { - /* mark enabled block as dirty */ - block = &ctx->groups[i].blocks[j]; - if (block->status & R600_BLOCK_STATUS_ENABLED) { - ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords; - block->status |= R600_BLOCK_STATUS_DIRTY; - for (int k = 1; k <= block->nbo; k++) { - for (int l = 0; l < block->reloc[k].nreloc; l++) { - r600_context_bo_reloc(ctx, - &block->pm4[block->reloc[k].bo_pm4_index[l]], - block->reloc[k].bo); - } - } - } - } - } -} - -void r600_context_dump_bof(struct r600_context *ctx, const char *file) -{ - bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root; - unsigned i; - - root = device_id = bcs = blob = array = bo = size = handle = NULL; - root = bof_object(); - if (root == NULL) - goto out_err; - device_id = bof_int32(ctx->radeon->device); - if (device_id == NULL) - goto out_err; - if (bof_object_set(root, "device_id", device_id)) - goto out_err; - bof_decref(device_id); - device_id = NULL; - /* dump relocs */ - blob = bof_blob(ctx->creloc * 16, ctx->reloc); - if (blob == NULL) - goto out_err; - if (bof_object_set(root, "reloc", blob)) - goto out_err; - bof_decref(blob); - blob = NULL; - /* dump cs */ - blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4); - if (blob == NULL) - goto out_err; - if (bof_object_set(root, "pm4", blob)) - goto out_err; - bof_decref(blob); - blob = NULL; - /* dump bo */ - array = bof_array(); - if (array == NULL) - goto out_err; - for (i = 0; i < ctx->creloc; i++) { - struct radeon_bo *rbo = radeon_bo_pb_get_bo(ctx->bo[i]->pb); - bo = bof_object(); - if (bo == NULL) - goto out_err; - size = bof_int32(rbo->size); - if (size == NULL) - goto out_err; - if (bof_object_set(bo, "size", size)) - goto out_err; - bof_decref(size); - size = NULL; - handle = bof_int32(rbo->handle); - if (handle == NULL) - goto out_err; - if (bof_object_set(bo, "handle", handle)) - goto out_err; - bof_decref(handle); - handle = NULL; - radeon_bo_map(ctx->radeon, rbo); - blob = bof_blob(rbo->size, rbo->data); - radeon_bo_unmap(ctx->radeon, rbo); - if (blob == NULL) - goto out_err; - if (bof_object_set(bo, "data", blob)) - goto out_err; - bof_decref(blob); - blob = NULL; - if (bof_array_append(array, bo)) - goto out_err; - bof_decref(bo); - bo = NULL; - } - if (bof_object_set(root, "bo", array)) - goto out_err; - bof_dump_file(root, file); -out_err: - bof_decref(blob); - bof_decref(array); - bof_decref(bo); - bof_decref(size); - bof_decref(handle); - bof_decref(device_id); - bof_decref(root); -} diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h deleted file mode 100644 index 50b25a99404..00000000000 --- a/src/gallium/winsys/r600/drm/r600_states.h +++ /dev/null @@ -1,522 +0,0 @@ -/* - * Copyright © 2009 Jerome Glisse <[email protected]> - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of version 2 of the GNU General Public License - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. - */ -#ifndef R600_STATES_H -#define R600_STATES_H - -static const struct radeon_register R600_names_CONFIG[] = { - {0x00008C00, 0, 0, "SQ_CONFIG"}, - {0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"}, - {0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"}, - {0x00008C0C, 0, 0, "SQ_THREAD_RESOURCE_MGMT"}, - {0x00008C10, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"}, - {0x00008C14, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"}, - {0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"}, - {0x00009508, 0, 0, "TA_CNTL_AUX"}, - {0x00009714, 0, 0, "VC_ENHANCE"}, - {0x00009830, 0, 0, "DB_DEBUG"}, - {0x00009838, 0, 0, "DB_WATERMARKS"}, - {0x00028350, 0, 0, "SX_MISC"}, - {0x000286C8, 0, 0, "SPI_THREAD_GROUPING"}, - {0x000287A0, 0, 0, "CB_SHADER_CONTROL"}, - {0x000288A8, 0, 0, "SQ_ESGS_RING_ITEMSIZE"}, - {0x000288AC, 0, 0, "SQ_GSVS_RING_ITEMSIZE"}, - {0x000288B0, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"}, - {0x000288B4, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"}, - {0x000288B8, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"}, - {0x000288BC, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"}, - {0x000288C0, 0, 0, "SQ_FBUF_RING_ITEMSIZE"}, - {0x000288C4, 0, 0, "SQ_REDUC_RING_ITEMSIZE"}, - {0x000288C8, 0, 0, "SQ_GS_VERT_ITEMSIZE"}, - {0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"}, - {0x00028A14, 0, 0, "VGT_HOS_CNTL"}, - {0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"}, - {0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"}, - {0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"}, - {0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"}, - {0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"}, - {0x00028A2C, 0, 0, "VGT_GROUP_DECR"}, - {0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"}, - {0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"}, - {0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"}, - {0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"}, - {0x00028A40, 0, 0, "VGT_GS_MODE"}, - {0x00028A4C, 0, 0, "PA_SC_MODE_CNTL"}, - {0x00028AB0, 0, 0, "VGT_STRMOUT_EN"}, - {0x00028AB4, 0, 0, "VGT_REUSE_OFF"}, - {0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"}, - {0x00028B20, 0, 0, "VGT_STRMOUT_BUFFER_EN"}, -}; - -static const struct radeon_register R600_names_CB_CNTL[] = { - {0x00028120, 0, 0, "CB_CLEAR_RED"}, - {0x00028124, 0, 0, "CB_CLEAR_GREEN"}, - {0x00028128, 0, 0, "CB_CLEAR_BLUE"}, - {0x0002812C, 0, 0, "CB_CLEAR_ALPHA"}, - {0x0002823C, 0, 0, "CB_SHADER_MASK"}, - {0x00028238, 0, 0, "CB_TARGET_MASK"}, - {0x00028424, 0, 0, "CB_FOG_RED"}, - {0x00028428, 0, 0, "CB_FOG_GREEN"}, - {0x0002842C, 0, 0, "CB_FOG_BLUE"}, - {0x00028808, 0, 0, "CB_COLOR_CONTROL"}, - {0x00028C04, 0, 0, "PA_SC_AA_CONFIG"}, - {0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"}, - {0x00028C20, 0, 0, "PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX"}, - {0x00028C30, 0, 0, "CB_CLRCMP_CONTROL"}, - {0x00028C34, 0, 0, "CB_CLRCMP_SRC"}, - {0x00028C38, 0, 0, "CB_CLRCMP_DST"}, - {0x00028C3C, 0, 0, "CB_CLRCMP_MSK"}, - {0x00028C48, 0, 0, "PA_SC_AA_MASK"}, -}; - -static const struct radeon_register R600_names_RASTERIZER[] = { - {0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"}, - {0x00028810, 0, 0, "PA_CL_CLIP_CNTL"}, - {0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"}, - {0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"}, - {0x00028820, 0, 0, "PA_CL_NANINF_CNTL"}, - {0x00028A00, 0, 0, "PA_SU_POINT_SIZE"}, - {0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"}, - {0x00028A08, 0, 0, "PA_SU_LINE_CNTL"}, - {0x00028A0C, 0, 0, "PA_SC_LINE_STIPPLE"}, - {0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"}, - {0x00028C00, 0, 0, "PA_SC_LINE_CNTL"}, - {0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"}, - {0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"}, - {0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"}, - {0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"}, - {0x00028DF8, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"}, - {0x00028DFC, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"}, - {0x00028E00, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"}, - {0x00028E04, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"}, - {0x00028E08, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"}, - {0x00028E0C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"}, -}; - -static const struct radeon_register R600_names_VIEWPORT[] = { - {0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"}, - {0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"}, - {0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"}, - {0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"}, - {0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"}, - {0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"}, - {0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"}, - {0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"}, - {0x00028818, 0, 0, "PA_CL_VTE_CNTL"}, -}; - -static const struct radeon_register R600_names_SCISSOR[] = { - {0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"}, - {0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"}, - {0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"}, - {0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"}, - {0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"}, - {0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"}, - {0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"}, - {0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"}, - {0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"}, - {0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"}, - {0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"}, - {0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"}, - {0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"}, - {0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"}, - {0x00028230, 0, 0, "PA_SC_EDGERULE"}, - {0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"}, - {0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"}, - {0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"}, - {0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"}, -}; - -static const struct radeon_register R600_names_BLEND[] = { - {0x00028414, 0, 0, "CB_BLEND_RED"}, - {0x00028418, 0, 0, "CB_BLEND_GREEN"}, - {0x0002841C, 0, 0, "CB_BLEND_BLUE"}, - {0x00028420, 0, 0, "CB_BLEND_ALPHA"}, - {0x00028780, 0, 0, "CB_BLEND0_CONTROL"}, - {0x00028784, 0, 0, "CB_BLEND1_CONTROL"}, - {0x00028788, 0, 0, "CB_BLEND2_CONTROL"}, - {0x0002878C, 0, 0, "CB_BLEND3_CONTROL"}, - {0x00028790, 0, 0, "CB_BLEND4_CONTROL"}, - {0x00028794, 0, 0, "CB_BLEND5_CONTROL"}, - {0x00028798, 0, 0, "CB_BLEND6_CONTROL"}, - {0x0002879C, 0, 0, "CB_BLEND7_CONTROL"}, - {0x00028804, 0, 0, "CB_BLEND_CONTROL"}, -}; - -static const struct radeon_register R600_names_DSA[] = { - {0x00028028, 0, 0, "DB_STENCIL_CLEAR"}, - {0x0002802C, 0, 0, "DB_DEPTH_CLEAR"}, - {0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"}, - {0x00028430, 0, 0, "DB_STENCILREFMASK"}, - {0x00028434, 0, 0, "DB_STENCILREFMASK_BF"}, - {0x00028438, 0, 0, "SX_ALPHA_REF"}, - {0x000286E0, 0, 0, "SPI_FOG_FUNC_SCALE"}, - {0x000286E4, 0, 0, "SPI_FOG_FUNC_BIAS"}, - {0x000286DC, 0, 0, "SPI_FOG_CNTL"}, - {0x00028800, 0, 0, "DB_DEPTH_CONTROL"}, - {0x0002880C, 0, 0, "DB_SHADER_CONTROL"}, - {0x00028D0C, 0, 0, "DB_RENDER_CONTROL"}, - {0x00028D10, 0, 0, "DB_RENDER_OVERRIDE"}, - {0x00028D2C, 0, 0, "DB_SRESULTS_COMPARE_STATE1"}, - {0x00028D30, 0, 0, "DB_PRELOAD_CONTROL"}, - {0x00028D44, 0, 0, "DB_ALPHA_TO_MASK"}, -}; - -static const struct radeon_register R600_names_VS_SHADER[] = { - {0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"}, - {0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"}, - {0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"}, - {0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"}, - {0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"}, - {0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"}, - {0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"}, - {0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"}, - {0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"}, - {0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"}, - {0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"}, - {0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"}, - {0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"}, - {0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"}, - {0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"}, - {0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"}, - {0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"}, - {0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"}, - {0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"}, - {0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"}, - {0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"}, - {0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"}, - {0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"}, - {0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"}, - {0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"}, - {0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"}, - {0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"}, - {0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"}, - {0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"}, - {0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"}, - {0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"}, - {0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"}, - {0x00028614, 0, 0, "SPI_VS_OUT_ID_0"}, - {0x00028618, 0, 0, "SPI_VS_OUT_ID_1"}, - {0x0002861C, 0, 0, "SPI_VS_OUT_ID_2"}, - {0x00028620, 0, 0, "SPI_VS_OUT_ID_3"}, - {0x00028624, 0, 0, "SPI_VS_OUT_ID_4"}, - {0x00028628, 0, 0, "SPI_VS_OUT_ID_5"}, - {0x0002862C, 0, 0, "SPI_VS_OUT_ID_6"}, - {0x00028630, 0, 0, "SPI_VS_OUT_ID_7"}, - {0x00028634, 0, 0, "SPI_VS_OUT_ID_8"}, - {0x00028638, 0, 0, "SPI_VS_OUT_ID_9"}, - {0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"}, - {0x00028858, 1, 0, "SQ_PGM_START_VS"}, - {0x00028868, 0, 0, "SQ_PGM_RESOURCES_VS"}, - {0x00028894, 1, 1, "SQ_PGM_START_FS"}, - {0x000288A4, 0, 0, "SQ_PGM_RESOURCES_FS"}, - {0x000288D0, 0, 0, "SQ_PGM_CF_OFFSET_VS"}, - {0x000288DC, 0, 0, "SQ_PGM_CF_OFFSET_FS"}, -}; - -static const struct radeon_register R600_names_PS_SHADER[] = { - {0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"}, - {0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"}, - {0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"}, - {0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"}, - {0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"}, - {0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"}, - {0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"}, - {0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"}, - {0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"}, - {0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"}, - {0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"}, - {0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"}, - {0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"}, - {0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"}, - {0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"}, - {0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"}, - {0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"}, - {0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"}, - {0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"}, - {0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"}, - {0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"}, - {0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"}, - {0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"}, - {0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"}, - {0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"}, - {0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"}, - {0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"}, - {0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"}, - {0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"}, - {0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"}, - {0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"}, - {0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"}, - {0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"}, - {0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"}, - {0x000286D8, 0, 0, "SPI_INPUT_Z"}, - {0x00028840, 1, 0, "SQ_PGM_START_PS"}, - {0x00028850, 0, 0, "SQ_PGM_RESOURCES_PS"}, - {0x00028854, 0, 0, "SQ_PGM_EXPORTS_PS"}, - {0x000288CC, 0, 0, "SQ_PGM_CF_OFFSET_PS"}, -}; - -static const struct radeon_register R600_names_VS_CBUF[] = { - {0x00028180, 0, 0, "ALU_CONST_BUFFER_SIZE_VS_0"}, - {0x00028980, 1, 0, "ALU_CONST_CACHE_VS_0"}, -}; - -static const struct radeon_register R600_names_PS_CBUF[] = { - {0x00028140, 0, 0, "ALU_CONST_BUFFER_SIZE_PS_0"}, - {0x00028940, 1, 0, "ALU_CONST_CACHE_PS_0"}, -}; - -static const struct radeon_register R600_names_PS_CONSTANT[] = { - {0x00030000, 0, 0, "SQ_ALU_CONSTANT0_0"}, - {0x00030004, 0, 0, "SQ_ALU_CONSTANT1_0"}, - {0x00030008, 0, 0, "SQ_ALU_CONSTANT2_0"}, - {0x0003000C, 0, 0, "SQ_ALU_CONSTANT3_0"}, -}; - -static const struct radeon_register R600_names_VS_CONSTANT[] = { - {0x00031000, 0, 0, "SQ_ALU_CONSTANT0_256"}, - {0x00031004, 0, 0, "SQ_ALU_CONSTANT1_256"}, - {0x00031008, 0, 0, "SQ_ALU_CONSTANT2_256"}, - {0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"}, -}; - -static const struct radeon_register R600_names_UCP[] = { - {0x00028E20, 0, 0, "PA_CL_UCP0_X"}, - {0x00028E24, 0, 0, "PA_CL_UCP0_Y"}, - {0x00028E28, 0, 0, "PA_CL_UCP0_Z"}, - {0x00028E2C, 0, 0, "PA_CL_UCP0_W"}, - {0x00028E30, 0, 0, "PA_CL_UCP1_X"}, - {0x00028E34, 0, 0, "PA_CL_UCP1_Y"}, - {0x00028E38, 0, 0, "PA_CL_UCP1_Z"}, - {0x00028E3C, 0, 0, "PA_CL_UCP1_W"}, - {0x00028E40, 0, 0, "PA_CL_UCP2_X"}, - {0x00028E44, 0, 0, "PA_CL_UCP2_Y"}, - {0x00028E48, 0, 0, "PA_CL_UCP2_Z"}, - {0x00028E4C, 0, 0, "PA_CL_UCP2_W"}, - {0x00028E50, 0, 0, "PA_CL_UCP3_X"}, - {0x00028E54, 0, 0, "PA_CL_UCP3_Y"}, - {0x00028E58, 0, 0, "PA_CL_UCP3_Z"}, - {0x00028E5C, 0, 0, "PA_CL_UCP3_W"}, - {0x00028E60, 0, 0, "PA_CL_UCP4_X"}, - {0x00028E64, 0, 0, "PA_CL_UCP4_Y"}, - {0x00028E68, 0, 0, "PA_CL_UCP4_Z"}, - {0x00028E6C, 0, 0, "PA_CL_UCP4_W"}, - {0x00028E70, 0, 0, "PA_CL_UCP5_X"}, - {0x00028E74, 0, 0, "PA_CL_UCP5_Y"}, - {0x00028E78, 0, 0, "PA_CL_UCP5_Z"}, - {0x00028E7C, 0, 0, "PA_CL_UCP5_W"}, -}; - -static const struct radeon_register R600_names_PS_RESOURCE[] = { - {0x00038000, 0, 0, "RESOURCE0_WORD0"}, - {0x00038004, 0, 0, "RESOURCE0_WORD1"}, - {0x00038008, 0, 0, "RESOURCE0_WORD2"}, - {0x0003800C, 0, 0, "RESOURCE0_WORD3"}, - {0x00038010, 0, 0, "RESOURCE0_WORD4"}, - {0x00038014, 0, 0, "RESOURCE0_WORD5"}, - {0x00038018, 0, 0, "RESOURCE0_WORD6"}, -}; - -static const struct radeon_register R600_names_VS_RESOURCE[] = { - {0x00039180, 0, 0, "RESOURCE160_WORD0"}, - {0x00039184, 0, 0, "RESOURCE160_WORD1"}, - {0x00039188, 0, 0, "RESOURCE160_WORD2"}, - {0x0003918C, 0, 0, "RESOURCE160_WORD3"}, - {0x00039190, 0, 0, "RESOURCE160_WORD4"}, - {0x00039194, 0, 0, "RESOURCE160_WORD5"}, - {0x00039198, 0, 0, "RESOURCE160_WORD6"}, -}; - -static const struct radeon_register R600_names_FS_RESOURCE[] = { - {0x0003A300, 0, 0, "RESOURCE320_WORD0"}, - {0x0003A304, 0, 0, "RESOURCE320_WORD1"}, - {0x0003A308, 0, 0, "RESOURCE320_WORD2"}, - {0x0003A30C, 0, 0, "RESOURCE320_WORD3"}, - {0x0003A310, 0, 0, "RESOURCE320_WORD4"}, - {0x0003A314, 0, 0, "RESOURCE320_WORD5"}, - {0x0003A318, 0, 0, "RESOURCE320_WORD6"}, -}; - -static const struct radeon_register R600_names_GS_RESOURCE[] = { - {0x0003A4C0, 0, 0, "RESOURCE336_WORD0"}, - {0x0003A4C4, 0, 0, "RESOURCE336_WORD1"}, - {0x0003A4C8, 0, 0, "RESOURCE336_WORD2"}, - {0x0003A4CC, 0, 0, "RESOURCE336_WORD3"}, - {0x0003A4D0, 0, 0, "RESOURCE336_WORD4"}, - {0x0003A4D4, 0, 0, "RESOURCE336_WORD5"}, - {0x0003A4D8, 0, 0, "RESOURCE336_WORD6"}, -}; - -static const struct radeon_register R600_names_PS_SAMPLER[] = { - {0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"}, - {0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"}, - {0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"}, -}; - -static const struct radeon_register R600_names_VS_SAMPLER[] = { - {0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"}, - {0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"}, - {0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"}, -}; - -static const struct radeon_register R600_names_GS_SAMPLER[] = { - {0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"}, - {0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"}, - {0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"}, -}; - -static const struct radeon_register R600_names_PS_SAMPLER_BORDER[] = { - {0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"}, - {0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"}, - {0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"}, - {0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"}, -}; - -static const struct radeon_register R600_names_VS_SAMPLER_BORDER[] = { - {0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"}, - {0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"}, - {0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"}, - {0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"}, -}; - -static const struct radeon_register R600_names_GS_SAMPLER_BORDER[] = { - {0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"}, - {0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"}, - {0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"}, - {0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"}, -}; - -static const struct radeon_register R600_names_CB0[] = { - {0x00028040, 1, 0, "CB_COLOR0_BASE"}, - {0x000280A0, 0, 0, "CB_COLOR0_INFO"}, - {0x00028060, 0, 0, "CB_COLOR0_SIZE"}, - {0x00028080, 0, 0, "CB_COLOR0_VIEW"}, - {0x000280E0, 1, 0, "CB_COLOR0_FRAG"}, - {0x000280C0, 1, 0, "CB_COLOR0_TILE"}, - {0x00028100, 0, 0, "CB_COLOR0_MASK"}, -}; - -static const struct radeon_register R600_names_CB1[] = { - {0x00028044, 1, 0, "CB_COLOR1_BASE"}, - {0x000280A4, 0, 0, "CB_COLOR1_INFO"}, - {0x00028064, 0, 0, "CB_COLOR1_SIZE"}, - {0x00028084, 0, 0, "CB_COLOR1_VIEW"}, - {0x000280E4, 1, 0, "CB_COLOR1_FRAG"}, - {0x000280C4, 1, 0, "CB_COLOR1_TILE"}, - {0x00028104, 0, 0, "CB_COLOR1_MASK"}, -}; - -static const struct radeon_register R600_names_CB2[] = { - {0x00028048, 1, 0, "CB_COLOR2_BASE"}, - {0x000280A8, 0, 0, "CB_COLOR2_INFO"}, - {0x00028068, 0, 0, "CB_COLOR2_SIZE"}, - {0x00028088, 0, 0, "CB_COLOR2_VIEW"}, - {0x000280E8, 1, 0, "CB_COLOR2_FRAG"}, - {0x000280C8, 1, 0, "CB_COLOR2_TILE"}, - {0x00028108, 0, 0, "CB_COLOR2_MASK"}, -}; - -static const struct radeon_register R600_names_CB3[] = { - {0x0002804C, 1, 0, "CB_COLOR3_BASE"}, - {0x000280AC, 0, 0, "CB_COLOR3_INFO"}, - {0x0002806C, 0, 0, "CB_COLOR3_SIZE"}, - {0x0002808C, 0, 0, "CB_COLOR3_VIEW"}, - {0x000280EC, 1, 0, "CB_COLOR3_FRAG"}, - {0x000280CC, 1, 0, "CB_COLOR3_TILE"}, - {0x0002810C, 0, 0, "CB_COLOR3_MASK"}, -}; - -static const struct radeon_register R600_names_CB4[] = { - {0x00028050, 1, 0, "CB_COLOR4_BASE"}, - {0x000280B0, 0, 0, "CB_COLOR4_INFO"}, - {0x00028070, 0, 0, "CB_COLOR4_SIZE"}, - {0x00028090, 0, 0, "CB_COLOR4_VIEW"}, - {0x000280F0, 1, 0, "CB_COLOR4_FRAG"}, - {0x000280D0, 1, 0, "CB_COLOR4_TILE"}, - {0x00028110, 0, 0, "CB_COLOR4_MASK"}, -}; - -static const struct radeon_register R600_names_CB5[] = { - {0x00028054, 1, 0, "CB_COLOR5_BASE"}, - {0x000280B4, 0, 0, "CB_COLOR5_INFO"}, - {0x00028074, 0, 0, "CB_COLOR5_SIZE"}, - {0x00028094, 0, 0, "CB_COLOR5_VIEW"}, - {0x000280F4, 1, 0, "CB_COLOR5_FRAG"}, - {0x000280D4, 1, 0, "CB_COLOR5_TILE"}, - {0x00028114, 0, 0, "CB_COLOR5_MASK"}, -}; - -static const struct radeon_register R600_names_CB6[] = { - {0x00028058, 1, 0, "CB_COLOR6_BASE"}, - {0x000280B8, 0, 0, "CB_COLOR6_INFO"}, - {0x00028078, 0, 0, "CB_COLOR6_SIZE"}, - {0x00028098, 0, 0, "CB_COLOR6_VIEW"}, - {0x000280F8, 1, 0, "CB_COLOR6_FRAG"}, - {0x000280D8, 1, 0, "CB_COLOR6_TILE"}, - {0x00028118, 0, 0, "CB_COLOR6_MASK"}, -}; - -static const struct radeon_register R600_names_CB7[] = { - {0x0002805C, 1, 0, "CB_COLOR7_BASE"}, - {0x000280BC, 0, 0, "CB_COLOR7_INFO"}, - {0x0002807C, 0, 0, "CB_COLOR7_SIZE"}, - {0x0002809C, 0, 0, "CB_COLOR7_VIEW"}, - {0x000280FC, 1, 0, "CB_COLOR7_FRAG"}, - {0x000280DC, 1, 0, "CB_COLOR7_TILE"}, - {0x0002811C, 0, 0, "CB_COLOR7_MASK"}, -}; - -static const struct radeon_register R600_names_DB[] = { - {0x0002800C, 1, 0, "DB_DEPTH_BASE"}, - {0x00028000, 0, 0, "DB_DEPTH_SIZE"}, - {0x00028004, 0, 0, "DB_DEPTH_VIEW"}, - {0x00028010, 0, 0, "DB_DEPTH_INFO"}, - {0x00028D24, 0, 0, "DB_HTILE_SURFACE"}, - {0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"}, -}; - -static const struct radeon_register R600_names_VGT[] = { - {0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"}, - {0x00028400, 0, 0, "VGT_MAX_VTX_INDX"}, - {0x00028404, 0, 0, "VGT_MIN_VTX_INDX"}, - {0x00028408, 0, 0, "VGT_INDX_OFFSET"}, - {0x0002840C, 0, 0, "VGT_MULTI_PRIM_IB_RESET_INDX"}, - {0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"}, - {0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"}, - {0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"}, - {0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"}, - {0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"}, - {0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"}, -}; - -static const struct radeon_register R600_names_DRAW[] = { - {0x00008970, 0, 0, "VGT_NUM_INDICES"}, - {0x000287E4, 0, 0, "VGT_DMA_BASE_HI"}, - {0x000287E8, 1, 0, "VGT_DMA_BASE"}, - {0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"}, -}; - -static const struct radeon_register R600_names_VGT_EVENT[] = { - {0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"}, -}; - -static const struct radeon_register R600_names_CB_FLUSH[] = { -}; - -static const struct radeon_register R600_names_DB_FLUSH[] = { -}; - -#endif diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h index c5d5fe9ddfc..d91f7737af3 100644 --- a/src/gallium/winsys/r600/drm/r600d.h +++ b/src/gallium/winsys/r600/drm/r600d.h @@ -28,7 +28,7 @@ /* evergreen values */ #define EG_RESOURCE_OFFSET 0x00030000 -#define EG_RESOURCE_END 0x00030400 +#define EG_RESOURCE_END 0x00034000 #define EG_LOOP_CONST_OFFSET 0x0003A200 #define EG_LOOP_CONST_END 0x0003A26C #define EG_BOOL_CONST_OFFSET 0x0003A500 @@ -91,6 +91,7 @@ #define PKT3_SET_CTL_CONST 0x6F #define PKT3_SURFACE_BASE_UPDATE 0x73 +#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 #define EVENT_TYPE_ZPASS_DONE 0x15 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 @@ -839,6 +840,16 @@ #define R_028800_DB_DEPTH_CONTROL 0x028800 #define R_02880C_DB_SHADER_CONTROL 0x02880C #define R_028D0C_DB_RENDER_CONTROL 0x028D0C +#define S_028D0C_DEPTH_CLEAR_ENABLE(x) (((x) & 0x1) << 0) +#define S_028D0C_STENCIL_CLEAR_ENABLE(x) (((x) & 0x1) << 1) +#define S_028D0C_DEPTH_COPY_ENABLE(x) (((x) & 0x1) << 2) +#define S_028D0C_STENCIL_COPY_ENABLE(x) (((x) & 0x1) << 3) +#define S_028D0C_RESUMMARIZE_ENABLE(x) (((x) & 0x1) << 4) +#define S_028D0C_STENCIL_COMPRESS_DISABLE(x) (((x) & 0x1) << 5) +#define S_028D0C_DEPTH_COMPRESS_DISABLE(x) (((x) & 0x1) << 6) +#define S_028D0C_COPY_CENTROID(x) (((x) & 0x1) << 7) +#define S_028D0C_COPY_SAMPLE(x) (((x) & 0x1) << 8) +#define S_028D0C_R700_PERFECT_ZPASS_COUNTS(x) (((x) & 0x1) << 15) #define R_028D10_DB_RENDER_OVERRIDE 0x028D10 #define R_028D2C_DB_SRESULTS_COMPARE_STATE1 0x028D2C #define R_028D30_DB_PRELOAD_CONTROL 0x028D30 @@ -2190,4 +2201,12 @@ #define R_038014_RESOURCE0_WORD5 0x038014 #define R_038018_RESOURCE0_WORD6 0x038018 +#define R_028140_ALU_CONST_BUFFER_SIZE_PS_0 0x00028140 +#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0 0x00028180 +#define R_028940_ALU_CONST_CACHE_PS_0 0x00028940 +#define R_028980_ALU_CONST_CACHE_VS_0 0x00028980 + +#define R_03CFF0_SQ_VTX_BASE_VTX_LOC 0x03CFF0 +#define R_03CFF4_SQ_VTX_START_INST_LOC 0x03CFF4 + #endif diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c deleted file mode 100644 index f39d020559c..00000000000 --- a/src/gallium/winsys/r600/drm/radeon.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright © 2009 Jerome Glisse <[email protected]> - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of version 2 of the GNU General Public License - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. - */ -#include <stdio.h> -#include <stdlib.h> -#include <stdint.h> -#include <unistd.h> -#include <string.h> -#include <errno.h> -#include <pipebuffer/pb_bufmgr.h> -#include "xf86drm.h" -#include "radeon_priv.h" -#include "radeon_drm.h" - -enum radeon_family radeon_get_family(struct radeon *radeon) -{ - return radeon->family; -} - -void radeon_set_mem_constant(struct radeon *radeon, boolean state) -{ - radeon->use_mem_constant = state; -} - -static int radeon_get_device(struct radeon *radeon) -{ - struct drm_radeon_info info; - int r; - - radeon->device = 0; - info.request = RADEON_INFO_DEVICE_ID; - info.value = (uintptr_t)&radeon->device; - r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info, - sizeof(struct drm_radeon_info)); - return r; -} - -struct radeon *radeon_new(int fd, unsigned device) -{ - struct radeon *radeon; - int r, i, id, j, k; - - radeon = calloc(1, sizeof(*radeon)); - if (radeon == NULL) { - return NULL; - } - radeon->fd = fd; - radeon->device = device; - radeon->refcount = 1; - if (fd >= 0) { - r = radeon_get_device(radeon); - if (r) { - fprintf(stderr, "Failed to get device id\n"); - return radeon_decref(radeon); - } - } - radeon->family = radeon_family_from_device(radeon->device); - if (radeon->family == CHIP_UNKNOWN) { - fprintf(stderr, "Unknown chipset 0x%04X\n", radeon->device); - return radeon_decref(radeon); - } - switch (radeon->family) { - case CHIP_R600: - case CHIP_RV610: - case CHIP_RV630: - case CHIP_RV670: - case CHIP_RV620: - case CHIP_RV635: - case CHIP_RS780: - case CHIP_RS880: - case CHIP_RV770: - case CHIP_RV730: - case CHIP_RV710: - case CHIP_RV740: - case CHIP_CEDAR: - case CHIP_REDWOOD: - case CHIP_JUNIPER: - case CHIP_CYPRESS: - case CHIP_HEMLOCK: - if (r600_init(radeon)) { - return radeon_decref(radeon); - } - break; - case CHIP_R100: - case CHIP_RV100: - case CHIP_RS100: - case CHIP_RV200: - case CHIP_RS200: - case CHIP_R200: - case CHIP_RV250: - case CHIP_RS300: - case CHIP_RV280: - case CHIP_R300: - case CHIP_R350: - case CHIP_RV350: - case CHIP_RV380: - case CHIP_R420: - case CHIP_R423: - case CHIP_RV410: - case CHIP_RS400: - case CHIP_RS480: - case CHIP_RS600: - case CHIP_RS690: - case CHIP_RS740: - case CHIP_RV515: - case CHIP_R520: - case CHIP_RV530: - case CHIP_RV560: - case CHIP_RV570: - case CHIP_R580: - default: - fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n", - __func__, radeon->device); - break; - } - - radeon->mman = pb_malloc_bufmgr_create(); - if (!radeon->mman) - return NULL; - radeon->kman = radeon_bo_pbmgr_create(radeon); - if (!radeon->kman) - return NULL; - radeon->cman = pb_cache_manager_create(radeon->kman, 100000); - if (!radeon->cman) - return NULL; - return radeon; -} - -struct radeon *radeon_incref(struct radeon *radeon) -{ - if (radeon == NULL) - return NULL; - radeon->refcount++; - return radeon; -} - -struct radeon *radeon_decref(struct radeon *radeon) -{ - if (radeon == NULL) - return NULL; - if (--radeon->refcount > 0) { - return NULL; - } - - radeon->mman->destroy(radeon->mman); - radeon->cman->destroy(radeon->cman); - radeon->kman->destroy(radeon->kman); - drmClose(radeon->fd); - free(radeon); - return NULL; -} diff --git a/src/gallium/winsys/r600/drm/radeon_bo.c b/src/gallium/winsys/r600/drm/radeon_bo.c index 51ce8649742..14a00161c8b 100644 --- a/src/gallium/winsys/r600/drm/radeon_bo.c +++ b/src/gallium/winsys/r600/drm/radeon_bo.c @@ -29,10 +29,45 @@ #include <string.h> #include <sys/mman.h> #include <errno.h> -#include "radeon_priv.h" +#include "r600_priv.h" #include "xf86drm.h" #include "radeon_drm.h" +static int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo) +{ + struct drm_radeon_gem_mmap args; + void *ptr; + int r; + + /* Zero out args to make valgrind happy */ + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + args.offset = 0; + args.size = (uint64_t)bo->size; + r = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_MMAP, + &args, sizeof(args)); + if (r) { + fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n", + bo, bo->handle, r); + return r; + } + ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, radeon->fd, args.addr_ptr); + if (ptr == MAP_FAILED) { + fprintf(stderr, "%s failed to map bo\n", __func__); + return -errno; + } + bo->data = ptr; + + bo->map_count++; + return 0; +} + +static void radeon_bo_fixed_unmap(struct radeon *radeon, struct radeon_bo *bo) +{ + munmap(bo->data, bo->size); + bo->data = NULL; +} + struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, unsigned size, unsigned alignment, void *ptr) { @@ -60,6 +95,7 @@ struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, } bo->handle = open_arg.handle; bo->size = open_arg.size; + bo->shared = TRUE; } else { struct drm_radeon_gem_create args; @@ -79,65 +115,24 @@ struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, return NULL; } } + if (radeon_bo_fixed_map(radeon, bo)) { + R600_ERR("failed to map bo\n"); + radeon_bo_reference(radeon, &bo, NULL); + return bo; + } if (ptr) { - if (radeon_bo_map(radeon, bo)) { - fprintf(stderr, "%s failed to copy data into bo\n", __func__); - radeon_bo_reference(radeon, &bo, NULL); - return bo; - } memcpy(bo->data, ptr, size); - radeon_bo_unmap(radeon, bo); } + LIST_INITHEAD(&bo->fencedlist); return bo; } -int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo) -{ - struct drm_radeon_gem_mmap args; - void *ptr; - int r; - - if (bo->map_count != 0) { - goto success; - } - /* Zero out args to make valgrind happy */ - memset(&args, 0, sizeof(args)); - args.handle = bo->handle; - args.offset = 0; - args.size = (uint64_t)bo->size; - r = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_MMAP, - &args, sizeof(args)); - if (r) { - fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n", - bo, bo->handle, r); - return r; - } - ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, radeon->fd, args.addr_ptr); - if (ptr == MAP_FAILED) { - fprintf(stderr, "%s failed to map bo\n", __func__); - return -errno; - } - bo->data = ptr; - -success: - bo->map_count++; - - return 0; -} - -void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo) -{ - if (--bo->map_count > 0) { - return; - } - munmap(bo->data, bo->size); - bo->data = NULL; -} - static void radeon_bo_destroy(struct radeon *radeon, struct radeon_bo *bo) { struct drm_gem_close args; + LIST_DEL(&bo->fencedlist); + radeon_bo_fixed_unmap(radeon, bo); memset(&args, 0, sizeof(args)); args.handle = bo->handle; drmIoctl(radeon->fd, DRM_IOCTL_GEM_CLOSE, &args); @@ -161,6 +156,15 @@ int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo) struct drm_radeon_gem_wait_idle args; int ret; + if (!bo->fence && !bo->shared) + return 0; + + if (bo->fence <= *bo->ctx->cfence) { + LIST_DELINIT(&bo->fencedlist); + bo->fence = 0; + return 0; + } + /* Zero out args to make valgrind happy */ memset(&args, 0, sizeof(args)); args.handle = bo->handle; @@ -173,16 +177,26 @@ int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo) int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain) { - struct drm_radeon_gem_busy args; - int ret; + struct drm_radeon_gem_busy args; + int ret; + + if (!bo->shared) { + if (!bo->fence) + return 0; + if (bo->fence <= *bo->ctx->cfence) { + LIST_DELINIT(&bo->fencedlist); + bo->fence = 0; + return 0; + } + } - memset(&args, 0, sizeof(args)); - args.handle = bo->handle; - args.domain = 0; + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + args.domain = 0; - ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_BUSY, - &args, sizeof(args)); + ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_BUSY, + &args, sizeof(args)); - *domain = args.domain; - return ret; + *domain = args.domain; + return ret; } diff --git a/src/gallium/winsys/r600/drm/radeon_bo_pb.c b/src/gallium/winsys/r600/drm/radeon_bo_pb.c index 65ba96233d5..a3452027f27 100644 --- a/src/gallium/winsys/r600/drm/radeon_bo_pb.c +++ b/src/gallium/winsys/r600/drm/radeon_bo_pb.c @@ -1,10 +1,34 @@ -#include "radeon_priv.h" - -#include "util/u_inlines.h" -#include "util/u_memory.h" -#include "util/u_double_list.h" -#include "pipebuffer/pb_buffer.h" -#include "pipebuffer/pb_bufmgr.h" +/* + * Copyright 2010 Dave Airlie + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Dave Airlie + */ +#include <util/u_inlines.h> +#include <util/u_memory.h> +#include <util/u_double_list.h> +#include <pipebuffer/pb_buffer.h> +#include <pipebuffer/pb_bufmgr.h> +#include "r600_priv.h" struct radeon_bo_pb { struct pb_buffer b; @@ -53,28 +77,49 @@ radeon_bo_pb_map_internal(struct pb_buffer *_buf, unsigned flags, void *ctx) { struct radeon_bo_pb *buf = radeon_bo_pb(_buf); - - if (flags & PB_USAGE_DONTBLOCK) { - if (p_atomic_read(&buf->bo->reference.count) > 1) + struct pipe_context *pctx = ctx; + + if (flags & PB_USAGE_UNSYNCHRONIZED) { + if (!buf->bo->data && radeon_bo_map(buf->mgr->radeon, buf->bo)) { return NULL; - } - if (buf->bo->data != NULL) { + } LIST_DELINIT(&buf->maplist); return buf->bo->data; } + if (p_atomic_read(&buf->bo->reference.count) > 1) { + if (flags & PB_USAGE_DONTBLOCK) { + return NULL; + } + if (ctx) { + pctx->flush(pctx, 0, NULL); + } + } + if (flags & PB_USAGE_DONTBLOCK) { uint32_t domain; if (radeon_bo_busy(buf->mgr->radeon, buf->bo, &domain)) return NULL; + if (radeon_bo_map(buf->mgr->radeon, buf->bo)) { + return NULL; + } + goto out; } - if (p_atomic_read(&buf->bo->reference.count) > 1 && ctx) { - r600_flush_ctx(ctx); - } - if (radeon_bo_map(buf->mgr->radeon, buf->bo)) { - return NULL; + if (buf->bo->data != NULL) { + if (radeon_bo_wait(buf->mgr->radeon, buf->bo)) { + return NULL; + } + } else { + if (radeon_bo_map(buf->mgr->radeon, buf->bo)) { + return NULL; + } + if (radeon_bo_wait(buf->mgr->radeon, buf->bo)) { + radeon_bo_unmap(buf->mgr->radeon, buf->bo); + return NULL; + } } +out: LIST_DELINIT(&buf->maplist); return buf->bo->data; } @@ -158,7 +203,6 @@ radeon_bo_pb_create_buffer(struct pb_manager *_mgr, struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr); struct radeon *radeon = mgr->radeon; struct radeon_bo_pb *bo; - uint32_t domain; bo = CALLOC_STRUCT(radeon_bo_pb); if (!bo) diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c deleted file mode 100644 index 7ccb5245905..00000000000 --- a/src/gallium/winsys/r600/drm/radeon_ctx.c +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright 2010 Jerome Glisse <[email protected]> - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jerome Glisse - */ -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include "radeon_priv.h" -#include "radeon_drm.h" -#include "bof.h" - -static int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_ws_bo *bo) -{ - if (ctx->nbo >= RADEON_CTX_MAX_PM4) - return -EBUSY; - /* take a reference to the kernel bo */ - radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->nbo], radeon_bo_pb_get_bo(bo->pb)); - ctx->nbo++; - return 0; -} - -static void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement) -{ - struct radeon_cs_reloc *greloc; - unsigned i; - - placement[0] = 0; - placement[1] = 0; - greloc = (void *)(((u8 *)ctx->reloc) + reloc * 4); - for (i = 0; i < ctx->nbo; i++) { - if (ctx->bo[i]->handle == greloc->handle) { - placement[0] = greloc->read_domain | greloc->write_domain; - placement[1] = placement[0]; - return; - } - } -} - -void radeon_ctx_clear(struct radeon_ctx *ctx) -{ - for (int i = 0; i < ctx->nbo; i++) { - radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL); - } - ctx->ndwords = RADEON_CTX_MAX_PM4; - ctx->cdwords = 0; - ctx->nreloc = 0; - ctx->nbo = 0; -} - -struct radeon_ctx *radeon_ctx_init(struct radeon *radeon) -{ - struct radeon_ctx *ctx; - if (radeon == NULL) - return NULL; - ctx = calloc(1, sizeof(struct radeon_ctx)); - ctx->radeon = radeon_incref(radeon); - radeon_ctx_clear(ctx); - ctx->pm4 = malloc(RADEON_CTX_MAX_PM4 * 4); - if (ctx->pm4 == NULL) { - radeon_ctx_fini(ctx); - return NULL; - } - ctx->reloc = malloc(sizeof(struct radeon_cs_reloc) * RADEON_CTX_MAX_PM4); - if (ctx->reloc == NULL) { - radeon_ctx_fini(ctx); - return NULL; - } - ctx->bo = calloc(sizeof(void *), RADEON_CTX_MAX_PM4); - if (ctx->bo == NULL) { - radeon_ctx_fini(ctx); - return NULL; - } - return ctx; -} - -void radeon_ctx_fini(struct radeon_ctx *ctx) -{ - unsigned i; - - if (ctx == NULL) - return; - - for (i = 0; i < ctx->nbo; i++) { - radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL); - } - ctx->radeon = radeon_decref(ctx->radeon); - free(ctx->bo); - free(ctx->pm4); - free(ctx->reloc); - free(ctx); -} - -static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *state) -{ - unsigned i, j; - int r; - struct radeon_bo *state_bo; - if (state == NULL) - return 0; - for (i = 0; i < state->nbo; i++) { - for (j = 0; j < ctx->nbo; j++) { - state_bo = radeon_bo_pb_get_bo(state->bo[i]->pb); - if (state_bo == ctx->bo[j]) - break; - } - if (j == ctx->nbo) { - r = radeon_ctx_set_bo_new(ctx, state->bo[i]); - if (r) - return r; - } - } - return 0; -} - - -int radeon_ctx_submit(struct radeon_ctx *ctx) -{ - struct drm_radeon_cs drmib; - struct drm_radeon_cs_chunk chunks[2]; - uint64_t chunk_array[2]; - int r = 0; - - if (!ctx->cdwords) - return 0; - - radeon_bo_pbmgr_flush_maps(ctx->radeon->kman); -#if 0 - for (r = 0; r < ctx->cdwords; r++) { - fprintf(stderr, "0x%08X\n", ctx->pm4[r]); - } -#endif - drmib.num_chunks = 2; - drmib.chunks = (uint64_t)(uintptr_t)chunk_array; - chunks[0].chunk_id = RADEON_CHUNK_ID_IB; - chunks[0].length_dw = ctx->cdwords; - chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4; - chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS; - chunks[1].length_dw = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4; - chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc; - chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0]; - chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1]; -#if 1 - r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib, - sizeof(struct drm_radeon_cs)); -#endif - return r; -} - -static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_ws_bo *bo, - unsigned id, unsigned *placement) -{ - unsigned i; - unsigned bo_handle = radeon_ws_bo_get_handle(bo); - - for (i = 0; i < ctx->nreloc; i++) { - if (ctx->reloc[i].handle == bo_handle) { - ctx->pm4[id] = i * sizeof(struct radeon_cs_reloc) / 4; - return 0; - } - } - if (ctx->nreloc >= RADEON_CTX_MAX_PM4) { - return -EBUSY; - } - ctx->reloc[ctx->nreloc].handle = bo_handle; - ctx->reloc[ctx->nreloc].read_domain = placement[0] | placement [1]; - ctx->reloc[ctx->nreloc].write_domain = placement[0] | placement [1]; - ctx->reloc[ctx->nreloc].flags = 0; - ctx->pm4[id] = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4; - ctx->nreloc++; - return 0; -} - -static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state *state) -{ - unsigned i, rid, bid, cid; - int r; - - if (state == NULL) - return 0; - if (state->cpm4 > ctx->ndwords) { - return -EBUSY; - } - memcpy(&ctx->pm4[ctx->cdwords], state->pm4, state->cpm4 * 4); - for (i = 0; i < state->nreloc; i++) { - rid = state->reloc_pm4_id[i]; - bid = state->reloc_bo_id[i]; - cid = ctx->cdwords + rid; - r = radeon_ctx_reloc(ctx, state->bo[bid], cid, - &state->placement[bid * 2]); - if (r) { - fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->stype->stype); - return r; - } - } - ctx->cdwords += state->cpm4; - ctx->ndwords -= state->cpm4; - return 0; -} - -int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state) -{ - int r = 0; - - /* !!! ONLY ACCEPT QUERY STATE HERE !!! */ - r = radeon_state_pm4(state); - if (r) - return r; - /* BEGIN/END query are balanced in the same cs so account for END - * END query when scheduling BEGIN query - */ - switch (state->stype->stype) { - case R600_STATE_QUERY_BEGIN: - /* is there enough place for begin & end */ - if ((state->cpm4 * 2) > ctx->ndwords) - return -EBUSY; - ctx->ndwords -= state->cpm4; - break; - case R600_STATE_QUERY_END: - ctx->ndwords += state->cpm4; - break; - default: - return -EINVAL; - } - return radeon_ctx_state_schedule(ctx, state); -} - -int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw) -{ - unsigned previous_cdwords; - int r = 0; - int i; - - for (i = 0; i < ctx->radeon->max_states; i++) { - r = radeon_ctx_state_bo(ctx, draw->state[i]); - if (r) - return r; - } - previous_cdwords = ctx->cdwords; - for (i = 0; i < ctx->radeon->max_states; i++) { - if (draw->state[i]) { - r = radeon_ctx_state_schedule(ctx, draw->state[i]); - if (r) { - ctx->cdwords = previous_cdwords; - return r; - } - } - } - - return 0; -} - -#if 0 -int radeon_ctx_pm4(struct radeon_ctx *ctx) -{ - unsigned i; - int r; - - free(ctx->pm4); - ctx->cpm4 = 0; - ctx->pm4 = malloc(ctx->draw_cpm4 * 4); - if (ctx->pm4 == NULL) - return -EINVAL; - for (i = 0, ctx->id = 0; i < ctx->nstate; i++) { - } - if (ctx->id != ctx->draw_cpm4) { - fprintf(stderr, "%s miss predicted pm4 size %d for %d\n", - __func__, ctx->draw_cpm4, ctx->id); - return -EINVAL; - } - ctx->cpm4 = ctx->draw_cpm4; - return 0; -} -#endif - -void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file) -{ - bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root; - unsigned i; - unsigned bo_size; - root = device_id = bcs = blob = array = bo = size = handle = NULL; - root = bof_object(); - if (root == NULL) - goto out_err; - device_id = bof_int32(ctx->radeon->device); - if (device_id == NULL) - return; - if (bof_object_set(root, "device_id", device_id)) - goto out_err; - bof_decref(device_id); - device_id = NULL; - /* dump relocs */ - blob = bof_blob(ctx->nreloc * 16, ctx->reloc); - if (blob == NULL) - goto out_err; - if (bof_object_set(root, "reloc", blob)) - goto out_err; - bof_decref(blob); - blob = NULL; - /* dump cs */ - blob = bof_blob(ctx->cdwords * 4, ctx->pm4); - if (blob == NULL) - goto out_err; - if (bof_object_set(root, "pm4", blob)) - goto out_err; - bof_decref(blob); - blob = NULL; - /* dump bo */ - array = bof_array(); - if (array == NULL) - goto out_err; - for (i = 0; i < ctx->nbo; i++) { - bo = bof_object(); - if (bo == NULL) - goto out_err; - bo_size = ctx->bo[i]->size; - size = bof_int32(bo_size); - if (size == NULL) - goto out_err; - if (bof_object_set(bo, "size", size)) - goto out_err; - bof_decref(size); - size = NULL; - handle = bof_int32(ctx->bo[i]->handle); - if (handle == NULL) - goto out_err; - if (bof_object_set(bo, "handle", handle)) - goto out_err; - bof_decref(handle); - handle = NULL; - radeon_bo_map(ctx->radeon, ctx->bo[i]); - blob = bof_blob(bo_size, ctx->bo[i]->data); - radeon_bo_unmap(ctx->radeon, ctx->bo[i]); - if (blob == NULL) - goto out_err; - if (bof_object_set(bo, "data", blob)) - goto out_err; - bof_decref(blob); - blob = NULL; - if (bof_array_append(array, bo)) - goto out_err; - bof_decref(bo); - bo = NULL; - } - if (bof_object_set(root, "bo", array)) - goto out_err; - bof_dump_file(root, file); -out_err: - bof_decref(blob); - bof_decref(array); - bof_decref(bo); - bof_decref(size); - bof_decref(handle); - bof_decref(device_id); - bof_decref(root); -} diff --git a/src/gallium/winsys/r600/drm/radeon_draw.c b/src/gallium/winsys/r600/drm/radeon_draw.c deleted file mode 100644 index a1269014958..00000000000 --- a/src/gallium/winsys/r600/drm/radeon_draw.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2010 Jerome Glisse <[email protected]> - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jerome Glisse - */ -#include <stdlib.h> -#include <string.h> -#include <errno.h> -#include "radeon_priv.h" - -/* - * draw functions - */ -int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon) -{ - draw->radeon = radeon; - draw->state = calloc(radeon->max_states, sizeof(void*)); - if (draw->state == NULL) - return -ENOMEM; - return 0; -} - -void radeon_draw_bind(struct radeon_draw *draw, struct radeon_state *state) -{ - if (state == NULL) - return; - draw->state[state->state_id] = state; -} - -void radeon_draw_unbind(struct radeon_draw *draw, struct radeon_state *state) -{ - if (state == NULL) - return; - if (draw->state[state->state_id] == state) { - draw->state[state->state_id] = NULL; - } -} diff --git a/src/gallium/winsys/r600/drm/radeon_pciid.c b/src/gallium/winsys/r600/drm/radeon_pciid.c index dd6156d585e..08cc1c41e37 100644 --- a/src/gallium/winsys/r600/drm/radeon_pciid.c +++ b/src/gallium/winsys/r600/drm/radeon_pciid.c @@ -24,7 +24,7 @@ * Jerome Glisse */ #include <stdlib.h> -#include "radeon_priv.h" +#include "r600.h" struct pci_id { unsigned vendor; diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h deleted file mode 100644 index c284f6aa7d1..00000000000 --- a/src/gallium/winsys/r600/drm/radeon_priv.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright © 2009 Jerome Glisse <[email protected]> - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of version 2 of the GNU General Public License - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. - */ -#ifndef RADEON_PRIV_H -#define RADEON_PRIV_H - -#include <stdint.h> -#include "xf86drm.h" -#include "xf86drmMode.h" -#include <errno.h> -#include "radeon.h" - -#include "pipe/p_compiler.h" -#include "util/u_inlines.h" -#include "pipe/p_defines.h" - -struct radeon; -struct radeon_ctx; - - -/* - * radeon functions - */ -typedef int (*radeon_state_pm4_t)(struct radeon_state *state); -struct radeon_register { - unsigned offset; - unsigned need_reloc; - unsigned bo_id; - char name[64]; -}; - -struct radeon_bo { - struct pipe_reference reference; - unsigned handle; - unsigned size; - unsigned alignment; - unsigned map_count; - void *data; -}; - -struct radeon_sub_type { - int shader_type; - const struct radeon_register *regs; - unsigned nstates; -}; - -struct radeon_stype_info { - unsigned stype; - unsigned num; - unsigned stride; - radeon_state_pm4_t pm4; - struct radeon_sub_type reginfo[R600_SHADER_MAX]; - unsigned base_id; - unsigned npm4; -}; - -struct radeon_ctx { - struct radeon *radeon; - u32 *pm4; - int cdwords; - int ndwords; - unsigned nreloc; - struct radeon_cs_reloc *reloc; - unsigned nbo; - struct radeon_bo **bo; -}; - -struct radeon { - int fd; - int refcount; - unsigned device; - unsigned family; - unsigned nstype; - struct radeon_stype_info *stype; - unsigned max_states; - boolean use_mem_constant; /* true for evergreen */ - struct pb_manager *mman; /* malloc manager */ - struct pb_manager *kman; /* kernel bo manager */ - struct pb_manager *cman; /* cached bo manager */ -}; - -struct radeon_ws_bo { - struct pipe_reference reference; - struct pb_buffer *pb; -}; - -extern struct radeon *radeon_new(int fd, unsigned device); -extern struct radeon *radeon_incref(struct radeon *radeon); -extern struct radeon *radeon_decref(struct radeon *radeon); -extern unsigned radeon_family_from_device(unsigned device); -extern int radeon_is_family_compatible(unsigned family1, unsigned family2); - -/* - * r600/r700 context functions - */ -extern int r600_init(struct radeon *radeon); -extern int r600_ctx_draw(struct radeon_ctx *ctx); -extern int r600_ctx_next_reloc(struct radeon_ctx *ctx, unsigned *reloc); - -/* - * radeon state functions - */ -extern u32 radeon_state_register_get(struct radeon_state *state, unsigned offset); -extern int radeon_state_register_set(struct radeon_state *state, unsigned offset, u32 value); -extern struct radeon_state *radeon_state_duplicate(struct radeon_state *state); -extern int radeon_state_replace_always(struct radeon_state *ostate, struct radeon_state *nstate); -extern int radeon_state_pm4_generic(struct radeon_state *state); -extern int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id); - -/* - * radeon draw functions - */ -extern int radeon_draw_pm4(struct radeon_draw *draw); - -/* ws bo winsys only */ -unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *bo); -unsigned radeon_ws_bo_get_size(struct radeon_ws_bo *bo); - -/* bo */ -struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, - unsigned size, unsigned alignment, void *ptr); -int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo); -void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo); -void radeon_bo_reference(struct radeon *radeon, struct radeon_bo **dst, - struct radeon_bo *src); -int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo); -int radeon_bo_busy(struct radeon *radeon, struct radeon_bo *bo, uint32_t *domain); - -/* pipebuffer kernel bo manager */ -struct pb_manager *radeon_bo_pbmgr_create(struct radeon *radeon); -struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf); -void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr); -struct pb_buffer *radeon_bo_pb_create_buffer_from_handle(struct pb_manager *_mgr, - uint32_t handle); - -#endif diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c deleted file mode 100644 index b237b39c2b1..00000000000 --- a/src/gallium/winsys/r600/drm/radeon_state.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2010 Jerome Glisse <[email protected]> - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jerome Glisse - */ -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <errno.h> -#include "radeon_priv.h" - -/* - * state core functions - */ -int radeon_state_init(struct radeon_state *state, struct radeon *radeon, u32 stype, u32 id, u32 shader_type) -{ - struct radeon_stype_info *found = NULL; - int i, j, shader_index = -1; - - /* traverse the stype array */ - for (i = 0; i < radeon->nstype; i++) { - /* if the type doesn't match, if the shader doesn't match */ - if (stype != radeon->stype[i].stype) - continue; - if (shader_type) { - for (j = 0; j < 4; j++) { - if (radeon->stype[i].reginfo[j].shader_type == shader_type) { - shader_index = j; - break; - } - } - if (shader_index == -1) - continue; - } else { - if (radeon->stype[i].reginfo[0].shader_type) - continue; - else - shader_index = 0; - } - if (id > radeon->stype[i].num) - continue; - - found = &radeon->stype[i]; - break; - } - - if (!found) { - fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type); - return -EINVAL; - } - - memset(state, 0, sizeof(struct radeon_state)); - state->stype = found; - state->state_id = state->stype->num * shader_index + state->stype->base_id + id; - state->radeon = radeon; - state->id = id; - state->shader_index = shader_index; - state->refcount = 1; - state->npm4 = found->npm4; - state->nstates = found->reginfo[shader_index].nstates; - return 0; -} - -int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type) -{ - struct radeon_stype_info *found = NULL; - int i, j, shader_index = -1; - - if (state == NULL) - return 0; - /* traverse the stype array */ - for (i = 0; i < state->radeon->nstype; i++) { - /* if the type doesn't match, if the shader doesn't match */ - if (stype != state->radeon->stype[i].stype) - continue; - if (shader_type) { - for (j = 0; j < 4; j++) { - if (state->radeon->stype[i].reginfo[j].shader_type == shader_type) { - shader_index = j; - break; - } - } - if (shader_index == -1) - continue; - } else { - if (state->radeon->stype[i].reginfo[0].shader_type) - continue; - else - shader_index = 0; - } - if (id > state->radeon->stype[i].num) - continue; - - found = &state->radeon->stype[i]; - break; - } - - if (!found) { - fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type); - return -EINVAL; - } - - if (found->reginfo[shader_index].nstates != state->nstates) { - fprintf(stderr, "invalid type change from (%d %d %d) to (%d %d %d)\n", - state->stype->stype, state->id, state->shader_index, stype, id, shader_index); - } - - state->stype = found; - state->id = id; - state->shader_index = shader_index; - state->state_id = state->stype->num * shader_index + state->stype->base_id + id; - return radeon_state_pm4(state); -} - -void radeon_state_fini(struct radeon_state *state) -{ - unsigned i; - - if (state == NULL) - return NULL; - for (i = 0; i < state->nbo; i++) { - radeon_ws_bo_reference(state->radeon, &state->bo[i], NULL); - } - memset(state, 0, sizeof(struct radeon_state)); -} - -int radeon_state_replace_always(struct radeon_state *ostate, - struct radeon_state *nstate) -{ - return 1; -} - -int radeon_state_pm4_generic(struct radeon_state *state) -{ - return -EINVAL; -} - -static u32 crc32(void *d, size_t len) -{ - u16 *data = (uint16_t*)d; - u32 sum1 = 0xffff, sum2 = 0xffff; - - len = len >> 1; - while (len) { - unsigned tlen = len > 360 ? 360 : len; - len -= tlen; - do { - sum1 += *data++; - sum2 += sum1; - } while (--tlen); - sum1 = (sum1 & 0xffff) + (sum1 >> 16); - sum2 = (sum2 & 0xffff) + (sum2 >> 16); - } - /* Second reduction step to reduce sums to 16 bits */ - sum1 = (sum1 & 0xffff) + (sum1 >> 16); - sum2 = (sum2 & 0xffff) + (sum2 >> 16); - return sum2 << 16 | sum1; -} - -int radeon_state_pm4(struct radeon_state *state) -{ - int r; - - if (state == NULL) - return 0; - state->cpm4 = 0; - r = state->stype->pm4(state); - if (r) { - fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n", - __func__, state->stype->stype, state->id); - return r; - } - state->pm4_crc = crc32(state->pm4, state->cpm4 * 4); - return 0; -} - -int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id) -{ - state->reloc_pm4_id[state->nreloc] = id; - state->reloc_bo_id[state->nreloc] = bo_id; - state->nreloc++; - return 0; -} diff --git a/src/gallium/winsys/r600/drm/radeon_ws_bo.c b/src/gallium/winsys/r600/drm/radeon_ws_bo.c deleted file mode 100644 index 8114526a14a..00000000000 --- a/src/gallium/winsys/r600/drm/radeon_ws_bo.c +++ /dev/null @@ -1,106 +0,0 @@ -#include <malloc.h> -#include <pipe/p_screen.h> -#include <pipebuffer/pb_bufmgr.h> -#include "radeon_priv.h" - -struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon, - unsigned size, unsigned alignment, unsigned usage) -{ - struct radeon_ws_bo *ws_bo = calloc(1, sizeof(struct radeon_ws_bo)); - struct pb_desc desc; - struct pb_manager *man; - - desc.alignment = alignment; - desc.usage = usage; - - if (!radeon->use_mem_constant && (usage & PIPE_BIND_CONSTANT_BUFFER)) { - man = radeon->mman; - } else if (usage & (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) - man = radeon->cman; - else - man = radeon->kman; - - ws_bo->pb = man->create_buffer(man, size, &desc); - if (ws_bo->pb == NULL) { - free(ws_bo); - return NULL; - } - - pipe_reference_init(&ws_bo->reference, 1); - return ws_bo; -} - -struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon, - unsigned handle) -{ - struct radeon_ws_bo *ws_bo = calloc(1, sizeof(struct radeon_ws_bo)); - - ws_bo->pb = radeon_bo_pb_create_buffer_from_handle(radeon->kman, handle); - if (!ws_bo->pb) { - free(ws_bo); - return NULL; - } - pipe_reference_init(&ws_bo->reference, 1); - return ws_bo; -} - -void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo, unsigned usage, void *ctx) -{ - return pb_map(bo->pb, usage, ctx); -} - -void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo) -{ - pb_unmap(bo->pb); -} - -static void radeon_ws_bo_destroy(struct radeon *radeon, struct radeon_ws_bo *bo) -{ - if (bo->pb) - pb_reference(&bo->pb, NULL); - free(bo); -} - -void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst, - struct radeon_ws_bo *src) -{ - struct radeon_ws_bo *old = *dst; - - if (pipe_reference(&(*dst)->reference, &src->reference)) { - radeon_ws_bo_destroy(radeon, old); - } - *dst = src; -} - -int radeon_ws_bo_wait(struct radeon *radeon, struct radeon_ws_bo *pb_bo) -{ - /* TODO */ - struct radeon_bo *bo; - bo = radeon_bo_pb_get_bo(pb_bo->pb); - if (!bo) - return 0; - radeon_bo_wait(radeon, bo); - return 0; -} - -unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *pb_bo) -{ - struct radeon_bo *bo; - - bo = radeon_bo_pb_get_bo(pb_bo->pb); - if (!bo) - return 0; - - return bo->handle; -} - -unsigned radeon_ws_bo_get_size(struct radeon_ws_bo *pb_bo) -{ - struct radeon_bo *bo; - - bo = radeon_bo_pb_get_bo(pb_bo->pb); - if (!bo) - return 0; - - return bo->size; -} |