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authorJerome Glisse <[email protected]>2010-09-17 10:41:50 -0400
committerJerome Glisse <[email protected]>2010-09-17 10:49:05 -0400
commitfd266ec62ca772a8551d2d7922d718d9d84bdf07 (patch)
tree1f664adfe2d523149885a4c19b0a240841053454 /src/gallium/winsys/r600/drm/r600d.h
parentd80bed15660e784a405c467be1ded8266d8ffc48 (diff)
r600g: alternative command stream building from context
Winsys context build a list of register block a register block is a set of consecutive register that will be emited together in the same pm4 packet (the various r600_block* are there to provide basic grouping that try to take advantage of states that are linked together) Some consecutive register are emited each in a different block, for instance the various cb[0-7]_base. At winsys context creation, the list of block is created & an index into the list of block. So to find into which block a register is in you simply use the register offset and lookup the block index. Block are grouped together into group which are the various pkt3 group of config, context, resource, Pipe state build a list of register each state want to modify, beside register value it also give a register mask so only subpart of a register can be updated by a given pipe state (the oring is in the winsys) There is no prebuild register list or define for each pipe state. Once pipe state are built they are bound to the winsys context. Each of this functions will go through the list of register and will find into which block each reg falls and will update the value of the block with proper masking (vs/ps resource/constant are specialized variant with somewhat limited capabilities). Each block modified by r600_context_pipe_state_set* is marked as dirty and we update a count of dwords needed to emit all dirty state so far. r600_context_pipe_state_set* should be call only when pipe context change some of the state (thus when pipe bind state or set state) Then to draw primitive you make a call to r600_context_draw void r600_context_draw(struct r600_context *ctx, struct r600_draw *draw) It will check if there is enough dwords in current cs buffer and if not will flush. Once there is enough room it will copy packet from dirty block and then add the draw packet3 to initiate the draw. The flush will send the current cs, reset the count of dwords to 0 and remark all states that are enabled as dirty and recompute the number of dwords needed to send the current context. Signed-off-by: Jerome Glisse <[email protected]>
Diffstat (limited to 'src/gallium/winsys/r600/drm/r600d.h')
-rw-r--r--src/gallium/winsys/r600/drm/r600d.h77
1 files changed, 68 insertions, 9 deletions
diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
index 05f31571f42..c5d5fe9ddfc 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -26,6 +26,15 @@
#ifndef R600D_H
#define R600D_H
+/* evergreen values */
+#define EG_RESOURCE_OFFSET 0x00030000
+#define EG_RESOURCE_END 0x00030400
+#define EG_LOOP_CONST_OFFSET 0x0003A200
+#define EG_LOOP_CONST_END 0x0003A26C
+#define EG_BOOL_CONST_OFFSET 0x0003A500
+#define EG_BOOL_CONST_END 0x0003A506
+
+
#define R600_CONFIG_REG_OFFSET 0X00008000
#define R600_CONFIG_REG_END 0X0000AC00
#define R600_CONTEXT_REG_OFFSET 0X00028000
@@ -43,15 +52,6 @@
#define R600_BOOL_CONST_OFFSET 0X0003E380
#define R600_BOOL_CONST_END 0X00040000
-/* evergreen values */
-#define EG_RESOURCE_OFFSET 0x00030000
-#define EG_RESOURCE_END 0x00030400
-#define EG_LOOP_CONST_OFFSET 0x0003A200
-#define EG_LOOP_CONST_END 0x0003A26C
-#define EG_BOOL_CONST_OFFSET 0x0003A500
-#define EG_BOOL_CONST_END 0x0003A506
-
-
#define PKT3_NOP 0x10
#define PKT3_INDIRECT_BUFFER_END 0x17
#define PKT3_SET_PREDICATION 0x20
@@ -939,6 +939,13 @@
#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13)
#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
#define C_028080_SLICE_MAX 0xFF001FFF
+#define R_028084_CB_COLOR1_VIEW 0x028084
+#define R_028088_CB_COLOR2_VIEW 0x028088
+#define R_02808C_CB_COLOR3_VIEW 0x02808C
+#define R_028090_CB_COLOR4_VIEW 0x028090
+#define R_028094_CB_COLOR5_VIEW 0x028094
+#define R_028098_CB_COLOR6_VIEW 0x028098
+#define R_02809C_CB_COLOR7_VIEW 0x02809C
#define R_028100_CB_COLOR0_MASK 0x028100
#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)
#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)
@@ -946,6 +953,13 @@
#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)
#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)
#define C_028100_FMASK_TILE_MAX 0x00000FFF
+#define R_028104_CB_COLOR1_MASK 0x028104
+#define R_028108_CB_COLOR2_MASK 0x028108
+#define R_02810C_CB_COLOR3_MASK 0x02810C
+#define R_028110_CB_COLOR4_MASK 0x028110
+#define R_028114_CB_COLOR5_MASK 0x028114
+#define R_028118_CB_COLOR6_MASK 0x028118
+#define R_02811C_CB_COLOR7_MASK 0x02811C
#define R_028040_CB_COLOR0_BASE 0x028040
#define S_028040_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
#define G_028040_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
@@ -954,10 +968,24 @@
#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
#define C_0280E0_BASE_256B 0x00000000
+#define R_0280E4_CB_COLOR1_FRAG 0x0280E4
+#define R_0280E8_CB_COLOR2_FRAG 0x0280E8
+#define R_0280EC_CB_COLOR3_FRAG 0x0280EC
+#define R_0280F0_CB_COLOR4_FRAG 0x0280F0
+#define R_0280F4_CB_COLOR5_FRAG 0x0280F4
+#define R_0280F8_CB_COLOR6_FRAG 0x0280F8
+#define R_0280FC_CB_COLOR7_FRAG 0x0280FC
#define R_0280C0_CB_COLOR0_TILE 0x0280C0
#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
#define C_0280C0_BASE_256B 0x00000000
+#define R_0280C4_CB_COLOR1_TILE 0x0280C4
+#define R_0280C8_CB_COLOR2_TILE 0x0280C8
+#define R_0280CC_CB_COLOR3_TILE 0x0280CC
+#define R_0280D0_CB_COLOR4_TILE 0x0280D0
+#define R_0280D4_CB_COLOR5_TILE 0x0280D4
+#define R_0280D8_CB_COLOR6_TILE 0x0280D8
+#define R_0280DC_CB_COLOR7_TILE 0x0280DC
#define R_028808_CB_COLOR_CONTROL 0x028808
#define S_028808_FOG_ENABLE(x) (((x) & 0x1) << 0)
#define G_028808_FOG_ENABLE(x) (((x) >> 0) & 0x1)
@@ -2130,5 +2158,36 @@
#define C_03000C_W 0x00000000
#define R_0287E4_VGT_DMA_BASE_HI 0x0287E4
#define R_0287E8_VGT_DMA_BASE 0x0287E8
+#define R_028E20_PA_CL_UCP0_X 0x028E20
+#define R_028E24_PA_CL_UCP0_Y 0x028E24
+#define R_028E28_PA_CL_UCP0_Z 0x028E28
+#define R_028E2C_PA_CL_UCP0_W 0x028E2C
+#define R_028E30_PA_CL_UCP1_X 0x028E30
+#define R_028E34_PA_CL_UCP1_Y 0x028E34
+#define R_028E38_PA_CL_UCP1_Z 0x028E38
+#define R_028E3C_PA_CL_UCP1_W 0x028E3C
+#define R_028E40_PA_CL_UCP2_X 0x028E40
+#define R_028E44_PA_CL_UCP2_Y 0x028E44
+#define R_028E48_PA_CL_UCP2_Z 0x028E48
+#define R_028E4C_PA_CL_UCP2_W 0x028E4C
+#define R_028E50_PA_CL_UCP3_X 0x028E50
+#define R_028E54_PA_CL_UCP3_Y 0x028E54
+#define R_028E58_PA_CL_UCP3_Z 0x028E58
+#define R_028E5C_PA_CL_UCP3_W 0x028E5C
+#define R_028E60_PA_CL_UCP4_X 0x028E60
+#define R_028E64_PA_CL_UCP4_Y 0x028E64
+#define R_028E68_PA_CL_UCP4_Z 0x028E68
+#define R_028E6C_PA_CL_UCP4_W 0x028E6C
+#define R_028E70_PA_CL_UCP5_X 0x028E70
+#define R_028E74_PA_CL_UCP5_Y 0x028E74
+#define R_028E78_PA_CL_UCP5_Z 0x028E78
+#define R_028E7C_PA_CL_UCP5_W 0x028E7C
+#define R_038000_RESOURCE0_WORD0 0x038000
+#define R_038004_RESOURCE0_WORD1 0x038004
+#define R_038008_RESOURCE0_WORD2 0x038008
+#define R_03800C_RESOURCE0_WORD3 0x03800C
+#define R_038010_RESOURCE0_WORD4 0x038010
+#define R_038014_RESOURCE0_WORD5 0x038014
+#define R_038018_RESOURCE0_WORD6 0x038018
#endif